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Merge git://www.denx.de/git/u-boot into fdt-cmd
[people/ms/u-boot.git] / cpu / mpc5xxx / fec.c
1 /*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
7 */
8
9 #include <common.h>
10 #include <mpc5xxx.h>
11 #include <malloc.h>
12 #include <net.h>
13 #include <miiphy.h>
14 #include "sdma.h"
15 #include "fec.h"
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 /* #define DEBUG 0x28 */
20
21 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
22 defined(CONFIG_MPC5xxx_FEC)
23
24 #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
25 #error "CONFIG_MII has to be defined!"
26 #endif
27
28 #if (DEBUG & 0x60)
29 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
30 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
31 #endif /* DEBUG */
32
33 #if (DEBUG & 0x40)
34 static uint32 local_crc32(char *string, unsigned int crc_value, int len);
35 #endif
36
37 typedef struct {
38 uint8 data[1500]; /* actual data */
39 int length; /* actual length */
40 int used; /* buffer in use or not */
41 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
42 } NBUF;
43
44 int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
45 int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
46
47 /********************************************************************/
48 #if (DEBUG & 0x2)
49 static void mpc5xxx_fec_phydump (char *devname)
50 {
51 uint16 phyStatus, i;
52 uint8 phyAddr = CONFIG_PHY_ADDR;
53 uint8 reg_mask[] = {
54 #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
55 /* regs to print: 0...7, 16...19, 21, 23, 24 */
56 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
57 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
58 #else
59 /* regs to print: 0...8, 16...20 */
60 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
61 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
62 #endif
63 };
64
65 for (i = 0; i < 32; i++) {
66 if (reg_mask[i]) {
67 miiphy_read(devname, phyAddr, i, &phyStatus);
68 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
69 }
70 }
71 }
72 #endif
73
74 /********************************************************************/
75 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
76 {
77 int ix;
78 char *data;
79 static int once = 0;
80
81 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
82 if (!once) {
83 data = (char *)malloc(FEC_MAX_PKT_SIZE);
84 if (data == NULL) {
85 printf ("RBD INIT FAILED\n");
86 return -1;
87 }
88 fec->rbdBase[ix].dataPointer = (uint32)data;
89 }
90 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
91 fec->rbdBase[ix].dataLength = 0;
92 }
93 once ++;
94
95 /*
96 * have the last RBD to close the ring
97 */
98 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
99 fec->rbdIndex = 0;
100
101 return 0;
102 }
103
104 /********************************************************************/
105 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
106 {
107 int ix;
108
109 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
110 fec->tbdBase[ix].status = 0;
111 }
112
113 /*
114 * Have the last TBD to close the ring
115 */
116 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
117
118 /*
119 * Initialize some indices
120 */
121 fec->tbdIndex = 0;
122 fec->usedTbdIndex = 0;
123 fec->cleanTbdNum = FEC_TBD_NUM;
124 }
125
126 /********************************************************************/
127 static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
128 {
129 /*
130 * Reset buffer descriptor as empty
131 */
132 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
133 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
134 else
135 pRbd->status = FEC_RBD_EMPTY;
136
137 pRbd->dataLength = 0;
138
139 /*
140 * Now, we have an empty RxBD, restart the SmartDMA receive task
141 */
142 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
143
144 /*
145 * Increment BD count
146 */
147 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
148 }
149
150 /********************************************************************/
151 static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
152 {
153 volatile FEC_TBD *pUsedTbd;
154
155 #if (DEBUG & 0x1)
156 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
157 fec->cleanTbdNum, fec->usedTbdIndex);
158 #endif
159
160 /*
161 * process all the consumed TBDs
162 */
163 while (fec->cleanTbdNum < FEC_TBD_NUM) {
164 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
165 if (pUsedTbd->status & FEC_TBD_READY) {
166 #if (DEBUG & 0x20)
167 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
168 #endif
169 return;
170 }
171
172 /*
173 * clean this buffer descriptor
174 */
175 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
176 pUsedTbd->status = FEC_TBD_WRAP;
177 else
178 pUsedTbd->status = 0;
179
180 /*
181 * update some indeces for a correct handling of the TBD ring
182 */
183 fec->cleanTbdNum++;
184 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
185 }
186 }
187
188 /********************************************************************/
189 static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
190 {
191 uint8 currByte; /* byte for which to compute the CRC */
192 int byte; /* loop - counter */
193 int bit; /* loop - counter */
194 uint32 crc = 0xffffffff; /* initial value */
195
196 /*
197 * The algorithm used is the following:
198 * we loop on each of the six bytes of the provided address,
199 * and we compute the CRC by left-shifting the previous
200 * value by one position, so that each bit in the current
201 * byte of the address may contribute the calculation. If
202 * the latter and the MSB in the CRC are different, then
203 * the CRC value so computed is also ex-ored with the
204 * "polynomium generator". The current byte of the address
205 * is also shifted right by one bit at each iteration.
206 * This is because the CRC generatore in hardware is implemented
207 * as a shift-register with as many ex-ores as the radixes
208 * in the polynomium. This suggests that we represent the
209 * polynomiumm itself as a 32-bit constant.
210 */
211 for (byte = 0; byte < 6; byte++) {
212 currByte = mac[byte];
213 for (bit = 0; bit < 8; bit++) {
214 if ((currByte & 0x01) ^ (crc & 0x01)) {
215 crc >>= 1;
216 crc = crc ^ 0xedb88320;
217 } else {
218 crc >>= 1;
219 }
220 currByte >>= 1;
221 }
222 }
223
224 crc = crc >> 26;
225
226 /*
227 * Set individual hash table register
228 */
229 if (crc >= 32) {
230 fec->eth->iaddr1 = (1 << (crc - 32));
231 fec->eth->iaddr2 = 0;
232 } else {
233 fec->eth->iaddr1 = 0;
234 fec->eth->iaddr2 = (1 << crc);
235 }
236
237 /*
238 * Set physical address
239 */
240 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
241 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
242 }
243
244 /********************************************************************/
245 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
246 {
247 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
248 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
249
250 #if (DEBUG & 0x1)
251 printf ("mpc5xxx_fec_init... Begin\n");
252 #endif
253
254 /*
255 * Initialize RxBD/TxBD rings
256 */
257 mpc5xxx_fec_rbd_init(fec);
258 mpc5xxx_fec_tbd_init(fec);
259
260 /*
261 * Clear FEC-Lite interrupt event register(IEVENT)
262 */
263 fec->eth->ievent = 0xffffffff;
264
265 /*
266 * Set interrupt mask register
267 */
268 fec->eth->imask = 0x00000000;
269
270 /*
271 * Set FEC-Lite receive control register(R_CNTRL):
272 */
273 if (fec->xcv_type == SEVENWIRE) {
274 /*
275 * Frame length=1518; 7-wire mode
276 */
277 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
278 } else {
279 /*
280 * Frame length=1518; MII mode;
281 */
282 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
283 }
284
285 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
286 if (fec->xcv_type != SEVENWIRE) {
287 /*
288 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
289 * and do not drop the Preamble.
290 */
291 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
292 }
293
294 /*
295 * Set Opcode/Pause Duration Register
296 */
297 fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */
298
299 /*
300 * Set Rx FIFO alarm and granularity value
301 */
302 fec->eth->rfifo_cntrl = 0x0c000000
303 | (fec->eth->rfifo_cntrl & ~0x0f000000);
304 fec->eth->rfifo_alarm = 0x0000030c;
305 #if (DEBUG & 0x22)
306 if (fec->eth->rfifo_status & 0x00700000 ) {
307 printf("mpc5xxx_fec_init() RFIFO error\n");
308 }
309 #endif
310
311 /*
312 * Set Tx FIFO granularity value
313 */
314 fec->eth->tfifo_cntrl = 0x0c000000
315 | (fec->eth->tfifo_cntrl & ~0x0f000000);
316 #if (DEBUG & 0x2)
317 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
318 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
319 #endif
320
321 /*
322 * Set transmit fifo watermark register(X_WMRK), default = 64
323 */
324 fec->eth->tfifo_alarm = 0x00000080;
325 fec->eth->x_wmrk = 0x2;
326
327 /*
328 * Set individual address filter for unicast address
329 * and set physical address registers.
330 */
331 mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
332
333 /*
334 * Set multicast address filter
335 */
336 fec->eth->gaddr1 = 0x00000000;
337 fec->eth->gaddr2 = 0x00000000;
338
339 /*
340 * Turn ON cheater FSM: ????
341 */
342 fec->eth->xmit_fsm = 0x03000000;
343
344 #if defined(CONFIG_MPC5200)
345 /*
346 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
347 * work w/ the current receive task.
348 */
349 sdma->PtdCntrl |= 0x00000001;
350 #endif
351
352 /*
353 * Set priority of different initiators
354 */
355 sdma->IPR0 = 7; /* always */
356 sdma->IPR3 = 6; /* Eth RX */
357 sdma->IPR4 = 5; /* Eth Tx */
358
359 /*
360 * Clear SmartDMA task interrupt pending bits
361 */
362 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
363
364 /*
365 * Initialize SmartDMA parameters stored in SRAM
366 */
367 *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
368 *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
369 *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
370 *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
371
372 /*
373 * Enable FEC-Lite controller
374 */
375 fec->eth->ecntrl |= 0x00000006;
376
377 #if (DEBUG & 0x2)
378 if (fec->xcv_type != SEVENWIRE)
379 mpc5xxx_fec_phydump (dev->name);
380 #endif
381
382 /*
383 * Enable SmartDMA receive task
384 */
385 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
386
387 #if (DEBUG & 0x1)
388 printf("mpc5xxx_fec_init... Done \n");
389 #endif
390
391 return 1;
392 }
393
394 /********************************************************************/
395 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
396 {
397 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
398 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
399
400 #if (DEBUG & 0x1)
401 printf ("mpc5xxx_fec_init_phy... Begin\n");
402 #endif
403
404 /*
405 * Initialize GPIO pins
406 */
407 if (fec->xcv_type == SEVENWIRE) {
408 /* 10MBit with 7-wire operation */
409 #if defined(CONFIG_TOTAL5200)
410 /* 7-wire and USB2 on Ethernet */
411 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
412 #else /* !CONFIG_TOTAL5200 */
413 /* 7-wire only */
414 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
415 #endif /* CONFIG_TOTAL5200 */
416 } else {
417 /* 100MBit with MD operation */
418 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
419 }
420
421 /*
422 * Clear FEC-Lite interrupt event register(IEVENT)
423 */
424 fec->eth->ievent = 0xffffffff;
425
426 /*
427 * Set interrupt mask register
428 */
429 fec->eth->imask = 0x00000000;
430
431 if (fec->xcv_type != SEVENWIRE) {
432 /*
433 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
434 * and do not drop the Preamble.
435 */
436 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
437 }
438
439 if (fec->xcv_type != SEVENWIRE) {
440 /*
441 * Initialize PHY(LXT971A):
442 *
443 * Generally, on power up, the LXT971A reads its configuration
444 * pins to check for forced operation, If not cofigured for
445 * forced operation, it uses auto-negotiation/parallel detection
446 * to automatically determine line operating conditions.
447 * If the PHY device on the other side of the link supports
448 * auto-negotiation, the LXT971A auto-negotiates with it
449 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
450 * support auto-negotiation, the LXT971A automatically detects
451 * the presence of either link pulses(10Mbps PHY) or Idle
452 * symbols(100Mbps) and sets its operating conditions accordingly.
453 *
454 * When auto-negotiation is controlled by software, the following
455 * steps are recommended.
456 *
457 * Note:
458 * The physical address is dependent on hardware configuration.
459 *
460 */
461 int timeout = 1;
462 uint16 phyStatus;
463
464 /*
465 * Reset PHY, then delay 300ns
466 */
467 miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
468 udelay(1000);
469
470 #if defined(CONFIG_UC101)
471 /* Set the LED configuration Register for the UC101 Board */
472 miiphy_write(dev->name, phyAddr, 0x14, 0x4122);
473 #endif
474 if (fec->xcv_type == MII10) {
475 /*
476 * Force 10Base-T, FDX operation
477 */
478 #if (DEBUG & 0x2)
479 printf("Forcing 10 Mbps ethernet link... ");
480 #endif
481 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
482 /*
483 miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
484 */
485 miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
486
487 timeout = 20;
488 do { /* wait for link status to go down */
489 udelay(10000);
490 if ((timeout--) == 0) {
491 #if (DEBUG & 0x2)
492 printf("hmmm, should not have waited...");
493 #endif
494 break;
495 }
496 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
497 #if (DEBUG & 0x2)
498 printf("=");
499 #endif
500 } while ((phyStatus & 0x0004)); /* !link up */
501
502 timeout = 1000;
503 do { /* wait for link status to come back up */
504 udelay(10000);
505 if ((timeout--) == 0) {
506 printf("failed. Link is down.\n");
507 break;
508 }
509 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
510 #if (DEBUG & 0x2)
511 printf("+");
512 #endif
513 } while (!(phyStatus & 0x0004)); /* !link up */
514
515 #if (DEBUG & 0x2)
516 printf ("done.\n");
517 #endif
518 } else { /* MII100 */
519 /*
520 * Set the auto-negotiation advertisement register bits
521 */
522 miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
523
524 /*
525 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
526 */
527 miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
528
529 /*
530 * Wait for AN completion
531 */
532 timeout = 5000;
533 do {
534 udelay(1000);
535
536 if ((timeout--) == 0) {
537 #if (DEBUG & 0x2)
538 printf("PHY auto neg 0 failed...\n");
539 #endif
540 return -1;
541 }
542
543 if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
544 #if (DEBUG & 0x2)
545 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
546 #endif
547 return -1;
548 }
549 } while (!(phyStatus & 0x0004));
550
551 #if (DEBUG & 0x2)
552 printf("PHY auto neg complete! \n");
553 #endif
554 }
555
556 }
557
558 #if (DEBUG & 0x2)
559 if (fec->xcv_type != SEVENWIRE)
560 mpc5xxx_fec_phydump (dev->name);
561 #endif
562
563
564 #if (DEBUG & 0x1)
565 printf("mpc5xxx_fec_init_phy... Done \n");
566 #endif
567
568 return 1;
569 }
570
571 /********************************************************************/
572 static void mpc5xxx_fec_halt(struct eth_device *dev)
573 {
574 #if defined(CONFIG_MPC5200)
575 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
576 #endif
577 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
578 int counter = 0xffff;
579
580 #if (DEBUG & 0x2)
581 if (fec->xcv_type != SEVENWIRE)
582 mpc5xxx_fec_phydump (dev->name);
583 #endif
584
585 /*
586 * mask FEC chip interrupts
587 */
588 fec->eth->imask = 0;
589
590 /*
591 * issue graceful stop command to the FEC transmitter if necessary
592 */
593 fec->eth->x_cntrl |= 0x00000001;
594
595 /*
596 * wait for graceful stop to register
597 */
598 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
599
600 /*
601 * Disable SmartDMA tasks
602 */
603 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
604 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
605
606 #if defined(CONFIG_MPC5200)
607 /*
608 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
609 * done. It doesn't work w/ the current receive task.
610 */
611 sdma->PtdCntrl &= ~0x00000001;
612 #endif
613
614 /*
615 * Disable the Ethernet Controller
616 */
617 fec->eth->ecntrl &= 0xfffffffd;
618
619 /*
620 * Clear FIFO status registers
621 */
622 fec->eth->rfifo_status &= 0x00700000;
623 fec->eth->tfifo_status &= 0x00700000;
624
625 fec->eth->reset_cntrl = 0x01000000;
626
627 /*
628 * Issue a reset command to the FEC chip
629 */
630 fec->eth->ecntrl |= 0x1;
631
632 /*
633 * wait at least 16 clock cycles
634 */
635 udelay(10);
636
637 #if (DEBUG & 0x3)
638 printf("Ethernet task stopped\n");
639 #endif
640 }
641
642 #if (DEBUG & 0x60)
643 /********************************************************************/
644
645 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
646 {
647 uint16 phyAddr = CONFIG_PHY_ADDR;
648 uint16 phyStatus;
649
650 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
651 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
652
653 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
654 printf("\nphyStatus: 0x%04x\n", phyStatus);
655 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
656 printf("ievent: 0x%08x\n", fec->eth->ievent);
657 printf("x_status: 0x%08x\n", fec->eth->x_status);
658 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
659
660 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
661 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
662 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
663 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
664 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
665 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
666 }
667 }
668
669 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
670 {
671 uint16 phyAddr = CONFIG_PHY_ADDR;
672 uint16 phyStatus;
673
674 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
675 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
676
677 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
678 printf("\nphyStatus: 0x%04x\n", phyStatus);
679 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
680 printf("ievent: 0x%08x\n", fec->eth->ievent);
681 printf("x_status: 0x%08x\n", fec->eth->x_status);
682 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
683
684 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
685 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
686 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
687 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
688 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
689 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
690 }
691 }
692 #endif /* DEBUG */
693
694 /********************************************************************/
695
696 static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
697 int data_length)
698 {
699 /*
700 * This routine transmits one frame. This routine only accepts
701 * 6-byte Ethernet addresses.
702 */
703 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
704 volatile FEC_TBD *pTbd;
705
706 #if (DEBUG & 0x20)
707 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
708 tfifo_print(dev->name, fec);
709 #endif
710
711 /*
712 * Clear Tx BD ring at first
713 */
714 mpc5xxx_fec_tbd_scrub(fec);
715
716 /*
717 * Check for valid length of data.
718 */
719 if ((data_length > 1500) || (data_length <= 0)) {
720 return -1;
721 }
722
723 /*
724 * Check the number of vacant TxBDs.
725 */
726 if (fec->cleanTbdNum < 1) {
727 #if (DEBUG & 0x20)
728 printf("No available TxBDs ...\n");
729 #endif
730 return -1;
731 }
732
733 /*
734 * Get the first TxBD to send the mac header
735 */
736 pTbd = &fec->tbdBase[fec->tbdIndex];
737 pTbd->dataLength = data_length;
738 pTbd->dataPointer = (uint32)eth_data;
739 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
740 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
741
742 #if (DEBUG & 0x100)
743 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
744 #endif
745
746 /*
747 * Kick the MII i/f
748 */
749 if (fec->xcv_type != SEVENWIRE) {
750 uint16 phyStatus;
751 miiphy_read(dev->name, 0, 0x1, &phyStatus);
752 }
753
754 /*
755 * Enable SmartDMA transmit task
756 */
757
758 #if (DEBUG & 0x20)
759 tfifo_print(dev->name, fec);
760 #endif
761 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
762 #if (DEBUG & 0x20)
763 tfifo_print(dev->name, fec);
764 #endif
765 #if (DEBUG & 0x8)
766 printf( "+" );
767 #endif
768
769 fec->cleanTbdNum -= 1;
770
771 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
772 printf ("smartDMA ethernet Tx task enabled\n");
773 #endif
774 /*
775 * wait until frame is sent .
776 */
777 while (pTbd->status & FEC_TBD_READY) {
778 udelay(10);
779 #if (DEBUG & 0x8)
780 printf ("TDB status = %04x\n", pTbd->status);
781 #endif
782 }
783
784 return 0;
785 }
786
787
788 /********************************************************************/
789 static int mpc5xxx_fec_recv(struct eth_device *dev)
790 {
791 /*
792 * This command pulls one frame from the card
793 */
794 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
795 volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
796 unsigned long ievent;
797 int frame_length, len = 0;
798 NBUF *frame;
799 uchar buff[FEC_MAX_PKT_SIZE];
800
801 #if (DEBUG & 0x1)
802 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
803 #endif
804 #if (DEBUG & 0x8)
805 printf( "-" );
806 #endif
807
808 /*
809 * Check if any critical events have happened
810 */
811 ievent = fec->eth->ievent;
812 fec->eth->ievent = ievent;
813 if (ievent & 0x20060000) {
814 /* BABT, Rx/Tx FIFO errors */
815 mpc5xxx_fec_halt(dev);
816 mpc5xxx_fec_init(dev, NULL);
817 return 0;
818 }
819 if (ievent & 0x80000000) {
820 /* Heartbeat error */
821 fec->eth->x_cntrl |= 0x00000001;
822 }
823 if (ievent & 0x10000000) {
824 /* Graceful stop complete */
825 if (fec->eth->x_cntrl & 0x00000001) {
826 mpc5xxx_fec_halt(dev);
827 fec->eth->x_cntrl &= ~0x00000001;
828 mpc5xxx_fec_init(dev, NULL);
829 }
830 }
831
832 if (!(pRbd->status & FEC_RBD_EMPTY)) {
833 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
834 ((pRbd->dataLength - 4) > 14)) {
835
836 /*
837 * Get buffer address and size
838 */
839 frame = (NBUF *)pRbd->dataPointer;
840 frame_length = pRbd->dataLength - 4;
841
842 #if (DEBUG & 0x20)
843 {
844 int i;
845 printf("recv data hdr:");
846 for (i = 0; i < 14; i++)
847 printf("%x ", *(frame->head + i));
848 printf("\n");
849 }
850 #endif
851 /*
852 * Fill the buffer and pass it to upper layers
853 */
854 memcpy(buff, frame->head, 14);
855 memcpy(buff + 14, frame->data, frame_length);
856 NetReceive(buff, frame_length);
857 len = frame_length;
858 }
859 /*
860 * Reset buffer descriptor as empty
861 */
862 mpc5xxx_fec_rbd_clean(fec, pRbd);
863 }
864 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
865 return len;
866 }
867
868
869 /********************************************************************/
870 int mpc5xxx_fec_initialize(bd_t * bis)
871 {
872 mpc5xxx_fec_priv *fec;
873 struct eth_device *dev;
874 char *tmp, *end;
875 char env_enetaddr[6];
876 int i;
877
878 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
879 dev = (struct eth_device *)malloc(sizeof(*dev));
880 memset(dev, 0, sizeof *dev);
881
882 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
883 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
884 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
885 #if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \
886 defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
887 defined(CONFIG_JUPITER) || defined(CONFIG_MCC200) || \
888 defined(CONFIG_MOTIONPRO)|| defined(CONFIG_O2DNT) || \
889 defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
890 defined(CONFIG_TQM5200) || defined(CONFIG_UC101) || \
891 defined(CONFIG_V38B)
892 # ifndef CONFIG_FEC_10MBIT
893 fec->xcv_type = MII100;
894 # else
895 fec->xcv_type = MII10;
896 # endif
897 #elif defined(CONFIG_TOTAL5200)
898 fec->xcv_type = SEVENWIRE;
899 #else
900 #error fec->xcv_type not initialized.
901 #endif
902
903 dev->priv = (void *)fec;
904 dev->iobase = MPC5XXX_FEC;
905 dev->init = mpc5xxx_fec_init;
906 dev->halt = mpc5xxx_fec_halt;
907 dev->send = mpc5xxx_fec_send;
908 dev->recv = mpc5xxx_fec_recv;
909
910 sprintf(dev->name, "FEC ETHERNET");
911 eth_register(dev);
912
913 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
914 miiphy_register (dev->name,
915 fec5xxx_miiphy_read, fec5xxx_miiphy_write);
916 #endif
917
918 /*
919 * Try to set the mac address now. The fec mac address is
920 * a garbage after reset. When not using fec for booting
921 * the Linux fec driver will try to work with this garbage.
922 */
923 tmp = getenv("ethaddr");
924 if (tmp) {
925 for (i=0; i<6; i++) {
926 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
927 if (tmp)
928 tmp = (*end) ? end+1 : end;
929 }
930 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
931 }
932
933 mpc5xxx_fec_init_phy(dev, bis);
934
935 return 1;
936 }
937
938 /* MII-interface related functions */
939 /********************************************************************/
940 int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
941 {
942 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
943 uint32 reg; /* convenient holder for the PHY register */
944 uint32 phy; /* convenient holder for the PHY */
945 int timeout = 0xffff;
946
947 /*
948 * reading from any PHY's register is done by properly
949 * programming the FEC's MII data register.
950 */
951 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
952 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
953
954 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
955
956 /*
957 * wait for the related interrupt
958 */
959 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
960
961 if (timeout == 0) {
962 #if (DEBUG & 0x2)
963 printf ("Read MDIO failed...\n");
964 #endif
965 return -1;
966 }
967
968 /*
969 * clear mii interrupt bit
970 */
971 eth->ievent = 0x00800000;
972
973 /*
974 * it's now safe to read the PHY's register
975 */
976 *retVal = (uint16) eth->mii_data;
977
978 return 0;
979 }
980
981 /********************************************************************/
982 int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
983 {
984 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
985 uint32 reg; /* convenient holder for the PHY register */
986 uint32 phy; /* convenient holder for the PHY */
987 int timeout = 0xffff;
988
989 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
990 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
991
992 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
993 FEC_MII_DATA_TA | phy | reg | data);
994
995 /*
996 * wait for the MII interrupt
997 */
998 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
999
1000 if (timeout == 0) {
1001 #if (DEBUG & 0x2)
1002 printf ("Write MDIO failed...\n");
1003 #endif
1004 return -1;
1005 }
1006
1007 /*
1008 * clear MII interrupt bit
1009 */
1010 eth->ievent = 0x00800000;
1011
1012 return 0;
1013 }
1014
1015 #if (DEBUG & 0x40)
1016 static uint32 local_crc32(char *string, unsigned int crc_value, int len)
1017 {
1018 int i;
1019 char c;
1020 unsigned int crc, count;
1021
1022 /*
1023 * crc32 algorithm
1024 */
1025 /*
1026 * crc = 0xffffffff; * The initialized value should be 0xffffffff
1027 */
1028 crc = crc_value;
1029
1030 for (i = len; --i >= 0;) {
1031 c = *string++;
1032 for (count = 0; count < 8; count++) {
1033 if ((c & 0x01) ^ (crc & 0x01)) {
1034 crc >>= 1;
1035 crc = crc ^ 0xedb88320;
1036 } else {
1037 crc >>= 1;
1038 }
1039 c >>= 1;
1040 }
1041 }
1042
1043 /*
1044 * In big endian system, do byte swaping for crc value
1045 */
1046 /**/ return crc;
1047 }
1048 #endif /* DEBUG */
1049
1050 #endif /* CONFIG_MPC5xxx_FEC */
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