cpu/mpc5xxx/pci_mpc5200.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25
  26 #if defined(CONFIG_PCI) && defined(CONFIG_MPC5200)
  27
  28 #include <asm/processor.h>
  29 #include <asm/io.h>
  30 #include <pci.h>
  31 #include <mpc5xxx.h>
  32
  33 /* System RAM mapped over PCI */
  34 #define CONFIG_PCI_MEMORY_BUS   CFG_SDRAM_BASE
  35 #define CONFIG_PCI_MEMORY_PHYS  CFG_SDRAM_BASE
  36 #define CONFIG_PCI_MEMORY_SIZE  (1024 * 1024 * 1024)
  37
  38 /* PCIIWCR bit fields */
  39 #define IWCR_MEM        (0 << 3)
  40 #define IWCR_IO         (1 << 3)
  41 #define IWCR_READ       (0 << 1)
  42 #define IWCR_READLINE   (1 << 1)
  43 #define IWCR_READMULT   (2 << 1)
  44 #define IWCR_EN         (1 << 0)
  45
  46 static int mpc5200_read_config_dword(struct pci_controller *hose,
  47                               pci_dev_t dev, int offset, u32* value)
  48 {
  49         *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
  50         eieio();
  51         *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
  52         eieio();
  53         *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
  54         return 0;
  55 }
  56
  57 static int mpc5200_write_config_dword(struct pci_controller *hose,
  58                               pci_dev_t dev, int offset, u32 value)
  59 {
  60         *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
  61         eieio();
  62         out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
  63         eieio();
  64         *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
  65         return 0;
  66 }
  67
  68 void pci_mpc5xxx_init (struct pci_controller *hose)
  69 {
  70         hose->first_busno = 0;
  71         hose->last_busno = 0xff;
  72
  73         /* System space */
  74         pci_set_region(hose->regions + 0,
  75                        CONFIG_PCI_MEMORY_BUS,
  76                        CONFIG_PCI_MEMORY_PHYS,
  77                        CONFIG_PCI_MEMORY_SIZE,
  78                        PCI_REGION_MEM | PCI_REGION_MEMORY);
  79
  80         /* PCI memory space */
  81         pci_set_region(hose->regions + 1,
  82                        CONFIG_PCI_MEM_BUS,
  83                        CONFIG_PCI_MEM_PHYS,
  84                        CONFIG_PCI_MEM_SIZE,
  85                        PCI_REGION_MEM);
  86
  87         /* PCI IO space */
  88         pci_set_region(hose->regions + 2,
  89                        CONFIG_PCI_IO_BUS,
  90                        CONFIG_PCI_IO_PHYS,
  91                        CONFIG_PCI_IO_SIZE,
  92                        PCI_REGION_IO);
  93
  94         hose->region_count = 3;
  95
  96         pci_register_hose(hose);
  97
  98         /* GPIO Multiplexing - enable PCI */
  99         *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
 100
 101         /* Set host bridge as pci master and enable memory decoding */
 102         *(vu_long *)MPC5XXX_PCI_CMD |=
 103                 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 104
 105         /* Set maximum latency timer */
 106         *(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
 107
 108         /* Set cache line size */
 109         *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
 110                 (CFG_CACHELINE_SIZE / 4);
 111
 112         /* Map MBAR to PCI space */
 113         *(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
 114         *(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1;
 115
 116         /* Map RAM to PCI space */
 117         *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
 118         *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
 119
 120         /* Enable snooping for RAM */
 121         *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
 122         *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d;
 123
 124         /* Park XLB on PCI */
 125         *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
 126         *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
 127
 128         /* Enable piplining */
 129         *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
 130
 131         /* Disable interrupts from PCI controller */
 132         *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
 133         *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
 134
 135         /* Disable initiator windows */
 136         *(vu_long *)MPC5XXX_PCI_IWCR = 0;
 137
 138         /* Map PCI memory to physical space */
 139         *(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
 140                 (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
 141                 (CONFIG_PCI_MEM_BUS >> 16);
 142         *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24;
 143
 144         /* Map PCI I/O to physical space */
 145         *(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS |
 146                 (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) |
 147                 (CONFIG_PCI_IO_BUS >> 16);
 148         *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16;
 149
 150         /* Reset the PCI bus */
 151         *(vu_long *)MPC5XXX_PCI_GSCR |= 1;
 152         udelay(1000);
 153         *(vu_long *)MPC5XXX_PCI_GSCR &= ~1;
 154         udelay(1000);
 155
 156         pci_set_ops(hose,
 157                 pci_hose_read_config_byte_via_dword,
 158                 pci_hose_read_config_word_via_dword,
 159                 mpc5200_read_config_dword,
 160                 pci_hose_write_config_byte_via_dword,
 161                 pci_hose_write_config_word_via_dword,
 162                 mpc5200_write_config_dword);
 163
 164         udelay(1000);
 165
 166 #ifdef CONFIG_PCI_SCAN_SHOW
 167         printf("PCI:   Bus Dev VenId DevId Class Int\n");
 168 #endif
 169
 170         hose->last_busno = pci_hose_scan(hose);
 171 }
 172 #endif /* CONFIG_PCI && CONFIG_MPC5200 */