cpu/mpc8220/cpu_init.c

   1 /*
   2  * (C) Copyright 2000-2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc8220.h>
  26
  27 /*
  28  * Breath some life into the CPU...
  29  *
  30  * Set up the memory map,
  31  * initialize a bunch of registers.
  32  */
  33 void cpu_init_f (void)
  34 {
  35         DECLARE_GLOBAL_DATA_PTR;
  36
  37         volatile flexbus8220_t *flexbus = (volatile flexbus8220_t *) MMAP_FB;
  38         volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG;
  39         volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB;
  40
  41         /* Pointer is writable since we allocated a register for it */
  42         gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
  43
  44         /* Clear initial global data */
  45         memset ((void *) gd, 0, sizeof (gd_t));
  46
  47         /* Clear all port configuration */
  48         portcfg->pcfg0 = 0;
  49         portcfg->pcfg1 = 0;
  50         portcfg->pcfg2 = 0;
  51         portcfg->pcfg3 = 0;
  52         portcfg->pcfg2 = CFG_GP1_PORT2_CONFIG;
  53         portcfg->pcfg3 = CFG_PCI_PORT3_CONFIG | CFG_GP2_PORT3_CONFIG;
  54
  55         /*
  56          * Flexbus Controller: configure chip selects and enable them
  57          */
  58 #if defined (CFG_CS0_BASE)
  59         flexbus->csar0 = CFG_CS0_BASE;
  60
  61 /* Sorcery-C can hang-up after CTRL reg initialization */
  62 #if defined (CFG_CS0_CTRL)
  63         flexbus->cscr0 = CFG_CS0_CTRL;
  64 #endif
  65         flexbus->csmr0 = ((CFG_CS0_MASK - 1) & 0xffff0000) | 1;
  66         __asm__ volatile ("sync");
  67 #endif
  68 #if defined (CFG_CS1_BASE)
  69         flexbus->csar1 = CFG_CS1_BASE;
  70         flexbus->cscr1 = CFG_CS1_CTRL;
  71         flexbus->csmr1 = ((CFG_CS1_MASK - 1) & 0xffff0000) | 1;
  72         __asm__ volatile ("sync");
  73 #endif
  74 #if defined (CFG_CS2_BASE)
  75         flexbus->csar2 = CFG_CS2_BASE;
  76         flexbus->cscr2 = CFG_CS2_CTRL;
  77         flexbus->csmr2 = ((CFG_CS2_MASK - 1) & 0xffff0000) | 1;
  78         portcfg->pcfg3 |= CFG_CS2_PORT3_CONFIG;
  79         __asm__ volatile ("sync");
  80 #endif
  81 #if defined (CFG_CS3_BASE)
  82         flexbus->csar3 = CFG_CS3_BASE;
  83         flexbus->cscr3 = CFG_CS3_CTRL;
  84         flexbus->csmr3 = ((CFG_CS3_MASK - 1) & 0xffff0000) | 1;
  85         portcfg->pcfg3 |= CFG_CS3_PORT3_CONFIG;
  86         __asm__ volatile ("sync");
  87 #endif
  88 #if defined (CFG_CS4_BASE)
  89         flexbus->csar4 = CFG_CS4_BASE;
  90         flexbus->cscr4 = CFG_CS4_CTRL;
  91         flexbus->csmr4 = ((CFG_CS4_MASK - 1) & 0xffff0000) | 1;
  92         portcfg->pcfg3 |= CFG_CS4_PORT3_CONFIG;
  93         __asm__ volatile ("sync");
  94 #endif
  95 #if defined (CFG_CS5_BASE)
  96         flexbus->csar5 = CFG_CS5_BASE;
  97         flexbus->cscr5 = CFG_CS5_CTRL;
  98         flexbus->csmr5 = ((CFG_CS5_MASK - 1) & 0xffff0000) | 1;
  99         portcfg->pcfg3 |= CFG_CS5_PORT3_CONFIG;
 100         __asm__ volatile ("sync");
 101 #endif
 102
 103         /* This section of the code cannot place in cpu_init_r(),
 104            it will cause the system to hang */
 105         /* enable timebase */
 106         xlbarb->addrTenTimeOut = 0x1000;
 107         xlbarb->dataTenTimeOut = 0x1000;
 108         xlbarb->busActTimeOut = 0x2000;
 109
 110         xlbarb->config = 0x00002000;
 111
 112         /* Master Priority Enable */
 113         xlbarb->mastPriority = 0;
 114         xlbarb->mastPriEn = 0xff;
 115 }
 116
 117 /*
 118  * initialize higher level parts of CPU like time base and timers
 119  */
 120 int cpu_init_r (void)
 121 {
 122         /* this may belongs to disable interrupt section */
 123         /* mask all interrupts */
 124         *(vu_long *) 0xf0000700 = 0xfffffc00;
 125         *(vu_long *) 0xf0000714 |= 0x0001ffff;
 126         *(vu_long *) 0xf0000710 &= ~0x00000f00;
 127
 128         /* route critical ints to normal ints */
 129         *(vu_long *) 0xf0000710 |= 0x00000001;
 130
 131 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_MPC8220_FEC)
 132         /* load FEC microcode */
 133         loadtask (0, 2);
 134 #endif
 135         return (0);
 136 }