cpu/mpc8260/cpu_init.c

   1 /*
   2  * (C) Copyright 2000-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc8260.h>
  26 #include <asm/cpm_8260.h>
  27 #include <ioports.h>
  28
  29 static void config_8260_ioports (volatile immap_t * immr)
  30 {
  31         int portnum;
  32
  33         for (portnum = 0; portnum < 4; portnum++) {
  34                 uint pmsk = 0,
  35                      ppar = 0,
  36                      psor = 0,
  37                      pdir = 0,
  38                      podr = 0,
  39                      pdat = 0;
  40                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  41                 iop_conf_t *eiopc = iopc + 32;
  42                 uint msk = 1;
  43
  44                 /*
  45                  * NOTE:
  46                  * index 0 refers to pin 31,
  47                  * index 31 refers to pin 0
  48                  */
  49                 while (iopc < eiopc) {
  50                         if (iopc->conf) {
  51                                 pmsk |= msk;
  52                                 if (iopc->ppar)
  53                                         ppar |= msk;
  54                                 if (iopc->psor)
  55                                         psor |= msk;
  56                                 if (iopc->pdir)
  57                                         pdir |= msk;
  58                                 if (iopc->podr)
  59                                         podr |= msk;
  60                                 if (iopc->pdat)
  61                                         pdat |= msk;
  62                         }
  63
  64                         msk <<= 1;
  65                         iopc++;
  66                 }
  67
  68                 if (pmsk != 0) {
  69                         volatile ioport_t *iop = ioport_addr (immr, portnum);
  70                         uint tpmsk = ~pmsk;
  71
  72                         /*
  73                          * the (somewhat confused) paragraph at the
  74                          * bottom of page 35-5 warns that there might
  75                          * be "unknown behaviour" when programming
  76                          * PSORx and PDIRx, if PPARx = 1, so I
  77                          * decided this meant I had to disable the
  78                          * dedicated function first, and enable it
  79                          * last.
  80                          */
  81                         iop->ppar &= tpmsk;
  82                         iop->psor = (iop->psor & tpmsk) | psor;
  83                         iop->podr = (iop->podr & tpmsk) | podr;
  84                         iop->pdat = (iop->pdat & tpmsk) | pdat;
  85                         iop->pdir = (iop->pdir & tpmsk) | pdir;
  86                         iop->ppar |= ppar;
  87                 }
  88         }
  89 }
  90
  91 /*
  92  * Breath some life into the CPU...
  93  *
  94  * Set up the memory map,
  95  * initialize a bunch of registers,
  96  * initialize the UPM's
  97  */
  98 void cpu_init_f (volatile immap_t * immr)
  99 {
 100         DECLARE_GLOBAL_DATA_PTR;
 101 #if !defined(CONFIG_COGENT)             /* done in start.S for the cogent */
 102         uint sccr;
 103 #endif
 104         volatile memctl8260_t *memctl = &immr->im_memctl;
 105         extern void m8260_cpm_reset (void);
 106
 107         /* Pointer is writable since we allocated a register for it */
 108         gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 109
 110         /* Clear initial global data */
 111         memset ((void *) gd, 0, sizeof (gd_t));
 112
 113         /* RSR - Reset Status Register - clear all status (5-4) */
 114         gd->reset_status = immr->im_clkrst.car_rsr;
 115         immr->im_clkrst.car_rsr = RSR_ALLBITS;
 116
 117         /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
 118         immr->im_clkrst.car_rmr = CFG_RMR;
 119
 120         /* BCR - Bus Configuration Register (4-25) */
 121         immr->im_siu_conf.sc_bcr = CFG_BCR;
 122
 123         /* SIUMCR - contains debug pin configuration (4-31) */
 124         immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
 125
 126         config_8260_ioports (immr);
 127
 128         /* initialize time counter status and control register (4-40) */
 129         immr->im_sit.sit_tmcntsc = CFG_TMCNTSC;
 130
 131         /* initialize the PIT (4-42) */
 132         immr->im_sit.sit_piscr = CFG_PISCR;
 133
 134 #if !defined(CONFIG_COGENT)             /* done in start.S for the cogent */
 135         /* System clock control register (9-8) */
 136         sccr = immr->im_clkrst.car_sccr &
 137                 (SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
 138         immr->im_clkrst.car_sccr = sccr |
 139                 (CFG_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
 140 #endif /* !CONFIG_COGENT */
 141
 142         /*
 143          * Memory Controller:
 144          */
 145
 146         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 147          * addresses - these have to be modified later when FLASH size
 148          * has been determined
 149          */
 150
 151 #if defined(CFG_OR0_REMAP)
 152         memctl->memc_or0 = CFG_OR0_REMAP;
 153 #endif
 154 #if defined(CFG_OR1_REMAP)
 155         memctl->memc_or1 = CFG_OR1_REMAP;
 156 #endif
 157
 158         /* now restrict to preliminary range */
 159         memctl->memc_br0 = CFG_BR0_PRELIM;
 160         memctl->memc_or0 = CFG_OR0_PRELIM;
 161
 162 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
 163         memctl->memc_or1 = CFG_OR1_PRELIM;
 164         memctl->memc_br1 = CFG_BR1_PRELIM;
 165 #endif
 166
 167 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
 168         memctl->memc_or2 = CFG_OR2_PRELIM;
 169         memctl->memc_br2 = CFG_BR2_PRELIM;
 170 #endif
 171
 172 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
 173         memctl->memc_or3 = CFG_OR3_PRELIM;
 174         memctl->memc_br3 = CFG_BR3_PRELIM;
 175 #endif
 176
 177 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
 178         memctl->memc_or4 = CFG_OR4_PRELIM;
 179         memctl->memc_br4 = CFG_BR4_PRELIM;
 180 #endif
 181
 182 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
 183         memctl->memc_or5 = CFG_OR5_PRELIM;
 184         memctl->memc_br5 = CFG_BR5_PRELIM;
 185 #endif
 186
 187 #if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
 188         memctl->memc_or6 = CFG_OR6_PRELIM;
 189         memctl->memc_br6 = CFG_BR6_PRELIM;
 190 #endif
 191
 192 #if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
 193         memctl->memc_or7 = CFG_OR7_PRELIM;
 194         memctl->memc_br7 = CFG_BR7_PRELIM;
 195 #endif
 196
 197 #if defined(CFG_BR8_PRELIM) && defined(CFG_OR8_PRELIM)
 198         memctl->memc_or8 = CFG_OR8_PRELIM;
 199         memctl->memc_br8 = CFG_BR8_PRELIM;
 200 #endif
 201
 202 #if defined(CFG_BR9_PRELIM) && defined(CFG_OR9_PRELIM)
 203         memctl->memc_or9 = CFG_OR9_PRELIM;
 204         memctl->memc_br9 = CFG_BR9_PRELIM;
 205 #endif
 206
 207 #if defined(CFG_BR10_PRELIM) && defined(CFG_OR10_PRELIM)
 208         memctl->memc_or10 = CFG_OR10_PRELIM;
 209         memctl->memc_br10 = CFG_BR10_PRELIM;
 210 #endif
 211
 212 #if defined(CFG_BR11_PRELIM) && defined(CFG_OR11_PRELIM)
 213         memctl->memc_or11 = CFG_OR11_PRELIM;
 214         memctl->memc_br11 = CFG_BR11_PRELIM;
 215 #endif
 216
 217         m8260_cpm_reset ();
 218 }
 219
 220 /*
 221  * initialize higher level parts of CPU like time base and timers
 222  */
 223 int cpu_init_r (void)
 224 {
 225         DECLARE_GLOBAL_DATA_PTR;
 226
 227         volatile immap_t *immr = (immap_t *) gd->bd->bi_immr_base;
 228
 229         immr->im_cpm.cp_rccr = CFG_RCCR;
 230
 231         return (0);
 232 }
 233
 234 /*
 235  * print out the reason for the reset
 236  */
 237 int prt_8260_rsr (void)
 238 {
 239         DECLARE_GLOBAL_DATA_PTR;
 240
 241         static struct {
 242                 ulong mask;
 243                 char *desc;
 244         } bits[] = {
 245                 {
 246                 RSR_JTRS, "JTAG"}, {
 247                 RSR_CSRS, "Check Stop"}, {
 248                 RSR_SWRS, "Software Watchdog"}, {
 249                 RSR_BMRS, "Bus Monitor"}, {
 250                 RSR_ESRS, "External Soft"}, {
 251                 RSR_EHRS, "External Hard"}
 252         };
 253         static int n = sizeof bits / sizeof bits[0];
 254         ulong rsr = gd->reset_status;
 255         int i;
 256         char *sep;
 257
 258         puts (CPU_ID_STR " Reset Status:");
 259
 260         sep = " ";
 261         for (i = 0; i < n; i++)
 262                 if (rsr & bits[i].mask) {
 263                         printf ("%s%s", sep, bits[i].desc);
 264                         sep = ", ";
 265                 }
 266
 267         puts ("\n\n");
 268         return (0);
 269 }