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1 /*
2 * (C) Copyright 2000
3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
4 *
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27 #include <common.h>
28
29 #if defined(CONFIG_HARD_I2C)
30
31 #include <asm/cpm_8260.h>
32 #include <i2c.h>
33
34 /* define to enable debug messages */
35 #undef DEBUG_I2C
36
37 /* uSec to wait between polls of the i2c */
38 #define DELAY_US 100
39 /* uSec to wait for the CPM to start processing the buffer */
40 #define START_DELAY_US 1000
41
42 /*
43 * tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the
44 * timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP
45 */
46 #define TOUT_LOOP 5
47
48 /*-----------------------------------------------------------------------
49 * Set default values
50 */
51 #ifndef CFG_I2C_SPEED
52 #define CFG_I2C_SPEED 50000
53 #endif
54
55 #ifndef CFG_I2C_SLAVE
56 #define CFG_I2C_SLAVE 0xFE
57 #endif
58 /*-----------------------------------------------------------------------
59 */
60
61 typedef void (*i2c_ecb_t)(int, int); /* error callback function */
62
63 /* This structure keeps track of the bd and buffer space usage. */
64 typedef struct i2c_state {
65 int rx_idx; /* index to next free Rx BD */
66 int tx_idx; /* index to next free Tx BD */
67 void *rxbd; /* pointer to next free Rx BD */
68 void *txbd; /* pointer to next free Tx BD */
69 int tx_space; /* number of Tx bytes left */
70 unsigned char *tx_buf; /* pointer to free Tx area */
71 i2c_ecb_t err_cb; /* error callback function */
72 } i2c_state_t;
73
74 /* flags for i2c_send() and i2c_receive() */
75 #define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
76 #define I2CF_START_COND 0x02 /* tx: generate start condition */
77 #define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
78
79 /* return codes */
80 #define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */
81 #define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */
82 #define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */
83 #define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */
84
85 /* error callback flags */
86 #define I2CECB_RX_ERR 0x10 /* this is a receive error */
87 #define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */
88 #define I2CECB_RX_MASK 0x0f /* mask for error bits */
89 #define I2CECB_TX_ERR 0x20 /* this is a transmit error */
90 #define I2CECB_TX_CL 0x01 /* transmit collision error */
91 #define I2CECB_TX_UN 0x02 /* transmit underflow error */
92 #define I2CECB_TX_NAK 0x04 /* transmit no ack error */
93 #define I2CECB_TX_MASK 0x0f /* mask for error bits */
94 #define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
95
96 #define ERROR_I2C_NONE 0
97 #define ERROR_I2C_LENGTH 1
98
99 #define I2C_WRITE_BIT 0x00
100 #define I2C_READ_BIT 0x01
101
102 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
103
104
105 #define NUM_RX_BDS 4
106 #define NUM_TX_BDS 4
107 #define MAX_TX_SPACE 256
108
109 typedef struct I2C_BD
110 {
111 unsigned short status;
112 unsigned short length;
113 unsigned char *addr;
114 } I2C_BD;
115 #define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
116
117 #define BD_I2C_TX_CL 0x0001 /* collision error */
118 #define BD_I2C_TX_UN 0x0002 /* underflow error */
119 #define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
120 #define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
121
122 #define BD_I2C_RX_ERR BD_SC_OV
123
124 #ifdef DEBUG_I2C
125 #define PRINTD(x) printf x
126 #else
127 #define PRINTD(x)
128 #endif
129
130 /*
131 * Returns the best value of I2BRG to meet desired clock speed of I2C with
132 * input parameters (clock speed, filter, and predivider value).
133 * It returns computer speed value and the difference between it and desired
134 * speed.
135 */
136 static inline int
137 i2c_roundrate(int hz, int speed, int filter, int modval,
138 int *brgval, int *totspeed)
139 {
140 int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
141
142 PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
143 hz, speed, filter, modval));
144
145 div = moddiv * speed;
146 brgdiv = (hz + div - 1) / div;
147
148 PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
149
150 *brgval = (brgdiv / 2) - 3 - (2*filter);
151
152 if ((*brgval < 0) || (*brgval > 255)) {
153 PRINTD(("\t\trejected brgval=%d\n", *brgval));
154 return -1;
155 }
156
157 brgdiv = 2 * (*brgval + 3 + (2 * filter));
158 div = moddiv * brgdiv ;
159 *totspeed = (hz + div - 1) / div;
160
161 PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
162
163 return 0;
164 }
165
166 /*
167 * Sets the I2C clock predivider and divider to meet required clock speed.
168 */
169 static int i2c_setrate(int hz, int speed)
170 {
171 immap_t *immap = (immap_t *)CFG_IMMR ;
172 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
173 int brgval,
174 modval, /* 0-3 */
175 bestspeed_diff = speed,
176 bestspeed_brgval=0,
177 bestspeed_modval=0,
178 bestspeed_filter=0,
179 totspeed,
180 filter = 0; /* Use this fixed value */
181
182 for (modval = 0; modval < 4; modval++)
183 {
184 if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0)
185 {
186 int diff = speed - totspeed ;
187
188 if ((diff >= 0) && (diff < bestspeed_diff))
189 {
190 bestspeed_diff = diff ;
191 bestspeed_modval = modval;
192 bestspeed_brgval = brgval;
193 bestspeed_filter = filter;
194 }
195 }
196 }
197
198 PRINTD(("[I2C] Best is:\n"));
199 PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
200 hz, speed,
201 bestspeed_filter, bestspeed_modval, bestspeed_brgval,
202 bestspeed_diff));
203
204 i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
205 i2c->i2c_i2brg = bestspeed_brgval & 0xff;
206
207 PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg));
208
209 return 1 ;
210 }
211
212 void i2c_init(int speed, int slaveadd)
213 {
214 DECLARE_GLOBAL_DATA_PTR;
215
216 volatile immap_t *immap = (immap_t *)CFG_IMMR ;
217 volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
218 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
219 volatile iic_t *iip;
220 ulong rbase, tbase;
221 volatile I2C_BD *rxbd, *txbd;
222 uint dpaddr;
223
224 #ifdef CFG_I2C_INIT_BOARD
225 /* call board specific i2c bus reset routine before accessing the */
226 /* environment, which might be in a chip on that bus. For details */
227 /* about this problem see doc/I2C_Edge_Conditions. */
228 i2c_init_board();
229 #endif
230
231 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
232 if (dpaddr == 0) {
233 /* need to allocate dual port ram */
234 dpaddr = m8260_cpm_dpalloc(64 +
235 (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
236 MAX_TX_SPACE, 64);
237 *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])) = dpaddr;
238 }
239
240 /*
241 * initialise data in dual port ram:
242 *
243 * dpaddr -> parameter ram (64 bytes)
244 * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
245 * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
246 * tx buffer (MAX_TX_SPACE bytes)
247 */
248
249 iip = (iic_t *)&immap->im_dprambase[dpaddr];
250 memset((void*)iip, 0, sizeof(iic_t));
251
252 rbase = dpaddr + 64;
253 tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
254
255 /* Disable interrupts */
256 i2c->i2c_i2mod = 0x00;
257 i2c->i2c_i2cmr = 0x00;
258 i2c->i2c_i2cer = 0xff;
259 i2c->i2c_i2add = slaveadd;
260
261 /*
262 * Set the I2C BRG Clock division factor from desired i2c rate
263 * and current CPU rate (we assume sccr dfbgr field is 0;
264 * divide BRGCLK by 1)
265 */
266 PRINTD(("[I2C] Setting rate...\n"));
267 i2c_setrate (gd->brg_clk, CFG_I2C_SPEED) ;
268
269 /* Set I2C controller in master mode */
270 i2c->i2c_i2com = 0x01;
271
272 /* Initialize Tx/Rx parameters */
273 iip->iic_rbase = rbase;
274 iip->iic_tbase = tbase;
275 rxbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_rbase]);
276 txbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_tbase]);
277
278 PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
279 PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
280 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
281 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
282
283 /* Set big endian byte order */
284 iip->iic_tfcr = 0x10;
285 iip->iic_rfcr = 0x10;
286
287 /* Set maximum receive size. */
288 iip->iic_mrblr = I2C_RXTX_LEN;
289
290 cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
291 CPM_CR_I2C_SBLOCK,
292 0x00,
293 CPM_CR_INIT_TRX) | CPM_CR_FLG;
294 do {
295 __asm__ __volatile__ ("eieio");
296 } while (cp->cp_cpcr & CPM_CR_FLG);
297
298 /* Clear events and interrupts */
299 i2c->i2c_i2cer = 0xff;
300 i2c->i2c_i2cmr = 0x00;
301 }
302
303 static
304 void i2c_newio(i2c_state_t *state)
305 {
306 volatile immap_t *immap = (immap_t *)CFG_IMMR ;
307 volatile iic_t *iip;
308 uint dpaddr;
309
310 PRINTD(("[I2C] i2c_newio\n"));
311
312 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
313 iip = (iic_t *)&immap->im_dprambase[dpaddr];
314 state->rx_idx = 0;
315 state->tx_idx = 0;
316 state->rxbd = (void*)&immap->im_dprambase[iip->iic_rbase];
317 state->txbd = (void*)&immap->im_dprambase[iip->iic_tbase];
318 state->tx_space = MAX_TX_SPACE;
319 state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
320 state->err_cb = NULL;
321
322 PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
323 PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
324 PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
325
326 /* clear the buffer memory */
327 memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
328 }
329
330 static
331 int i2c_send(i2c_state_t *state,
332 unsigned char address,
333 unsigned char secondary_address,
334 unsigned int flags,
335 unsigned short size,
336 unsigned char *dataout)
337 {
338 volatile I2C_BD *txbd;
339 int i,j;
340
341 PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
342 address, secondary_address, flags, size));
343
344 /* trying to send message larger than BD */
345 if (size > I2C_RXTX_LEN)
346 return I2CERR_MSG_TOO_LONG;
347
348 /* no more free bds */
349 if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
350 return I2CERR_NO_BUFFERS;
351
352 txbd = (I2C_BD *)state->txbd;
353 txbd->addr = state->tx_buf;
354
355 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
356
357 if (flags & I2CF_START_COND)
358 {
359 PRINTD(("[I2C] Formatting addresses...\n"));
360 if (flags & I2CF_ENABLE_SECONDARY)
361 {
362 txbd->length = size + 2; /* Length of message plus dest addresses */
363 txbd->addr[0] = address << 1;
364 txbd->addr[1] = secondary_address;
365 i = 2;
366 }
367 else
368 {
369 txbd->length = size + 1; /* Length of message plus dest address */
370 txbd->addr[0] = address << 1; /* Write destination address to BD */
371 i = 1;
372 }
373 }
374 else
375 {
376 txbd->length = size; /* Length of message */
377 i = 0;
378 }
379
380 /* set up txbd */
381 txbd->status = BD_SC_READY;
382 if (flags & I2CF_START_COND)
383 txbd->status |= BD_I2C_TX_START;
384 if (flags & I2CF_STOP_COND)
385 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
386
387 /* Copy data to send into buffer */
388 PRINTD(("[I2C] copy data...\n"));
389 for(j = 0; j < size; i++, j++)
390 txbd->addr[i] = dataout[j];
391
392 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
393 txbd->length,
394 txbd->status,
395 txbd->addr[0],
396 txbd->addr[1]));
397
398 /* advance state */
399 state->tx_buf += txbd->length;
400 state->tx_space -= txbd->length;
401 state->tx_idx++;
402 state->txbd = (void*)(txbd + 1);
403
404 return 0;
405 }
406
407 static
408 int i2c_receive(i2c_state_t *state,
409 unsigned char address,
410 unsigned char secondary_address,
411 unsigned int flags,
412 unsigned short size_to_expect,
413 unsigned char *datain)
414 {
415 volatile I2C_BD *rxbd, *txbd;
416
417 PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
418
419 /* Expected to receive too much */
420 if (size_to_expect > I2C_RXTX_LEN)
421 return I2CERR_MSG_TOO_LONG;
422
423 /* no more free bds */
424 if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
425 || state->tx_space < 2)
426 return I2CERR_NO_BUFFERS;
427
428 rxbd = (I2C_BD *)state->rxbd;
429 txbd = (I2C_BD *)state->txbd;
430
431 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
432 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
433
434 txbd->addr = state->tx_buf;
435
436 /* set up TXBD for destination address */
437 if (flags & I2CF_ENABLE_SECONDARY)
438 {
439 txbd->length = 2;
440 txbd->addr[0] = address << 1; /* Write data */
441 txbd->addr[1] = secondary_address; /* Internal address */
442 txbd->status = BD_SC_READY;
443 }
444 else
445 {
446 txbd->length = 1 + size_to_expect;
447 txbd->addr[0] = (address << 1) | 0x01;
448 txbd->status = BD_SC_READY;
449 memset(&txbd->addr[1], 0, txbd->length);
450 }
451
452 /* set up rxbd for reception */
453 rxbd->status = BD_SC_EMPTY;
454 rxbd->length = size_to_expect;
455 rxbd->addr = datain;
456
457 txbd->status |= BD_I2C_TX_START;
458 if (flags & I2CF_STOP_COND)
459 {
460 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
461 rxbd->status |= BD_SC_WRAP;
462 }
463
464 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
465 txbd->length,
466 txbd->status,
467 txbd->addr[0],
468 txbd->addr[1]));
469 PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
470 rxbd->length,
471 rxbd->status,
472 rxbd->addr[0],
473 rxbd->addr[1]));
474
475 /* advance state */
476 state->tx_buf += txbd->length;
477 state->tx_space -= txbd->length;
478 state->tx_idx++;
479 state->txbd = (void*)(txbd + 1);
480 state->rx_idx++;
481 state->rxbd = (void*)(rxbd + 1);
482
483 return 0;
484 }
485
486
487 static
488 int i2c_doio(i2c_state_t *state)
489 {
490 volatile immap_t *immap = (immap_t *)CFG_IMMR ;
491 volatile iic_t *iip;
492 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
493 volatile I2C_BD *txbd, *rxbd;
494 int j;
495 int timeout;
496 uint dpaddr;
497
498 PRINTD(("[I2C] i2c_doio\n"));
499
500 timeout = TOUT_LOOP * 256; /* arbitrarily long */
501
502 if (state->tx_idx <= 0 && state->rx_idx <= 0) {
503 PRINTD(("[I2C] No I/O is queued\n"));
504 return I2CERR_QUEUE_EMPTY;
505 }
506
507 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
508 iip = (iic_t *)&immap->im_dprambase[dpaddr];
509 iip->iic_rbptr = iip->iic_rbase;
510 iip->iic_tbptr = iip->iic_tbase;
511
512 /* Enable I2C */
513 PRINTD(("[I2C] Enabling I2C...\n"));
514 i2c->i2c_i2mod |= 0x01;
515
516 /* Begin transmission */
517 i2c->i2c_i2com |= 0x80;
518
519 /* Loop until transmit & receive completed */
520
521 txbd = ((I2C_BD*)state->txbd) - 1;
522 j = 0;
523 if (state->tx_idx > 0) {
524 timeout = TOUT_LOOP * txbd->length;
525
526 PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
527 udelay(START_DELAY_US); /* give it time to start */
528 while((txbd->status & BD_SC_READY) && (j++ < timeout)) {
529 udelay(DELAY_US);
530 if (ctrlc())
531 return (-1);
532 __asm__ __volatile__ ("eieio");
533 }
534 }
535
536 rxbd = ((I2C_BD*)state->rxbd) - 1;
537 j = 0;
538 if ((state->rx_idx > 0) && (j < timeout)) {
539 timeout = TOUT_LOOP * rxbd->length;
540 PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
541 udelay(START_DELAY_US); /* give it time to start */
542 while((rxbd->status & BD_SC_EMPTY) && (j++ < timeout)) {
543 udelay(DELAY_US);
544 if (ctrlc())
545 return (-1);
546 __asm__ __volatile__ ("eieio");
547 }
548 }
549
550 /* Turn off I2C */
551 i2c->i2c_i2mod &= ~0x01;
552
553 if (state->err_cb != NULL) {
554 int n, i, b;
555
556 /*
557 * if we have an error callback function, look at the
558 * error bits in the bd status and pass them back
559 */
560
561 if ((n = state->tx_idx) > 0) {
562 for (i = 0; i < n; i++) {
563 txbd = ((I2C_BD*)state->txbd) - (n - i);
564 if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
565 (*state->err_cb)(I2CECB_TX_ERR|b, i);
566 }
567 }
568
569 if ((n = state->rx_idx) > 0) {
570 for (i = 0; i < n; i++) {
571 rxbd = ((I2C_BD*)state->rxbd) - (n - i);
572 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
573 (*state->err_cb)(I2CECB_RX_ERR|b, i);
574 }
575 }
576
577 if (j >= timeout)
578 (*state->err_cb)(I2CECB_TIMEOUT, 0);
579 }
580
581 /* sort out errors and return appropriate good/error status */
582 if(j >= timeout)
583 return(I2CERR_TIMEOUT);
584 if((txbd->status & BD_I2C_TX_ERR) != 0)
585 return(I2CECB_TX_ERR | (txbd->status & I2CECB_TX_MASK));
586 if((rxbd->status & BD_I2C_RX_ERR) != 0)
587 return(I2CECB_RX_ERR | (rxbd->status & I2CECB_RX_MASK));
588
589 return(0);
590 }
591
592 static int had_tx_nak;
593
594 static void
595 i2c_test_callback(int flags, int xnum)
596 {
597 if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
598 had_tx_nak = 1;
599 }
600
601 int i2c_probe(uchar chip)
602 {
603 i2c_state_t state;
604 int rc;
605 uchar buf[1];
606
607 i2c_newio(&state);
608
609 state.err_cb = i2c_test_callback;
610 had_tx_nak = 0;
611
612 rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);
613
614 if (rc != 0)
615 return (rc);
616
617 rc = i2c_doio(&state);
618
619 if ((rc != 0) && (rc != I2CERR_TIMEOUT))
620 return (rc);
621
622 return (had_tx_nak);
623 }
624
625
626 int
627 i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
628 {
629 i2c_state_t state;
630 uchar xaddr[4];
631 int rc;
632
633 xaddr[0] = (addr >> 24) & 0xFF;
634 xaddr[1] = (addr >> 16) & 0xFF;
635 xaddr[2] = (addr >> 8) & 0xFF;
636 xaddr[3] = addr & 0xFF;
637
638 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
639 /*
640 * EEPROM chips that implement "address overflow" are ones
641 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
642 * and the extra bits end up in the "chip address" bit slots.
643 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
644 * chips.
645 *
646 * Note that we consider the length of the address field to still
647 * be one byte because the extra address bits are hidden in the
648 * chip address.
649 */
650 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
651 #endif
652
653 i2c_newio(&state);
654
655 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
656 if (rc != 0) {
657 printf("i2c_read: i2c_send failed (%d)\n", rc);
658 return 1;
659 }
660
661 rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
662 if (rc != 0) {
663 printf("i2c_read: i2c_receive failed (%d)\n", rc);
664 return 1;
665 }
666
667 rc = i2c_doio(&state);
668 if (rc != 0) {
669 printf("i2c_read: i2c_doio failed (%d)\n", rc);
670 return 1;
671 }
672 return 0;
673 }
674
675 int
676 i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
677 {
678 i2c_state_t state;
679 uchar xaddr[4];
680 int rc;
681
682 xaddr[0] = (addr >> 24) & 0xFF;
683 xaddr[1] = (addr >> 16) & 0xFF;
684 xaddr[2] = (addr >> 8) & 0xFF;
685 xaddr[3] = addr & 0xFF;
686
687 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
688 /*
689 * EEPROM chips that implement "address overflow" are ones
690 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
691 * and the extra bits end up in the "chip address" bit slots.
692 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
693 * chips.
694 *
695 * Note that we consider the length of the address field to still
696 * be one byte because the extra address bits are hidden in the
697 * chip address.
698 */
699 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
700 #endif
701
702 i2c_newio(&state);
703
704 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
705 if (rc != 0) {
706 printf("i2c_write: first i2c_send failed (%d)\n", rc);
707 return 1;
708 }
709
710 rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
711 if (rc != 0) {
712 printf("i2c_write: second i2c_send failed (%d)\n", rc);
713 return 1;
714 }
715
716 rc = i2c_doio(&state);
717 if (rc != 0) {
718 printf("i2c_write: i2c_doio failed (%d)\n", rc);
719 return 1;
720 }
721 return 0;
722 }
723
724 uchar
725 i2c_reg_read(uchar chip, uchar reg)
726 {
727 char buf;
728
729 i2c_read(chip, reg, 1, &buf, 1);
730
731 return (buf);
732 }
733
734 void
735 i2c_reg_write(uchar chip, uchar reg, uchar val)
736 {
737 i2c_write(chip, reg, 1, &val, 1);
738 }
739
740 #endif /* CONFIG_HARD_I2C */
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