cpu/mpc8260/speed.c

   1 /*
   2  * (C) Copyright 2000-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc8260.h>
  26 #include <asm/processor.h>
  27
  28 /* ------------------------------------------------------------------------- */
  29
  30 /* Bus-to-Core Multiplier */
  31 #define _1x     2
  32 #define _1_5x   3
  33 #define _2x     4
  34 #define _2_5x   5
  35 #define _3x     6
  36 #define _3_5x   7
  37 #define _4x     8
  38 #define _4_5x   9
  39 #define _5x     10
  40 #define _5_5x   11
  41 #define _6x     12
  42 #define _6_5x   13
  43 #define _7x     14
  44 #define _7_5x   15
  45 #define _8x     16
  46 #define _byp    -1
  47 #define _off    -2
  48 #define _unk    -3
  49
  50 typedef struct {
  51         int b2c_mult;
  52         int vco_div;
  53         char *freq_60x;
  54         char *freq_core;
  55 } corecnf_t;
  56
  57 /*
  58  * this table based on "Errata to MPC8260 PowerQUICC II User's Manual",
  59  * Rev. 1, 8/2000, page 10.
  60  */
  61 corecnf_t corecnf_tab[] = {
  62         { _1_5x,  4, " 33-100", " 33-100" },    /* 0x00 */
  63         {   _1x,  4, " 50-150", " 50-150" },    /* 0x01 */
  64         {   _1x,  8, " 25-75 ", " 25-75 " },    /* 0x02 */
  65         {  _byp, -1, "  ?-?  ", "  ?-?  " },    /* 0x03 */
  66         {   _2x,  2, " 50-150", "100-300" },    /* 0x04 */
  67         {   _2x,  4, " 25-75 ", " 50-150" },    /* 0x05 */
  68         { _2_5x,  2, " 40-120", "100-240" },    /* 0x06 */
  69         { _4_5x,  2, " 22-65 ", "100-300" },    /* 0x07 */
  70         {   _3x,  2, " 33-100", "100-300" },    /* 0x08 */
  71         { _5_5x,  2, " 18-55 ", "100-300" },    /* 0x09 */
  72         {   _4x,  2, " 25-75 ", "100-300" },    /* 0x0A */
  73         {   _5x,  2, " 20-60 ", "100-300" },    /* 0x0B */
  74         { _1_5x,  8, " 16-50 ", " 16-50 " },    /* 0x0C */
  75         {   _6x,  2, " 16-50 ", "100-300" },    /* 0x0D */
  76         { _3_5x,  2, " 30-85 ", "100-300" },    /* 0x0E */
  77         {  _off, -1, "  ?-?  ", "  ?-?  " },    /* 0x0F */
  78         {   _3x,  4, " 16-50 ", " 50-150" },    /* 0x10 */
  79         { _2_5x,  4, " 20-60 ", " 50-120" },    /* 0x11 */
  80         { _6_5x,  2, " 15-46 ", "100-300" },    /* 0x12 */
  81         {  _byp, -1, "  ?-?  ", "  ?-?  " },    /* 0x13 */
  82         {   _7x,  2, " 14-43 ", "100-300" },    /* 0x14 */
  83         {   _2x,  4, " 25-75 ", " 50-150" },    /* 0x15 */
  84         { _7_5x,  2, " 13-40 ", "100-300" },    /* 0x16 */
  85         { _4_5x,  2, " 22-65 ", "100-300" },    /* 0x17 */
  86         {  _unk, -1, "  ?-?  ", "  ?-?  " },    /* 0x18 */
  87         { _5_5x,  2, " 18-55 ", "100-300" },    /* 0x19 */
  88         {   _4x,  2, " 25-75 ", "100-300" },    /* 0x1A */
  89         {   _5x,  2, " 20-60 ", "100-300" },    /* 0x1B */
  90         {   _8x,  2, " 12-38 ", "100-300" },    /* 0x1C */
  91         {   _6x,  2, " 16-50 ", "100-300" },    /* 0x1D */
  92         { _3_5x,  2, " 30-85 ", "100-300" },    /* 0x1E */
  93         {  _off, -1, "  ?-?  ", "  ?-?  " },    /* 0x1F */
  94 };
  95
  96 /* ------------------------------------------------------------------------- */
  97
  98 /*
  99  *
 100  */
 101
 102 int get_clocks (void)
 103 {
 104         DECLARE_GLOBAL_DATA_PTR;
 105
 106         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 107         ulong clkin;
 108         ulong sccr, dfbrg;
 109         ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
 110         corecnf_t *cp;
 111
 112 #if !defined(CONFIG_8260_CLKIN)
 113 #error clock measuring not implemented yet - define CONFIG_8260_CLKIN
 114 #else
 115         clkin = CONFIG_8260_CLKIN;
 116 #endif
 117
 118         sccr = immap->im_clkrst.car_sccr;
 119         dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
 120
 121         scmr = immap->im_clkrst.car_scmr;
 122         corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
 123         cp = &corecnf_tab[corecnf];
 124
 125         busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
 126         cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
 127
 128         /* HiP7, HiP7 Rev01, HiP7 RevA */
 129         if ((get_pvr () == PVR_8260_HIP7) ||
 130             (get_pvr () == PVR_8260_HIP7R1) ||
 131             (get_pvr () == PVR_8260_HIP7RA)) {
 132                 pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT;
 133                 gd->vco_out = clkin * (pllmf + 1);
 134         } else {                        /* HiP3, HiP4 */
 135                 pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
 136                 plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
 137                 gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
 138         }
 139 #if 0
 140         if (gd->vco_out / (busdf + 1) != clkin) {
 141                 /* aaarrrggghhh!!! */
 142                 return (1);
 143         }
 144 #endif
 145
 146         gd->cpm_clk = gd->vco_out / 2;
 147         gd->bus_clk = clkin;
 148         gd->scc_clk = gd->vco_out / 4;
 149         gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
 150
 151         if (cp->b2c_mult > 0) {
 152                 gd->cpu_clk = (clkin * cp->b2c_mult) / 2;
 153         } else {
 154                 gd->cpu_clk = clkin;
 155         }
 156
 157         return (0);
 158 }
 159
 160 int prt_8260_clks (void)
 161 {
 162         DECLARE_GLOBAL_DATA_PTR;
 163
 164         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 165         ulong sccr, dfbrg;
 166         ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf, pcidf;
 167         corecnf_t *cp;
 168
 169         sccr = immap->im_clkrst.car_sccr;
 170         dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
 171
 172         scmr = immap->im_clkrst.car_scmr;
 173         corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
 174         busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
 175         cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
 176         plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
 177         pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
 178         pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;
 179
 180         cp = &corecnf_tab[corecnf];
 181
 182         puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
 183
 184         switch (cp->b2c_mult) {
 185         case _byp:
 186                 puts ("BYPASS");
 187                 break;
 188
 189         case _off:
 190                 puts ("OFF");
 191                 break;
 192
 193         case _unk:
 194                 puts ("UNKNOWN");
 195                 break;
 196
 197         default:
 198                 printf ("%d%sx",
 199                         cp->b2c_mult / 2,
 200                         (cp->b2c_mult % 2) ? ".5" : "");
 201                 break;
 202         }
 203
 204         printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
 205                         cp->vco_div, cp->freq_60x, cp->freq_core);
 206
 207         printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
 208                 "plldf %ld, pllmf %ld, pcidf %ld\n",
 209                         dfbrg, corecnf, busdf, cpmdf,
 210                         plldf, pllmf, pcidf);
 211
 212         printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
 213                         gd->vco_out, gd->scc_clk, gd->brg_clk);
 214
 215         printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
 216                         gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
 217
 218         if (sccr & SCCR_PCI_MODE) {
 219                 uint pci_div;
 220                 uint pcidf = (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT;
 221
 222                 if (sccr & SCCR_PCI_MODCK) {
 223                         pci_div = 2;
 224                         if (pcidf == 9) {
 225                                 pci_div *= 5;
 226                         } else if (pcidf == 0xB) {
 227                                 pci_div *= 6;
 228                         } else {
 229                                 pci_div *= (pcidf + 1);
 230                         }
 231                 } else {
 232                         pci_div = pcidf + 1;
 233                 }
 234
 235                 printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div);
 236         }
 237         putc ('\n');
 238
 239         return (0);
 240 }