cpu/mpc83xx/speed.c

   1 /*
   2  * (C) Copyright 2000-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Copyright 2004 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  *
  25  * Change log:
  26  *
  27  * 20050101: Eran Liberty (liberty@freescale.com)
  28  *           Initial file creating (porting from 85XX & 8260)
  29  */
  30
  31 #include <common.h>
  32 #include <mpc83xx.h>
  33 #include <asm/processor.h>
  34
  35 /* ----------------------------------------------------------------- */
  36
  37 typedef enum {
  38         _unk,
  39         _off,
  40         _byp,
  41         _x8,
  42         _x4,
  43         _x2,
  44         _x1,
  45         _1x,
  46         _1_5x,
  47         _2x,
  48         _2_5x,
  49         _3x
  50 } mult_t;
  51
  52 typedef struct {
  53         mult_t core_csb_ratio;
  54         mult_t  vco_divider;
  55 } corecnf_t;
  56
  57 corecnf_t corecnf_tab[] = {
  58         { _byp, _byp},  /* 0x00 */
  59         { _byp, _byp},  /* 0x01 */
  60         { _byp, _byp},  /* 0x02 */
  61         { _byp, _byp},  /* 0x03 */
  62         { _byp, _byp},  /* 0x04 */
  63         { _byp, _byp},  /* 0x05 */
  64         { _byp, _byp},  /* 0x06 */
  65         { _byp, _byp},  /* 0x07 */
  66         {  _1x,  _x2},  /* 0x08 */
  67         {  _1x,  _x4},  /* 0x09 */
  68         {  _1x,  _x8},  /* 0x0A */
  69         {  _1x,  _x8},  /* 0x0B */
  70         {_1_5x,  _x2},  /* 0x0C */
  71         {_1_5x,  _x4},  /* 0x0D */
  72         {_1_5x,  _x8},  /* 0x0E */
  73         {_1_5x,  _x8},  /* 0x0F */
  74         {  _2x,  _x2},  /* 0x10 */
  75         {  _2x,  _x4},  /* 0x11 */
  76         {  _2x,  _x8},  /* 0x12 */
  77         {  _2x,  _x8},  /* 0x13 */
  78         {_2_5x,  _x2},  /* 0x14 */
  79         {_2_5x,  _x4},  /* 0x15 */
  80         {_2_5x,  _x8},  /* 0x16 */
  81         {_2_5x,  _x8},  /* 0x17 */
  82         {  _3x,  _x2},  /* 0x18 */
  83         {  _3x,  _x4},  /* 0x19 */
  84         {  _3x,  _x8},  /* 0x1A */
  85         {  _3x,  _x8},  /* 0x1B */
  86 };
  87
  88 /* ----------------------------------------------------------------- */
  89
  90 /*
  91  *
  92  */
  93 int get_clocks (void)
  94 {
  95         DECLARE_GLOBAL_DATA_PTR;
  96         volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
  97         u32 pci_sync_in;
  98         u8  spmf;
  99         u8  clkin_div;
 100         u32 sccr;
 101         u32 corecnf_tab_index;
 102         u8  corepll;
 103         u32 lcrr;
 104
 105         u32 csb_clk;
 106         u32 tsec1_clk;
 107         u32 tsec2_clk;
 108         u32 core_clk;
 109         u32 usbmph_clk;
 110         u32 usbdr_clk;
 111         u32 i2c_clk;
 112         u32 enc_clk;
 113         u32 lbiu_clk;
 114         u32 lclk_clk;
 115         u32 ddr_clk;
 116
 117         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 118                 return -1;
 119
 120 #ifndef CFG_HRCW_HIGH
 121 # error "CFG_HRCW_HIGH must be defined in board config file"
 122 #endif /* CFG_HCWD_HIGH */
 123
 124 #if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
 125
 126 # ifndef CONFIG_83XX_CLKIN
 127 #  error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file"
 128 # endif /* CONFIG_83XX_CLKIN */
 129 # ifdef CONFIG_83XX_PCICLK
 130 #  warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred"
 131 # endif /* CONFIG_83XX_PCICLK */
 132
 133         /* PCI Host Mode */
 134         if (!(im->reset.rcwh & RCWH_PCIHOST)) {
 135                 /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH
 136                  * the im->reset.rcwhr PCI Host Mode is disabled
 137                  * FIXME: findout if there is a way to issue some warning */
 138                 return -2;
 139         }
 140         if (im->clk.spmr & SPMR_CKID) {
 141                 /* PCI Clock is half CONFIG_83XX_CLKIN */
 142                 pci_sync_in = CONFIG_83XX_CLKIN / 2;
 143         }
 144         else {
 145                 pci_sync_in = CONFIG_83XX_CLKIN;
 146         }
 147
 148 #else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */
 149
 150 # ifdef CONFIG_83XX_CLKIN
 151 #  warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred"
 152 # endif /* CONFIG_83XX_CLKIN */
 153 # ifndef CONFIG_83XX_PCICLK
 154 #  error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file"
 155 # endif /* CONFIG_83XX_PCICLK */
 156
 157         /* PCI Agent Mode */
 158         if (im->reset.rcwh & RCWH_PCIHOST) {
 159                 /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH
 160                  * the im->reset.rcwhr PCI Host Mode is enabled */
 161                 return -3;
 162         }
 163         pci_sync_in = CONFIG_83XX_PCICLK;
 164
 165 #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
 166
 167         /* we have up to date pci_sync_in */
 168         spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
 169         clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
 170
 171         if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) {
 172                 csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2;
 173         }
 174         else {
 175                 csb_clk = pci_sync_in * spmf * (1 + clkin_div);
 176         }
 177
 178         sccr = im->clk.sccr;
 179         switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 180         case 0:
 181                 tsec1_clk = 0;
 182                 break;
 183         case 1:
 184                 tsec1_clk = csb_clk;
 185                 break;
 186         case 2:
 187                 tsec1_clk = csb_clk / 2;
 188                 break;
 189         case 3:
 190                 tsec1_clk = csb_clk / 3;
 191                 break;
 192         default:
 193                 /* unkown SCCR_TSEC1CM value */
 194                 return -4;
 195         }
 196
 197         switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 198         case 0:
 199                 tsec2_clk = 0;
 200                 break;
 201         case 1:
 202                 tsec2_clk = csb_clk;
 203                 break;
 204         case 2:
 205                 tsec2_clk = csb_clk / 2;
 206                 break;
 207         case 3:
 208                 tsec2_clk = csb_clk / 3;
 209                 break;
 210         default:
 211                 /* unkown SCCR_TSEC2CM value */
 212                 return -5;
 213         }
 214         i2c_clk = tsec2_clk;
 215
 216         switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
 217         case 0:
 218                 enc_clk = 0;
 219                 break;
 220         case 1:
 221                 enc_clk = csb_clk;
 222                 break;
 223         case 2:
 224                 enc_clk = csb_clk / 2;
 225                 break;
 226         case 3:
 227                 enc_clk = csb_clk / 3;
 228                 break;
 229         default:
 230                 /* unkown SCCR_ENCCM value */
 231                 return -6;
 232         }
 233
 234         switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
 235         case 0:
 236                 usbmph_clk = 0;
 237                 break;
 238         case 1:
 239                 usbmph_clk = csb_clk;
 240                 break;
 241         case 2:
 242                 usbmph_clk = csb_clk / 2;
 243                 break;
 244         case 3:
 245                 usbmph_clk = csb_clk / 3;
 246                 break;
 247         default:
 248                 /* unkown SCCR_USBMPHCM value */
 249                 return -7;
 250         }
 251
 252         switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
 253         case 0:
 254                 usbdr_clk = 0;
 255                 break;
 256         case 1:
 257                 usbdr_clk = csb_clk;
 258                 break;
 259         case 2:
 260                 usbdr_clk = csb_clk / 2;
 261                 break;
 262         case 3:
 263                 usbdr_clk = csb_clk / 3;
 264                 break;
 265         default:
 266                 /* unkown SCCR_USBDRCM value */
 267                 return -8;
 268         }
 269
 270         if (usbmph_clk != 0
 271                 && usbdr_clk != 0
 272                 && usbmph_clk != usbdr_clk ) {
 273                 /* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */
 274                 return -9;
 275         }
 276
 277         lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
 278         lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
 279         switch (lcrr) {
 280         case 2:
 281         case 4:
 282         case 8:
 283                 lclk_clk = lbiu_clk / lcrr;
 284                 break;
 285         default:
 286                 /* unknown lcrr */
 287                 return -10;
 288         }
 289
 290         ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
 291
 292         corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
 293         corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
 294         if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) {
 295                 /* corecnf_tab_index is too high, possibly worng value */
 296                 return -11;
 297         }
 298         switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
 299         case _byp:
 300         case _x1:
 301         case _1x:
 302                 core_clk = csb_clk;
 303                 break;
 304         case _1_5x:
 305                 core_clk = (3 * csb_clk) / 2;
 306                 break;
 307         case _2x:
 308                 core_clk = 2 * csb_clk;
 309                 break;
 310         case _2_5x:
 311                 core_clk = ( 5 * csb_clk) / 2;
 312                 break;
 313         case _3x:
 314                 core_clk = 3 * csb_clk;
 315                 break;
 316         default:
 317                 /* unkown core to csb ratio */
 318                 return -12;
 319         }
 320
 321         gd->csb_clk    = csb_clk   ;
 322         gd->tsec1_clk  = tsec1_clk ;
 323         gd->tsec2_clk  = tsec2_clk ;
 324         gd->core_clk   = core_clk  ;
 325         gd->usbmph_clk = usbmph_clk;
 326         gd->usbdr_clk  = usbdr_clk ;
 327         gd->i2c_clk    = i2c_clk   ;
 328         gd->enc_clk    = enc_clk   ;
 329         gd->lbiu_clk   = lbiu_clk  ;
 330         gd->lclk_clk   = lclk_clk  ;
 331         gd->ddr_clk    = ddr_clk   ;
 332         gd->pci_clk    = pci_sync_in;
 333
 334         gd->cpu_clk = gd->core_clk;
 335         gd->bus_clk = gd->lbiu_clk;
 336         return 0;
 337 }
 338
 339 /********************************************
 340  * get_bus_freq
 341  * return system bus freq in Hz
 342  *********************************************/
 343 ulong get_bus_freq (ulong dummy)
 344 {
 345         DECLARE_GLOBAL_DATA_PTR;
 346         return gd->csb_clk;
 347 }
 348
 349 int print_clock_conf (void)
 350 {
 351         DECLARE_GLOBAL_DATA_PTR;
 352
 353         printf("Clock configuration:\n");
 354         printf("  Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
 355         printf("  Core:                %4d MHz\n",gd->core_clk/1000000);
 356         debug("  Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
 357         printf("  Local Bus:           %4d MHz\n",gd->lclk_clk/1000000);
 358         debug("  DDR:                 %4d MHz\n",gd->ddr_clk/1000000);
 359         debug("  I2C:                 %4d MHz\n",gd->i2c_clk/1000000);
 360         debug("  TSEC1:               %4d MHz\n",gd->tsec1_clk/1000000);
 361         debug("  TSEC2:               %4d MHz\n",gd->tsec2_clk/1000000);
 362         debug("  USB MPH:             %4d MHz\n",gd->usbmph_clk/1000000);
 363         debug("  USB DR:              %4d MHz\n",gd->usbdr_clk/1000000);
 364
 365         return 0;
 366 }