cpu/mpc83xx/speed.c

   1 /*
   2  * (C) Copyright 2000-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <mpc83xx.h>
  28 #include <command.h>
  29 #include <asm/processor.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 /* ----------------------------------------------------------------- */
  34
  35 typedef enum {
  36         _unk,
  37         _off,
  38         _byp,
  39         _x8,
  40         _x4,
  41         _x2,
  42         _x1,
  43         _1x,
  44         _1_5x,
  45         _2x,
  46         _2_5x,
  47         _3x
  48 } mult_t;
  49
  50 typedef struct {
  51         mult_t core_csb_ratio;
  52         mult_t vco_divider;
  53 } corecnf_t;
  54
  55 corecnf_t corecnf_tab[] = {
  56         {_byp, _byp},           /* 0x00 */
  57         {_byp, _byp},           /* 0x01 */
  58         {_byp, _byp},           /* 0x02 */
  59         {_byp, _byp},           /* 0x03 */
  60         {_byp, _byp},           /* 0x04 */
  61         {_byp, _byp},           /* 0x05 */
  62         {_byp, _byp},           /* 0x06 */
  63         {_byp, _byp},           /* 0x07 */
  64         {_1x, _x2},             /* 0x08 */
  65         {_1x, _x4},             /* 0x09 */
  66         {_1x, _x8},             /* 0x0A */
  67         {_1x, _x8},             /* 0x0B */
  68         {_1_5x, _x2},           /* 0x0C */
  69         {_1_5x, _x4},           /* 0x0D */
  70         {_1_5x, _x8},           /* 0x0E */
  71         {_1_5x, _x8},           /* 0x0F */
  72         {_2x, _x2},             /* 0x10 */
  73         {_2x, _x4},             /* 0x11 */
  74         {_2x, _x8},             /* 0x12 */
  75         {_2x, _x8},             /* 0x13 */
  76         {_2_5x, _x2},           /* 0x14 */
  77         {_2_5x, _x4},           /* 0x15 */
  78         {_2_5x, _x8},           /* 0x16 */
  79         {_2_5x, _x8},           /* 0x17 */
  80         {_3x, _x2},             /* 0x18 */
  81         {_3x, _x4},             /* 0x19 */
  82         {_3x, _x8},             /* 0x1A */
  83         {_3x, _x8},             /* 0x1B */
  84 };
  85
  86 /* ----------------------------------------------------------------- */
  87
  88 /*
  89  *
  90  */
  91 int get_clocks(void)
  92 {
  93         volatile immap_t *im = (immap_t *) CFG_IMMR;
  94         u32 pci_sync_in;
  95         u8 spmf;
  96         u8 clkin_div;
  97         u32 sccr;
  98         u32 corecnf_tab_index;
  99         u8 corepll;
 100         u32 lcrr;
 101
 102         u32 csb_clk;
 103 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 104         u32 tsec1_clk;
 105         u32 tsec2_clk;
 106         u32 usbdr_clk;
 107 #endif
 108 #ifdef CONFIG_MPC834X
 109         u32 usbmph_clk;
 110 #endif
 111         u32 core_clk;
 112         u32 i2c1_clk;
 113 #if !defined(CONFIG_MPC832X)
 114         u32 i2c2_clk;
 115 #endif
 116         u32 enc_clk;
 117         u32 lbiu_clk;
 118         u32 lclk_clk;
 119         u32 ddr_clk;
 120 #if defined(CONFIG_MPC8360)
 121         u32 ddr_sec_clk;
 122 #endif
 123 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 124         u32 qepmf;
 125         u32 qepdf;
 126         u32 qe_clk;
 127         u32 brg_clk;
 128 #endif
 129
 130         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 131                 return -1;
 132
 133         clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
 134
 135         if (im->reset.rcwh & HRCWH_PCI_HOST) {
 136 #if defined(CONFIG_83XX_CLKIN)
 137                 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
 138 #else
 139                 pci_sync_in = 0xDEADBEEF;
 140 #endif
 141         } else {
 142 #if defined(CONFIG_83XX_PCICLK)
 143                 pci_sync_in = CONFIG_83XX_PCICLK;
 144 #else
 145                 pci_sync_in = 0xDEADBEEF;
 146 #endif
 147         }
 148
 149         spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
 150         csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
 151
 152         sccr = im->clk.sccr;
 153
 154 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 155         switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 156         case 0:
 157                 tsec1_clk = 0;
 158                 break;
 159         case 1:
 160                 tsec1_clk = csb_clk;
 161                 break;
 162         case 2:
 163                 tsec1_clk = csb_clk / 2;
 164                 break;
 165         case 3:
 166                 tsec1_clk = csb_clk / 3;
 167                 break;
 168         default:
 169                 /* unkown SCCR_TSEC1CM value */
 170                 return -4;
 171         }
 172
 173         switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
 174         case 0:
 175                 usbdr_clk = 0;
 176                 break;
 177         case 1:
 178                 usbdr_clk = csb_clk;
 179                 break;
 180         case 2:
 181                 usbdr_clk = csb_clk / 2;
 182                 break;
 183         case 3:
 184                 usbdr_clk = csb_clk / 3;
 185                 break;
 186         default:
 187                 /* unkown SCCR_USBDRCM value */
 188                 return -8;
 189         }
 190 #endif
 191
 192 #if defined(CONFIG_MPC834X)
 193         switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 194         case 0:
 195                 tsec2_clk = 0;
 196                 break;
 197         case 1:
 198                 tsec2_clk = csb_clk;
 199                 break;
 200         case 2:
 201                 tsec2_clk = csb_clk / 2;
 202                 break;
 203         case 3:
 204                 tsec2_clk = csb_clk / 3;
 205                 break;
 206         default:
 207                 /* unkown SCCR_TSEC2CM value */
 208                 return -5;
 209         }
 210
 211         i2c1_clk = tsec2_clk;
 212
 213         switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
 214         case 0:
 215                 usbmph_clk = 0;
 216                 break;
 217         case 1:
 218                 usbmph_clk = csb_clk;
 219                 break;
 220         case 2:
 221                 usbmph_clk = csb_clk / 2;
 222                 break;
 223         case 3:
 224                 usbmph_clk = csb_clk / 3;
 225                 break;
 226         default:
 227                 /* unkown SCCR_USBMPHCM value */
 228                 return -7;
 229         }
 230
 231         if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
 232                 /* if USB MPH clock is not disabled and
 233                  * USB DR clock is not disabled then
 234                  * USB MPH & USB DR must have the same rate
 235                  */
 236                 return -9;
 237         }
 238 #elif defined(CONFIG_MPC831X)
 239         tsec2_clk = tsec1_clk;
 240
 241         if (!(sccr & SCCR_TSEC1ON))
 242                 tsec1_clk = 0;
 243         if (!(sccr & SCCR_TSEC2ON))
 244                 tsec2_clk = 0;
 245 #endif
 246
 247 #if !defined(CONFIG_MPC834X)
 248         i2c1_clk = csb_clk;
 249 #endif
 250 #if !defined(CONFIG_MPC832X)
 251         i2c2_clk = csb_clk;     /* i2c-2 clk is equal to csb clk */
 252 #endif
 253
 254         switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
 255         case 0:
 256                 enc_clk = 0;
 257                 break;
 258         case 1:
 259                 enc_clk = csb_clk;
 260                 break;
 261         case 2:
 262                 enc_clk = csb_clk / 2;
 263                 break;
 264         case 3:
 265                 enc_clk = csb_clk / 3;
 266                 break;
 267         default:
 268                 /* unkown SCCR_ENCCM value */
 269                 return -6;
 270         }
 271
 272         lbiu_clk = csb_clk *
 273                    (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
 274         lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
 275         switch (lcrr) {
 276         case 2:
 277         case 4:
 278         case 8:
 279                 lclk_clk = lbiu_clk / lcrr;
 280                 break;
 281         default:
 282                 /* unknown lcrr */
 283                 return -10;
 284         }
 285
 286         ddr_clk = csb_clk *
 287                   (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
 288         corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
 289 #if defined(CONFIG_MPC8360)
 290         ddr_sec_clk = csb_clk * (1 +
 291                        ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
 292 #endif
 293
 294         corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
 295         if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
 296                 /* corecnf_tab_index is too high, possibly worng value */
 297                 return -11;
 298         }
 299         switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
 300         case _byp:
 301         case _x1:
 302         case _1x:
 303                 core_clk = csb_clk;
 304                 break;
 305         case _1_5x:
 306                 core_clk = (3 * csb_clk) / 2;
 307                 break;
 308         case _2x:
 309                 core_clk = 2 * csb_clk;
 310                 break;
 311         case _2_5x:
 312                 core_clk = (5 * csb_clk) / 2;
 313                 break;
 314         case _3x:
 315                 core_clk = 3 * csb_clk;
 316                 break;
 317         default:
 318                 /* unkown core to csb ratio */
 319                 return -12;
 320         }
 321
 322 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 323         qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
 324         qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
 325         qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
 326         brg_clk = qe_clk / 2;
 327 #endif
 328
 329         gd->csb_clk = csb_clk;
 330 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 331         gd->tsec1_clk = tsec1_clk;
 332         gd->tsec2_clk = tsec2_clk;
 333         gd->usbdr_clk = usbdr_clk;
 334 #endif
 335 #if defined(CONFIG_MPC834X)
 336         gd->usbmph_clk = usbmph_clk;
 337 #endif
 338         gd->core_clk = core_clk;
 339         gd->i2c1_clk = i2c1_clk;
 340 #if !defined(CONFIG_MPC832X)
 341         gd->i2c2_clk = i2c2_clk;
 342 #endif
 343         gd->enc_clk = enc_clk;
 344         gd->lbiu_clk = lbiu_clk;
 345         gd->lclk_clk = lclk_clk;
 346         gd->ddr_clk = ddr_clk;
 347 #if defined(CONFIG_MPC8360)
 348         gd->ddr_sec_clk = ddr_sec_clk;
 349 #endif
 350 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 351         gd->qe_clk = qe_clk;
 352         gd->brg_clk = brg_clk;
 353 #endif
 354         gd->pci_clk = pci_sync_in;
 355         gd->cpu_clk = gd->core_clk;
 356         gd->bus_clk = gd->csb_clk;
 357         return 0;
 358
 359 }
 360
 361 /********************************************
 362  * get_bus_freq
 363  * return system bus freq in Hz
 364  *********************************************/
 365 ulong get_bus_freq(ulong dummy)
 366 {
 367         return gd->csb_clk;
 368 }
 369
 370 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 371 {
 372         printf("Clock configuration:\n");
 373         printf("  Core:                %4d MHz\n", gd->core_clk / 1000000);
 374         printf("  Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
 375 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
 376         printf("  QE:                  %4d MHz\n", gd->qe_clk / 1000000);
 377         printf("  BRG:                 %4d MHz\n", gd->brg_clk / 1000000);
 378 #endif
 379         printf("  Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
 380         printf("  Local Bus:           %4d MHz\n", gd->lclk_clk / 1000000);
 381         printf("  DDR:                 %4d MHz\n", gd->ddr_clk / 1000000);
 382 #if defined(CONFIG_MPC8360)
 383         printf("  DDR Secondary:       %4d MHz\n", gd->ddr_sec_clk / 1000000);
 384 #endif
 385         printf("  SEC:                 %4d MHz\n", gd->enc_clk / 1000000);
 386         printf("  I2C1:                %4d MHz\n", gd->i2c1_clk / 1000000);
 387 #if !defined(CONFIG_MPC832X)
 388         printf("  I2C2:                %4d MHz\n", gd->i2c2_clk / 1000000);
 389 #endif
 390 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
 391         printf("  TSEC1:               %4d MHz\n", gd->tsec1_clk / 1000000);
 392         printf("  TSEC2:               %4d MHz\n", gd->tsec2_clk / 1000000);
 393         printf("  USB DR:              %4d MHz\n", gd->usbdr_clk / 1000000);
 394 #endif
 395 #if defined(CONFIG_MPC834X)
 396         printf("  USB MPH:             %4d MHz\n", gd->usbmph_clk / 1000000);
 397 #endif
 398         return 0;
 399 }
 400
 401 U_BOOT_CMD(clocks, 1, 0, do_clocks,
 402         "clocks  - print clock configuration\n",
 403         "    clocks\n"
 404 );