cpu/mpc85xx/cpu.c

   1 /*
   2  * Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
   3  * (C) Copyright 2002, 2003 Motorola Inc.
   4  * Xianghua Xiao (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2000
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <common.h>
  30 #include <watchdog.h>
  31 #include <command.h>
  32 #include <fsl_esdhc.h>
  33 #include <asm/cache.h>
  34 #include <asm/io.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 int checkcpu (void)
  39 {
  40         sys_info_t sysinfo;
  41         uint pvr, svr;
  42         uint fam;
  43         uint ver;
  44         uint major, minor;
  45         struct cpu_type *cpu;
  46         char buf1[32], buf2[32];
  47 #ifdef CONFIG_DDR_CLK_FREQ
  48         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  49         u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  50                 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  51 #else
  52         u32 ddr_ratio = 0;
  53 #endif
  54         int i;
  55
  56         svr = get_svr();
  57         major = SVR_MAJ(svr);
  58 #ifdef CONFIG_MPC8536
  59         major &= 0x7; /* the msb of this nibble is a mfg code */
  60 #endif
  61         minor = SVR_MIN(svr);
  62
  63         if (cpu_numcores() > 1) {
  64 #ifndef CONFIG_MP
  65                 puts("Unicore software on multiprocessor system!!\n"
  66                      "To enable mutlticore build define CONFIG_MP\n");
  67 #endif
  68                 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
  69                 printf("CPU%d:  ", pic->whoami);
  70         } else {
  71                 puts("CPU:   ");
  72         }
  73
  74         cpu = gd->cpu;
  75
  76         puts(cpu->name);
  77         if (IS_E_PROCESSOR(svr))
  78                 puts("E");
  79
  80         printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  81
  82         pvr = get_pvr();
  83         fam = PVR_FAM(pvr);
  84         ver = PVR_VER(pvr);
  85         major = PVR_MAJ(pvr);
  86         minor = PVR_MIN(pvr);
  87
  88         printf("Core:  ");
  89         switch (fam) {
  90         case PVR_FAM(PVR_85xx):
  91             puts("E500");
  92             break;
  93         default:
  94             puts("Unknown");
  95             break;
  96         }
  97
  98         if (PVR_MEM(pvr) == 0x03)
  99                 puts("MC");
 100
 101         printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
 102
 103         get_sys_info(&sysinfo);
 104
 105         puts("Clock Configuration:");
 106         for (i = 0; i < cpu_numcores(); i++) {
 107                 if (!(i & 3))
 108                         printf ("\n       ");
 109                 printf("CPU%d:%-4s MHz, ",
 110                                 i,strmhz(buf1, sysinfo.freqProcessor[i]));
 111         }
 112         printf("\n       CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
 113
 114         switch (ddr_ratio) {
 115         case 0x0:
 116                 printf("       DDR:%-4s MHz (%s MT/s data rate), ",
 117                         strmhz(buf1, sysinfo.freqDDRBus/2),
 118                         strmhz(buf2, sysinfo.freqDDRBus));
 119                 break;
 120         case 0x7:
 121                 printf("       DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
 122                         strmhz(buf1, sysinfo.freqDDRBus/2),
 123                         strmhz(buf2, sysinfo.freqDDRBus));
 124                 break;
 125         default:
 126                 printf("       DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
 127                         strmhz(buf1, sysinfo.freqDDRBus/2),
 128                         strmhz(buf2, sysinfo.freqDDRBus));
 129                 break;
 130         }
 131
 132         if (sysinfo.freqLocalBus > LCRR_CLKDIV)
 133                 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
 134         else
 135                 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
 136                        sysinfo.freqLocalBus);
 137
 138 #ifdef CONFIG_CPM2
 139         printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
 140 #endif
 141
 142 #ifdef CONFIG_QE
 143         printf("       QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
 144 #endif
 145
 146         puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
 147
 148         return 0;
 149 }
 150
 151
 152 /* ------------------------------------------------------------------------- */
 153
 154 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 155 {
 156 /* Everything after the first generation of PQ3 parts has RSTCR */
 157 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
 158     defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
 159         unsigned long val, msr;
 160
 161         /*
 162          * Initiate hard reset in debug control register DBCR0
 163          * Make sure MSR[DE] = 1.  This only resets the core.
 164          */
 165         msr = mfmsr ();
 166         msr |= MSR_DE;
 167         mtmsr (msr);
 168
 169         val = mfspr(DBCR0);
 170         val |= 0x70000000;
 171         mtspr(DBCR0,val);
 172 #else
 173         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 174         out_be32(&gur->rstcr, 0x2);     /* HRESET_REQ */
 175         udelay(100);
 176 #endif
 177
 178         return 1;
 179 }
 180
 181
 182 /*
 183  * Get timebase clock frequency
 184  */
 185 unsigned long get_tbclk (void)
 186 {
 187         return (gd->bus_clk + 4UL)/8UL;
 188 }
 189
 190
 191 #if defined(CONFIG_WATCHDOG)
 192 void
 193 watchdog_reset(void)
 194 {
 195         int re_enable = disable_interrupts();
 196         reset_85xx_watchdog();
 197         if (re_enable) enable_interrupts();
 198 }
 199
 200 void
 201 reset_85xx_watchdog(void)
 202 {
 203         /*
 204          * Clear TSR(WIS) bit by writing 1
 205          */
 206         unsigned long val;
 207         val = mfspr(SPRN_TSR);
 208         val |= TSR_WIS;
 209         mtspr(SPRN_TSR, val);
 210 }
 211 #endif  /* CONFIG_WATCHDOG */
 212
 213 /*
 214  * Configures a UPM. The function requires the respective MxMR to be set
 215  * before calling this function. "size" is the number or entries, not a sizeof.
 216  */
 217 void upmconfig (uint upm, uint * table, uint size)
 218 {
 219         int i, mdr, mad, old_mad = 0;
 220         volatile u32 *mxmr;
 221         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 222         volatile u32 *brp,*orp;
 223         volatile u8* dummy = NULL;
 224         int upmmask;
 225
 226         switch (upm) {
 227         case UPMA:
 228                 mxmr = &lbc->mamr;
 229                 upmmask = BR_MS_UPMA;
 230                 break;
 231         case UPMB:
 232                 mxmr = &lbc->mbmr;
 233                 upmmask = BR_MS_UPMB;
 234                 break;
 235         case UPMC:
 236                 mxmr = &lbc->mcmr;
 237                 upmmask = BR_MS_UPMC;
 238                 break;
 239         default:
 240                 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
 241                 hang();
 242         }
 243
 244         /* Find the address for the dummy write transaction */
 245         for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
 246                  i++, brp += 2, orp += 2) {
 247
 248                 /* Look for a valid BR with selected UPM */
 249                 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
 250                         dummy = (volatile u8*)(in_be32(brp) & BR_BA);
 251                         break;
 252                 }
 253         }
 254
 255         if (i == 8) {
 256                 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
 257                 hang();
 258         }
 259
 260         for (i = 0; i < size; i++) {
 261                 /* 1 */
 262                 out_be32(mxmr,  (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
 263                 /* 2 */
 264                 out_be32(&lbc->mdr, table[i]);
 265                 /* 3 */
 266                 mdr = in_be32(&lbc->mdr);
 267                 /* 4 */
 268                 *(volatile u8 *)dummy = 0;
 269                 /* 5 */
 270                 do {
 271                         mad = in_be32(mxmr) & MxMR_MAD_MSK;
 272                 } while (mad <= old_mad && !(!mad && i == (size-1)));
 273                 old_mad = mad;
 274         }
 275         out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
 276 }
 277
 278 /*
 279  * Initializes on-chip MMC controllers.
 280  * to override, implement board_mmc_init()
 281  */
 282 int cpu_mmc_init(bd_t *bis)
 283 {
 284 #ifdef CONFIG_FSL_ESDHC
 285         return fsl_esdhc_mmc_init(bis);
 286 #else
 287         return 0;
 288 #endif
 289 }