cpu/mpc85xx/cpu_init.c

   1 /*
   2  * (C) Copyright 2003 Motorola Inc.
   3  * Modified by Xianghua Xiao, X.Xiao@motorola.com
   4  *
   5  * (C) Copyright 2000
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #include <common.h>
  28 #include <watchdog.h>
  29 #include <asm/processor.h>
  30 #include <ioports.h>
  31 #include <asm/io.h>
  32
  33 #ifdef CONFIG_CPM2
  34 static void config_8560_ioports (volatile immap_t * immr)
  35 {
  36         int portnum;
  37
  38         for (portnum = 0; portnum < 4; portnum++) {
  39                 uint pmsk = 0,
  40                      ppar = 0,
  41                      psor = 0,
  42                      pdir = 0,
  43                      podr = 0,
  44                      pdat = 0;
  45                 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
  46                 iop_conf_t *eiopc = iopc + 32;
  47                 uint msk = 1;
  48
  49                 /*
  50                  * NOTE:
  51                  * index 0 refers to pin 31,
  52                  * index 31 refers to pin 0
  53                  */
  54                 while (iopc < eiopc) {
  55                         if (iopc->conf) {
  56                                 pmsk |= msk;
  57                                 if (iopc->ppar)
  58                                         ppar |= msk;
  59                                 if (iopc->psor)
  60                                         psor |= msk;
  61                                 if (iopc->pdir)
  62                                         pdir |= msk;
  63                                 if (iopc->podr)
  64                                         podr |= msk;
  65                                 if (iopc->pdat)
  66                                         pdat |= msk;
  67                         }
  68
  69                         msk <<= 1;
  70                         iopc++;
  71                 }
  72
  73                 if (pmsk != 0) {
  74                         volatile ioport_t *iop = ioport_addr (immr, portnum);
  75                         uint tpmsk = ~pmsk;
  76
  77                         /*
  78                          * the (somewhat confused) paragraph at the
  79                          * bottom of page 35-5 warns that there might
  80                          * be "unknown behaviour" when programming
  81                          * PSORx and PDIRx, if PPARx = 1, so I
  82                          * decided this meant I had to disable the
  83                          * dedicated function first, and enable it
  84                          * last.
  85                          */
  86                         iop->ppar &= tpmsk;
  87                         iop->psor = (iop->psor & tpmsk) | psor;
  88                         iop->podr = (iop->podr & tpmsk) | podr;
  89                         iop->pdat = (iop->pdat & tpmsk) | pdat;
  90                         iop->pdir = (iop->pdir & tpmsk) | pdir;
  91                         iop->ppar |= ppar;
  92                 }
  93         }
  94 }
  95 #endif
  96
  97 /*
  98  * Breathe some life into the CPU...
  99  *
 100  * Set up the memory map
 101  * initialize a bunch of registers
 102  */
 103
 104 void cpu_init_f (void)
 105 {
 106         DECLARE_GLOBAL_DATA_PTR;
 107         volatile immap_t    *immap = (immap_t *)CFG_IMMR;
 108         volatile ccsr_lbc_t *memctl = &immap->im_lbc;
 109         extern void m8560_cpm_reset (void);
 110
 111         /* Pointer is writable since we allocated a register for it */
 112         gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 113
 114         /* Clear initial global data */
 115         memset ((void *) gd, 0, sizeof (gd_t));
 116
 117
 118 #ifdef CONFIG_CPM2
 119         config_8560_ioports(immap);
 120 #endif
 121
 122         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 123          * addresses - these have to be modified later when FLASH size
 124          * has been determined
 125          */
 126 #if defined(CFG_OR0_REMAP)
 127         memctl->or0 = CFG_OR0_REMAP;
 128 #endif
 129 #if defined(CFG_OR1_REMAP)
 130         memctl->or1 = CFG_OR1_REMAP;
 131 #endif
 132
 133         /* now restrict to preliminary range */
 134 #if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
 135         memctl->br0 = CFG_BR0_PRELIM;
 136         memctl->or0 = CFG_OR0_PRELIM;
 137 #endif
 138
 139 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
 140         memctl->or1 = CFG_OR1_PRELIM;
 141         memctl->br1 = CFG_BR1_PRELIM;
 142 #endif
 143
 144 #if !defined(CONFIG_MPC85xx)
 145 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
 146         memctl->or2 = CFG_OR2_PRELIM;
 147         memctl->br2 = CFG_BR2_PRELIM;
 148 #endif
 149 #endif
 150
 151 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
 152         memctl->or3 = CFG_OR3_PRELIM;
 153         memctl->br3 = CFG_BR3_PRELIM;
 154 #endif
 155
 156 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
 157         memctl->or4 = CFG_OR4_PRELIM;
 158         memctl->br4 = CFG_BR4_PRELIM;
 159 #endif
 160
 161 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
 162         memctl->or5 = CFG_OR5_PRELIM;
 163         memctl->br5 = CFG_BR5_PRELIM;
 164 #endif
 165
 166 #if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
 167         memctl->or6 = CFG_OR6_PRELIM;
 168         memctl->br6 = CFG_BR6_PRELIM;
 169 #endif
 170
 171 #if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
 172         memctl->or7 = CFG_OR7_PRELIM;
 173         memctl->br7 = CFG_BR7_PRELIM;
 174 #endif
 175
 176 #if defined(CONFIG_CPM2)
 177         m8560_cpm_reset();
 178 #endif
 179 }
 180
 181
 182 /*
 183  * Initialize L2 as cache.
 184  *
 185  * The newer 8548, etc, parts have twice as much cache, but
 186  * use the same bit-encoding as the older 8555, etc, parts.
 187  *
 188  * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()?
 189  */
 190
 191 int cpu_init_r(void)
 192 {
 193 #if defined(CONFIG_L2_CACHE)
 194         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 195         volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
 196         volatile uint cache_ctl;
 197         uint svr, ver;
 198
 199         svr = get_svr();
 200         ver = SVR_VER(svr);
 201
 202         asm("msync;isync");
 203         cache_ctl = l2cache->l2ctl;
 204
 205         switch (cache_ctl & 0x30000000) {
 206         case 0x20000000:
 207                 if (ver == SVR_8548 || ver == SVR_8548_E) {
 208                         printf ("L2 cache 512KB:");
 209                 } else {
 210                         printf ("L2 cache 256KB:");
 211                 }
 212                 break;
 213         case 0x00000000:
 214         case 0x10000000:
 215         case 0x30000000:
 216         default:
 217                 printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
 218                 return -1;
 219         }
 220
 221         asm("msync;isync");
 222         l2cache->l2ctl = 0x68000000; /* invalidate */
 223         cache_ctl = l2cache->l2ctl;
 224         asm("msync;isync");
 225
 226         l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */
 227         cache_ctl = l2cache->l2ctl;
 228         asm("msync;isync");
 229
 230         printf(" enabled\n");
 231 #else
 232         printf("L2 cache: disabled\n");
 233 #endif
 234
 235         return 0;
 236 }