2 * (C) Copyright 2003 Motorola Inc.
3 * Xianghua Xiao (X.Xiao@motorola.com)
4 * Modified based on 8260 for 8560.
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
31 * Minimal serial functions needed to use one of the SCC ports
32 * as serial console interface.
36 #include <asm/cpm_85xx.h>
38 DECLARE_GLOBAL_DATA_PTR
;
40 #if defined(CONFIG_CPM2)
41 #if defined(CONFIG_CONS_ON_SCC)
43 #if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */
46 #define PROFF_SCC PROFF_SCC1
47 #define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\
48 CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
49 #define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
50 #define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE
51 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK
53 #elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */
56 #define PROFF_SCC PROFF_SCC2
57 #define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\
58 CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
59 #define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
60 #define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE
61 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK
63 #elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */
66 #define PROFF_SCC PROFF_SCC3
67 #define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\
68 CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
69 #define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
70 #define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE
71 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK
73 #elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */
76 #define PROFF_SCC PROFF_SCC4
77 #define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\
78 CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
79 #define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
80 #define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE
81 #define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK
85 #error "console not correctly defined"
89 int serial_init (void)
91 volatile ccsr_cpm_t
*cpm
= (ccsr_cpm_t
*)CONFIG_SYS_MPC85xx_CPM_ADDR
;
92 volatile ccsr_cpm_scc_t
*sp
;
93 volatile scc_uart_t
*up
;
94 volatile cbd_t
*tbdf
, *rbdf
;
95 volatile ccsr_cpm_cp_t
*cp
= &(cpm
->im_cpm_cp
);
98 /* initialize pointers to SCC */
100 sp
= (ccsr_cpm_scc_t
*) &(cpm
->im_cpm_scc
[SCC_INDEX
]);
101 up
= (scc_uart_t
*)&(cpm
->im_dprambase
[PROFF_SCC
]);
103 /* Disable transmitter/receiver.
105 sp
->gsmrl
&= ~(SCC_GSMRL_ENR
| SCC_GSMRL_ENT
);
107 /* put the SCC channel into NMSI (non multiplexd serial interface)
108 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
110 cpm
->im_cpm_mux
.cmxscr
= \
111 (cpm
->im_cpm_mux
.cmxscr
&~CMXSCR_MASK
)|CMXSCR_VALUE
;
113 /* Set up the baud rate generator.
117 /* Allocate space for two buffer descriptors in the DP ram.
118 * damm: allocating space after the two buffers for rx/tx data
121 dpaddr
= m8560_cpm_dpalloc((2 * sizeof (cbd_t
)) + 2, 16);
123 /* Set the physical address of the host memory buffers in
124 * the buffer descriptors.
126 rbdf
= (cbd_t
*)&(cpm
->im_dprambase
[dpaddr
]);
127 rbdf
->cbd_bufaddr
= (uint
) (rbdf
+2);
128 rbdf
->cbd_sc
= BD_SC_EMPTY
| BD_SC_WRAP
;
130 tbdf
->cbd_bufaddr
= ((uint
) (rbdf
+2)) + 1;
131 tbdf
->cbd_sc
= BD_SC_WRAP
;
133 /* Set up the uart parameters in the parameter ram.
135 up
->scc_genscc
.scc_rbase
= dpaddr
;
136 up
->scc_genscc
.scc_tbase
= dpaddr
+sizeof(cbd_t
);
137 up
->scc_genscc
.scc_rfcr
= CPMFCR_EB
;
138 up
->scc_genscc
.scc_tfcr
= CPMFCR_EB
;
139 up
->scc_genscc
.scc_mrblr
= 1;
149 up
->scc_char1
= up
->scc_char2
= up
->scc_char3
= up
->scc_char4
= 0x8000;
150 up
->scc_char5
= up
->scc_char6
= up
->scc_char7
= up
->scc_char8
= 0x8000;
151 up
->scc_rccm
= 0xc0ff;
153 /* Mask all interrupts and remove anything pending.
158 /* Set 8 bit FIFO, 16 bit oversampling and UART mode.
160 sp
->gsmrh
= SCC_GSMRH_RFW
; /* 8 bit FIFO */
162 SCC_GSMRL_TDCR_16
| SCC_GSMRL_RDCR_16
| SCC_GSMRL_MODE_UART
;
164 /* Set CTS no flow control, 1 stop bit, 8 bit character length,
165 * normal async UART mode, no parity
167 sp
->psmr
= SCU_PSMR_CL
;
169 /* execute the "Init Rx and Tx params" CP command.
172 while (cp
->cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
175 cp
->cpcr
= mk_cr_cmd(CPM_CR_SCC_PAGE
, CPM_CR_SCC_SBLOCK
,
176 0, CPM_CR_INIT_TRX
) | CPM_CR_FLG
;
178 while (cp
->cpcr
& CPM_CR_FLG
) /* wait if cp is busy */
181 /* Enable transmitter/receiver.
183 sp
->gsmrl
|= SCC_GSMRL_ENR
| SCC_GSMRL_ENT
;
191 #if defined(CONFIG_CONS_USE_EXTC)
192 m8560_cpm_extcbrg(SCC_INDEX
, gd
->baudrate
,
193 CONFIG_CONS_EXTC_RATE
, CONFIG_CONS_EXTC_PINSEL
);
195 m8560_cpm_setbrg(SCC_INDEX
, gd
->baudrate
);
200 serial_putc(const char c
)
202 volatile scc_uart_t
*up
;
203 volatile cbd_t
*tbdf
;
204 volatile ccsr_cpm_t
*cpm
= (ccsr_cpm_t
*)CONFIG_SYS_MPC85xx_CPM_ADDR
;
209 up
= (scc_uart_t
*)&(cpm
->im_dprambase
[PROFF_SCC
]);
210 tbdf
= (cbd_t
*)&(cpm
->im_dprambase
[up
->scc_genscc
.scc_tbase
]);
212 /* Wait for last character to go.
214 while (tbdf
->cbd_sc
& BD_SC_READY
)
217 /* Load the character into the transmit buffer.
219 *(volatile char *)tbdf
->cbd_bufaddr
= c
;
220 tbdf
->cbd_datlen
= 1;
221 tbdf
->cbd_sc
|= BD_SC_READY
;
225 serial_puts (const char *s
)
235 volatile cbd_t
*rbdf
;
236 volatile scc_uart_t
*up
;
237 volatile ccsr_cpm_t
*cpm
= (ccsr_cpm_t
*)CONFIG_SYS_MPC85xx_CPM_ADDR
;
240 up
= (scc_uart_t
*)&(cpm
->im_dprambase
[PROFF_SCC
]);
241 rbdf
= (cbd_t
*)&(cpm
->im_dprambase
[up
->scc_genscc
.scc_rbase
]);
243 /* Wait for character to show up.
245 while (rbdf
->cbd_sc
& BD_SC_EMPTY
)
248 /* Grab the char and clear the buffer again.
250 c
= *(volatile unsigned char *)rbdf
->cbd_bufaddr
;
251 rbdf
->cbd_sc
|= BD_SC_EMPTY
;
259 volatile cbd_t
*rbdf
;
260 volatile scc_uart_t
*up
;
261 volatile ccsr_cpm_t
*cpm
= (ccsr_cpm_t
*)CONFIG_SYS_MPC85xx_CPM_ADDR
;
263 up
= (scc_uart_t
*)&(cpm
->im_dprambase
[PROFF_SCC
]);
264 rbdf
= (cbd_t
*)&(cpm
->im_dprambase
[up
->scc_genscc
.scc_rbase
]);
266 return ((rbdf
->cbd_sc
& BD_SC_EMPTY
) == 0);
269 #endif /* CONFIG_CONS_ON_SCC */
271 #endif /* CONFIG_CPM2 */