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Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
[people/ms/u-boot.git] / cpu / mpc85xx / spd_sdram.c
1 /*
2 * Copyright 2004, 2007 Freescale Semiconductor.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25 #include <common.h>
26 #include <asm/processor.h>
27 #include <i2c.h>
28 #include <spd.h>
29 #include <asm/mmu.h>
30 #include <asm/fsl_law.h>
31
32
33 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
34 extern void dma_init(void);
35 extern uint dma_check(void);
36 extern int dma_xfer(void *dest, uint count, void *src);
37 #endif
38
39 #ifdef CONFIG_SPD_EEPROM
40
41 #ifndef CFG_READ_SPD
42 #define CFG_READ_SPD i2c_read
43 #endif
44
45 static unsigned int setup_laws_and_tlbs(unsigned int memsize);
46
47
48 /*
49 * Convert picoseconds into clock cycles (rounding up if needed).
50 */
51
52 int
53 picos_to_clk(int picos)
54 {
55 int clks;
56
57 clks = picos / (2000000000 / (get_ddr_freq(0) / 1000));
58 if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) {
59 clks++;
60 }
61
62 return clks;
63 }
64
65
66 /*
67 * Calculate the Density of each Physical Rank.
68 * Returned size is in bytes.
69 *
70 * Study these table from Byte 31 of JEDEC SPD Spec.
71 *
72 * DDR I DDR II
73 * Bit Size Size
74 * --- ----- ------
75 * 7 high 512MB 512MB
76 * 6 256MB 256MB
77 * 5 128MB 128MB
78 * 4 64MB 16GB
79 * 3 32MB 8GB
80 * 2 16MB 4GB
81 * 1 2GB 2GB
82 * 0 low 1GB 1GB
83 *
84 * Reorder Table to be linear by stripping the bottom
85 * 2 or 5 bits off and shifting them up to the top.
86 */
87
88 unsigned int
89 compute_banksize(unsigned int mem_type, unsigned char row_dens)
90 {
91 unsigned int bsize;
92
93 if (mem_type == SPD_MEMTYPE_DDR) {
94 /* Bottom 2 bits up to the top. */
95 bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
96 debug("DDR: DDR I rank density = 0x%08x\n", bsize);
97 } else {
98 /* Bottom 5 bits up to the top. */
99 bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
100 debug("DDR: DDR II rank density = 0x%08x\n", bsize);
101 }
102 return bsize;
103 }
104
105
106 /*
107 * Convert a two-nibble BCD value into a cycle time.
108 * While the spec calls for nano-seconds, picos are returned.
109 *
110 * This implements the tables for bytes 9, 23 and 25 for both
111 * DDR I and II. No allowance for distinguishing the invalid
112 * fields absent for DDR I yet present in DDR II is made.
113 * (That is, cycle times of .25, .33, .66 and .75 ns are
114 * allowed for both DDR II and I.)
115 */
116
117 unsigned int
118 convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
119 {
120 /*
121 * Table look up the lower nibble, allow DDR I & II.
122 */
123 unsigned int tenths_ps[16] = {
124 0,
125 100,
126 200,
127 300,
128 400,
129 500,
130 600,
131 700,
132 800,
133 900,
134 250,
135 330,
136 660,
137 750,
138 0, /* undefined */
139 0 /* undefined */
140 };
141
142 unsigned int whole_ns = (spd_val & 0xF0) >> 4;
143 unsigned int tenth_ns = spd_val & 0x0F;
144 unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
145
146 return ps;
147 }
148
149
150 /*
151 * Determine Refresh Rate. Ignore self refresh bit on DDR I.
152 * Table from SPD Spec, Byte 12, converted to picoseconds and
153 * filled in with "default" normal values.
154 */
155 unsigned int determine_refresh_rate(unsigned int spd_refresh)
156 {
157 unsigned int refresh_time_ns[8] = {
158 15625000, /* 0 Normal 1.00x */
159 3900000, /* 1 Reduced .25x */
160 7800000, /* 2 Extended .50x */
161 31300000, /* 3 Extended 2.00x */
162 62500000, /* 4 Extended 4.00x */
163 125000000, /* 5 Extended 8.00x */
164 15625000, /* 6 Normal 1.00x filler */
165 15625000, /* 7 Normal 1.00x filler */
166 };
167
168 return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]);
169 }
170
171
172 long int
173 spd_sdram(void)
174 {
175 volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
176 spd_eeprom_t spd;
177 unsigned int n_ranks;
178 unsigned int rank_density;
179 unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits;
180 unsigned int odt_cfg, mode_odt_enable;
181 unsigned int refresh_clk;
182 #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
183 unsigned char clk_adjust;
184 #endif
185 unsigned int dqs_cfg;
186 unsigned char twr_clk, twtr_clk, twr_auto_clk;
187 unsigned int tCKmin_ps, tCKmax_ps;
188 unsigned int max_data_rate, effective_data_rate;
189 unsigned int busfreq;
190 unsigned sdram_cfg;
191 unsigned int memsize = 0;
192 unsigned char caslat, caslat_ctrl;
193 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
194 unsigned int trcd_clk;
195 unsigned int trtp_clk;
196 unsigned char cke_min_clk;
197 unsigned char add_lat;
198 unsigned char wr_lat;
199 unsigned char wr_data_delay;
200 unsigned char four_act;
201 unsigned char cpo;
202 unsigned char burst_len;
203 unsigned int mode_caslat;
204 unsigned char sdram_type;
205 unsigned char d_init;
206 unsigned int bnds;
207
208 /*
209 * Skip configuration if already configured.
210 * memsize is determined from last configured chip select.
211 */
212 if (ddr->cs0_config & 0x80000000) {
213 debug(" cs0 already configured, bnds=%x\n",ddr->cs0_bnds);
214 bnds = 0xfff & ddr->cs0_bnds;
215 if (bnds < 0xff) { /* do not add if at top of 4G */
216 memsize = (bnds + 1) << 4;
217 }
218 }
219 if (ddr->cs1_config & 0x80000000) {
220 debug(" cs1 already configured, bnds=%x\n",ddr->cs1_bnds);
221 bnds = 0xfff & ddr->cs1_bnds;
222 if (bnds < 0xff) { /* do not add if at top of 4G */
223 memsize = (bnds + 1) << 4; /* assume ordered bnds */
224 }
225 }
226 if (ddr->cs2_config & 0x80000000) {
227 debug(" cs2 already configured, bnds=%x\n",ddr->cs2_bnds);
228 bnds = 0xfff & ddr->cs2_bnds;
229 if (bnds < 0xff) { /* do not add if at top of 4G */
230 memsize = (bnds + 1) << 4;
231 }
232 }
233 if (ddr->cs3_config & 0x80000000) {
234 debug(" cs3 already configured, bnds=%x\n",ddr->cs3_bnds);
235 bnds = 0xfff & ddr->cs3_bnds;
236 if (bnds < 0xff) { /* do not add if at top of 4G */
237 memsize = (bnds + 1) << 4;
238 }
239 }
240
241 if (memsize) {
242 printf(" Reusing current %dMB configuration\n",memsize);
243 memsize = setup_laws_and_tlbs(memsize);
244 return memsize << 20;
245 }
246
247 /*
248 * Read SPD information.
249 */
250 CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd));
251
252 /*
253 * Check for supported memory module types.
254 */
255 if (spd.mem_type != SPD_MEMTYPE_DDR &&
256 spd.mem_type != SPD_MEMTYPE_DDR2) {
257 printf("Unable to locate DDR I or DDR II module.\n"
258 " Fundamental memory type is 0x%0x\n",
259 spd.mem_type);
260 return 0;
261 }
262
263 /*
264 * These test gloss over DDR I and II differences in interpretation
265 * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
266 * are not supported on DDR I; and not encoded on DDR II.
267 *
268 * Also note that the 8548 controller can support:
269 * 12 <= nrow <= 16
270 * and
271 * 8 <= ncol <= 11 (still, for DDR)
272 * 6 <= ncol <= 9 (for FCRAM)
273 */
274 if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
275 printf("DDR: Unsupported number of Row Addr lines: %d.\n",
276 spd.nrow_addr);
277 return 0;
278 }
279 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
280 printf("DDR: Unsupported number of Column Addr lines: %d.\n",
281 spd.ncol_addr);
282 return 0;
283 }
284
285 /*
286 * Determine the number of physical banks controlled by
287 * different Chip Select signals. This is not quite the
288 * same as the number of DIMM modules on the board. Feh.
289 */
290 if (spd.mem_type == SPD_MEMTYPE_DDR) {
291 n_ranks = spd.nrows;
292 } else {
293 n_ranks = (spd.nrows & 0x7) + 1;
294 }
295
296 debug("DDR: number of ranks = %d\n", n_ranks);
297
298 if (n_ranks > 2) {
299 printf("DDR: Only 2 chip selects are supported: %d\n",
300 n_ranks);
301 return 0;
302 }
303
304 #ifdef CONFIG_MPC8548
305 /*
306 * Adjust DDR II IO voltage biasing.
307 * Only 8548 rev 1 needs the fix
308 */
309 if ((SVR_SOC_VER(get_svr()) == SVR_8548_E) &&
310 (SVR_MJREV(get_svr()) == 1) &&
311 (spd.mem_type == SPD_MEMTYPE_DDR2)) {
312 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
313 gur->ddrioovcr = (0x80000000 /* Enable */
314 | 0x10000000);/* VSEL to 1.8V */
315 }
316 #endif
317
318 /*
319 * Determine the size of each Rank in bytes.
320 */
321 rank_density = compute_banksize(spd.mem_type, spd.row_dens);
322
323
324 /*
325 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
326 */
327 ddr->cs0_bnds = (rank_density >> 24) - 1;
328
329 /*
330 * ODT configuration recommendation from DDR Controller Chapter.
331 */
332 odt_rd_cfg = 0; /* Never assert ODT */
333 odt_wr_cfg = 0; /* Never assert ODT */
334 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
335 odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
336 #if 0
337 /* FIXME: How to determine the number of dimm modules? */
338 if (n_dimm_modules == 2) {
339 odt_rd_cfg = 1; /* Assert ODT on reads to CS0 */
340 }
341 #endif
342 }
343
344 ba_bits = 0;
345 if (spd.nbanks == 0x8)
346 ba_bits = 1;
347
348 ddr->cs0_config = ( 1 << 31
349 | (odt_rd_cfg << 20)
350 | (odt_wr_cfg << 16)
351 | (ba_bits << 14)
352 | (spd.nrow_addr - 12) << 8
353 | (spd.ncol_addr - 8) );
354 debug("\n");
355 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
356 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
357
358 if (n_ranks == 2) {
359 /*
360 * Eg: Bounds: 0x0f00_0000 to 0x1e0000_0000, second 256 Meg
361 */
362 ddr->cs1_bnds = ( (rank_density >> 8)
363 | ((rank_density >> (24 - 1)) - 1) );
364 ddr->cs1_config = ( 1<<31
365 | (odt_rd_cfg << 20)
366 | (odt_wr_cfg << 16)
367 | (spd.nrow_addr - 12) << 8
368 | (spd.ncol_addr - 8) );
369 debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
370 debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
371 }
372
373
374 /*
375 * Find the largest CAS by locating the highest 1 bit
376 * in the spd.cas_lat field. Translate it to a DDR
377 * controller field value:
378 *
379 * CAS Lat DDR I DDR II Ctrl
380 * Clocks SPD Bit SPD Bit Value
381 * ------- ------- ------- -----
382 * 1.0 0 0001
383 * 1.5 1 0010
384 * 2.0 2 2 0011
385 * 2.5 3 0100
386 * 3.0 4 3 0101
387 * 3.5 5 0110
388 * 4.0 4 0111
389 * 4.5 1000
390 * 5.0 5 1001
391 */
392 caslat = __ilog2(spd.cas_lat);
393 if ((spd.mem_type == SPD_MEMTYPE_DDR)
394 && (caslat > 5)) {
395 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
396 return 0;
397
398 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
399 && (caslat < 2 || caslat > 5)) {
400 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
401 spd.cas_lat);
402 return 0;
403 }
404 debug("DDR: caslat SPD bit is %d\n", caslat);
405
406 /*
407 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
408 * The SPD clk_cycle field (tCKmin) is measured in tenths of
409 * nanoseconds and represented as BCD.
410 */
411 tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
412 debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
413
414 /*
415 * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
416 */
417 max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
418 debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
419
420
421 /*
422 * Adjust the CAS Latency to allow for bus speeds that
423 * are slower than the DDR module.
424 */
425 busfreq = get_ddr_freq(0) / 1000000; /* MHz */
426
427 effective_data_rate = max_data_rate;
428 if (busfreq < 90) {
429 /* DDR rate out-of-range */
430 puts("DDR: platform frequency is not fit for DDR rate\n");
431 return 0;
432
433 } else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) {
434 /*
435 * busfreq 90~230 range, treated as DDR 200.
436 */
437 effective_data_rate = 200;
438 if (spd.clk_cycle3 == 0xa0) /* 10 ns */
439 caslat -= 2;
440 else if (spd.clk_cycle2 == 0xa0)
441 caslat--;
442
443 } else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) {
444 /*
445 * busfreq 230~280 range, treated as DDR 266.
446 */
447 effective_data_rate = 266;
448 if (spd.clk_cycle3 == 0x75) /* 7.5 ns */
449 caslat -= 2;
450 else if (spd.clk_cycle2 == 0x75)
451 caslat--;
452
453 } else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) {
454 /*
455 * busfreq 280~350 range, treated as DDR 333.
456 */
457 effective_data_rate = 333;
458 if (spd.clk_cycle3 == 0x60) /* 6.0 ns */
459 caslat -= 2;
460 else if (spd.clk_cycle2 == 0x60)
461 caslat--;
462
463 } else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) {
464 /*
465 * busfreq 350~460 range, treated as DDR 400.
466 */
467 effective_data_rate = 400;
468 if (spd.clk_cycle3 == 0x50) /* 5.0 ns */
469 caslat -= 2;
470 else if (spd.clk_cycle2 == 0x50)
471 caslat--;
472
473 } else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) {
474 /*
475 * busfreq 460~560 range, treated as DDR 533.
476 */
477 effective_data_rate = 533;
478 if (spd.clk_cycle3 == 0x3D) /* 3.75 ns */
479 caslat -= 2;
480 else if (spd.clk_cycle2 == 0x3D)
481 caslat--;
482
483 } else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) {
484 /*
485 * busfreq 560~700 range, treated as DDR 667.
486 */
487 effective_data_rate = 667;
488 if (spd.clk_cycle3 == 0x30) /* 3.0 ns */
489 caslat -= 2;
490 else if (spd.clk_cycle2 == 0x30)
491 caslat--;
492
493 } else if (700 <= busfreq) {
494 /*
495 * DDR rate out-of-range
496 */
497 printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
498 busfreq, max_data_rate);
499 return 0;
500 }
501
502
503 /*
504 * Convert caslat clocks to DDR controller value.
505 * Force caslat_ctrl to be DDR Controller field-sized.
506 */
507 if (spd.mem_type == SPD_MEMTYPE_DDR) {
508 caslat_ctrl = (caslat + 1) & 0x07;
509 } else {
510 caslat_ctrl = (2 * caslat - 1) & 0x0f;
511 }
512
513 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
514 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
515 caslat, caslat_ctrl);
516
517 /*
518 * Timing Config 0.
519 * Avoid writing for DDR I. The new PQ38 DDR controller
520 * dreams up non-zero default values to be backwards compatible.
521 */
522 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
523 unsigned char taxpd_clk = 8; /* By the book. */
524 unsigned char tmrd_clk = 2; /* By the book. */
525 unsigned char act_pd_exit = 2; /* Empirical? */
526 unsigned char pre_pd_exit = 6; /* Empirical? */
527
528 ddr->timing_cfg_0 = (0
529 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
530 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
531 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
532 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
533 );
534 #if 0
535 ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */
536 #endif
537 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
538
539 } else {
540 #if 0
541 /*
542 * Force extra cycles with 0xaa bits.
543 * Incidentally supply the dreamt-up backwards compat value!
544 */
545 ddr->timing_cfg_0 = 0x00110105; /* backwards compat value */
546 ddr->timing_cfg_0 |= 0xaa000000; /* extra cycles */
547 debug("DDR: HACK timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
548 #endif
549 }
550
551
552 /*
553 * Some Timing Config 1 values now.
554 * Sneak Extended Refresh Recovery in here too.
555 */
556
557 /*
558 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
559 * use conservative value.
560 * For DDR II, they are bytes 36 and 37, in quarter nanos.
561 */
562
563 if (spd.mem_type == SPD_MEMTYPE_DDR) {
564 twr_clk = 3; /* Clocks */
565 twtr_clk = 1; /* Clocks */
566 } else {
567 twr_clk = picos_to_clk(spd.twr * 250);
568 twtr_clk = picos_to_clk(spd.twtr * 250);
569 }
570
571 /*
572 * Calculate Trfc, in picos.
573 * DDR I: Byte 42 straight up in ns.
574 * DDR II: Byte 40 and 42 swizzled some, in ns.
575 */
576 if (spd.mem_type == SPD_MEMTYPE_DDR) {
577 trfc = spd.trfc * 1000; /* up to ps */
578 } else {
579 unsigned int byte40_table_ps[8] = {
580 0,
581 250,
582 330,
583 500,
584 660,
585 750,
586 0,
587 0
588 };
589
590 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
591 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
592 }
593 trfc_clk = picos_to_clk(trfc);
594
595 /*
596 * Trcd, Byte 29, from quarter nanos to ps and clocks.
597 */
598 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
599
600 /*
601 * Convert trfc_clk to DDR controller fields. DDR I should
602 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
603 * 8548 controller has an extended REFREC field of three bits.
604 * The controller automatically adds 8 clocks to this value,
605 * so preadjust it down 8 first before splitting it up.
606 */
607 trfc_low = (trfc_clk - 8) & 0xf;
608 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
609
610 /*
611 * Sneak in some Extended Refresh Recovery.
612 */
613 ddr->timing_cfg_3 = (trfc_high << 16);
614 debug("DDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
615
616 ddr->timing_cfg_1 =
617 (0
618 | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
619 | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
620 | (trcd_clk << 20) /* ACTTORW */
621 | (caslat_ctrl << 16) /* CASLAT */
622 | (trfc_low << 12) /* REFEC */
623 | ((twr_clk & 0x07) << 8) /* WRRREC */
624 | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
625 | ((twtr_clk & 0x07) << 0) /* WRTORD */
626 );
627
628 debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
629
630
631 /*
632 * Timing_Config_2
633 * Was: 0x00000800;
634 */
635
636 /*
637 * Additive Latency
638 * For DDR I, 0.
639 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
640 * which comes from Trcd, and also note that:
641 * add_lat + caslat must be >= 4
642 */
643 add_lat = 0;
644 if (spd.mem_type == SPD_MEMTYPE_DDR2
645 && (odt_wr_cfg || odt_rd_cfg)
646 && (caslat < 4)) {
647 add_lat = 4 - caslat;
648 if (add_lat > trcd_clk) {
649 add_lat = trcd_clk - 1;
650 }
651 }
652
653 /*
654 * Write Data Delay
655 * Historically 0x2 == 4/8 clock delay.
656 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
657 */
658 wr_data_delay = 3;
659
660 /*
661 * Write Latency
662 * Read to Precharge
663 * Minimum CKE Pulse Width.
664 * Four Activate Window
665 */
666 if (spd.mem_type == SPD_MEMTYPE_DDR) {
667 /*
668 * This is a lie. It should really be 1, but if it is
669 * set to 1, bits overlap into the old controller's
670 * otherwise unused ACSM field. If we leave it 0, then
671 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
672 */
673 wr_lat = 0;
674
675 trtp_clk = 2; /* By the book. */
676 cke_min_clk = 1; /* By the book. */
677 four_act = 1; /* By the book. */
678
679 } else {
680 wr_lat = caslat - 1;
681
682 /* Convert SPD value from quarter nanos to picos. */
683 trtp_clk = picos_to_clk(spd.trtp * 250);
684
685 cke_min_clk = 3; /* By the book. */
686 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
687 }
688
689 /*
690 * Empirically set ~MCAS-to-preamble override for DDR 2.
691 * Your milage will vary.
692 */
693 cpo = 0;
694 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
695 if (effective_data_rate <= 333) {
696 cpo = 0x7; /* READ_LAT + 5/4 */
697 } else {
698 cpo = 0x9; /* READ_LAT + 7/4 */
699 }
700 }
701
702 ddr->timing_cfg_2 = (0
703 | ((add_lat & 0x7) << 28) /* ADD_LAT */
704 | ((cpo & 0x1f) << 23) /* CPO */
705 | ((wr_lat & 0x7) << 19) /* WR_LAT */
706 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
707 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
708 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
709 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
710 );
711
712 debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
713
714
715 /*
716 * Determine the Mode Register Set.
717 *
718 * This is nominally part specific, but it appears to be
719 * consistent for all DDR I devices, and for all DDR II devices.
720 *
721 * caslat must be programmed
722 * burst length is always 4
723 * burst type is sequential
724 *
725 * For DDR I:
726 * operating mode is "normal"
727 *
728 * For DDR II:
729 * other stuff
730 */
731
732 mode_caslat = 0;
733
734 /*
735 * Table lookup from DDR I or II Device Operation Specs.
736 */
737 if (spd.mem_type == SPD_MEMTYPE_DDR) {
738 if (1 <= caslat && caslat <= 4) {
739 unsigned char mode_caslat_table[4] = {
740 0x5, /* 1.5 clocks */
741 0x2, /* 2.0 clocks */
742 0x6, /* 2.5 clocks */
743 0x3 /* 3.0 clocks */
744 };
745 mode_caslat = mode_caslat_table[caslat - 1];
746 } else {
747 puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
748 "2.5 and 3.0 clocks are supported.\n");
749 return 0;
750 }
751
752 } else {
753 if (2 <= caslat && caslat <= 5) {
754 mode_caslat = caslat;
755 } else {
756 puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
757 "4.0 and 5.0 clocks are supported.\n");
758 return 0;
759 }
760 }
761
762 /*
763 * Encoded Burst Lenght of 4.
764 */
765 burst_len = 2; /* Fiat. */
766
767 if (spd.mem_type == SPD_MEMTYPE_DDR) {
768 twr_auto_clk = 0; /* Historical */
769 } else {
770 /*
771 * Determine tCK max in picos. Grab tWR and convert to picos.
772 * Auto-precharge write recovery is:
773 * WR = roundup(tWR_ns/tCKmax_ns).
774 *
775 * Ponder: Is twr_auto_clk different than twr_clk?
776 */
777 tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
778 twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
779 }
780
781
782 /*
783 * Mode Reg in bits 16 ~ 31,
784 * Extended Mode Reg 1 in bits 0 ~ 15.
785 */
786 mode_odt_enable = 0x0; /* Default disabled */
787 if (odt_wr_cfg || odt_rd_cfg) {
788 /*
789 * Bits 6 and 2 in Extended MRS(1)
790 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
791 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
792 */
793 mode_odt_enable = 0x40; /* 150 Ohm */
794 }
795
796 ddr->sdram_mode =
797 (0
798 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
799 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
800 | (twr_auto_clk << 9) /* Write Recovery Autopre */
801 | (mode_caslat << 4) /* caslat */
802 | (burst_len << 0) /* Burst length */
803 );
804
805 debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode);
806
807
808 /*
809 * Clear EMRS2 and EMRS3.
810 */
811 ddr->sdram_mode_2 = 0;
812 debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
813
814 /*
815 * Determine Refresh Rate.
816 */
817 refresh_clk = determine_refresh_rate(spd.refresh & 0x7);
818
819 /*
820 * Set BSTOPRE to 0x100 for page mode
821 * If auto-charge is used, set BSTOPRE = 0
822 */
823 ddr->sdram_interval =
824 (0
825 | (refresh_clk & 0x3fff) << 16
826 | 0x100
827 );
828 debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
829
830 /*
831 * Is this an ECC DDR chip?
832 * But don't mess with it if the DDR controller will init mem.
833 */
834 #ifdef CONFIG_DDR_ECC
835 if (spd.config == 0x02) {
836 #ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER
837 ddr->err_disable = 0x0000000d;
838 #endif
839 ddr->err_sbe = 0x00ff0000;
840 }
841
842 debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
843 debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
844 #endif /* CONFIG_DDR_ECC */
845
846 asm("sync;isync;msync");
847 udelay(500);
848
849 /*
850 * SDRAM Cfg 2
851 */
852
853 /*
854 * When ODT is enabled, Chap 9 suggests asserting ODT to
855 * internal IOs only during reads.
856 */
857 odt_cfg = 0;
858 if (odt_rd_cfg | odt_wr_cfg) {
859 odt_cfg = 0x2; /* ODT to IOs during reads */
860 }
861
862 /*
863 * Try to use differential DQS with DDR II.
864 */
865 if (spd.mem_type == SPD_MEMTYPE_DDR) {
866 dqs_cfg = 0; /* No Differential DQS for DDR I */
867 } else {
868 dqs_cfg = 0x1; /* Differential DQS for DDR II */
869 }
870
871 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
872 /*
873 * Use the DDR controller to auto initialize memory.
874 */
875 d_init = 1;
876 ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
877 debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
878 #else
879 /*
880 * Memory will be initialized via DMA, or not at all.
881 */
882 d_init = 0;
883 #endif
884
885 ddr->sdram_cfg_2 = (0
886 | (dqs_cfg << 26) /* Differential DQS */
887 | (odt_cfg << 21) /* ODT */
888 | (d_init << 4) /* D_INIT auto init DDR */
889 );
890
891 debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
892
893
894 #ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
895 /*
896 * Setup the clock control.
897 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
898 * SDRAM_CLK_CNTL[5-7] = Clock Adjust
899 * 0110 3/4 cycle late
900 * 0111 7/8 cycle late
901 */
902 if (spd.mem_type == SPD_MEMTYPE_DDR)
903 clk_adjust = 0x6;
904 else
905 #ifdef CONFIG_MPC8568
906 /* Empirally setting clk_adjust */
907 clk_adjust = 0x6;
908 #else
909 clk_adjust = 0x7;
910 #endif
911
912 ddr->sdram_clk_cntl = (0
913 | 0x80000000
914 | (clk_adjust << 23)
915 );
916 debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
917 #endif
918
919 /*
920 * Figure out the settings for the sdram_cfg register.
921 * Build up the entire register in 'sdram_cfg' before writing
922 * since the write into the register will actually enable the
923 * memory controller; all settings must be done before enabling.
924 *
925 * sdram_cfg[0] = 1 (ddr sdram logic enable)
926 * sdram_cfg[1] = 1 (self-refresh-enable)
927 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
928 * 010 DDR 1 SDRAM
929 * 011 DDR 2 SDRAM
930 */
931 sdram_type = (spd.mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
932 sdram_cfg = (0
933 | (1 << 31) /* Enable */
934 | (1 << 30) /* Self refresh */
935 | (sdram_type << 24) /* SDRAM type */
936 );
937
938 /*
939 * sdram_cfg[3] = RD_EN - registered DIMM enable
940 * A value of 0x26 indicates micron registered DIMMS (micron.com)
941 */
942 if (spd.mem_type == SPD_MEMTYPE_DDR && spd.mod_attr == 0x26) {
943 sdram_cfg |= 0x10000000; /* RD_EN */
944 }
945
946 #if defined(CONFIG_DDR_ECC)
947 /*
948 * If the user wanted ECC (enabled via sdram_cfg[2])
949 */
950 if (spd.config == 0x02) {
951 sdram_cfg |= 0x20000000; /* ECC_EN */
952 }
953 #endif
954
955 /*
956 * REV1 uses 1T timing.
957 * REV2 may use 1T or 2T as configured by the user.
958 */
959 {
960 uint pvr = get_pvr();
961
962 if (pvr != PVR_85xx_REV1) {
963 #if defined(CONFIG_DDR_2T_TIMING)
964 /*
965 * Enable 2T timing by setting sdram_cfg[16].
966 */
967 sdram_cfg |= 0x8000; /* 2T_EN */
968 #endif
969 }
970 }
971
972 /*
973 * 200 painful micro-seconds must elapse between
974 * the DDR clock setup and the DDR config enable.
975 */
976 udelay(200);
977
978 /*
979 * Go!
980 */
981 ddr->sdram_cfg = sdram_cfg;
982
983 asm("sync;isync;msync");
984 udelay(500);
985
986 debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg);
987
988
989 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
990 /*
991 * Poll until memory is initialized.
992 * 512 Meg at 400 might hit this 200 times or so.
993 */
994 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
995 udelay(1000);
996 }
997 #endif
998
999
1000 /*
1001 * Figure out memory size in Megabytes.
1002 */
1003 memsize = n_ranks * rank_density / 0x100000;
1004
1005 /*
1006 * Establish Local Access Window and TLB mappings for DDR memory.
1007 */
1008 memsize = setup_laws_and_tlbs(memsize);
1009 if (memsize == 0) {
1010 return 0;
1011 }
1012
1013 return memsize * 1024 * 1024;
1014 }
1015
1016
1017 /*
1018 * Setup Local Access Window and TLB1 mappings for the requested
1019 * amount of memory. Returns the amount of memory actually mapped
1020 * (usually the original request size), or 0 on error.
1021 */
1022
1023 static unsigned int
1024 setup_laws_and_tlbs(unsigned int memsize)
1025 {
1026 unsigned int tlb_size;
1027 unsigned int law_size;
1028 unsigned int ram_tlb_index;
1029 unsigned int ram_tlb_address;
1030
1031 /*
1032 * Determine size of each TLB1 entry.
1033 */
1034 switch (memsize) {
1035 case 16:
1036 case 32:
1037 tlb_size = BOOKE_PAGESZ_16M;
1038 break;
1039 case 64:
1040 case 128:
1041 tlb_size = BOOKE_PAGESZ_64M;
1042 break;
1043 case 256:
1044 case 512:
1045 tlb_size = BOOKE_PAGESZ_256M;
1046 break;
1047 case 1024:
1048 case 2048:
1049 if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
1050 tlb_size = BOOKE_PAGESZ_1G;
1051 else
1052 tlb_size = BOOKE_PAGESZ_256M;
1053 break;
1054 default:
1055 puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n");
1056
1057 /*
1058 * The memory was not able to be mapped.
1059 * Default to a small size.
1060 */
1061 tlb_size = BOOKE_PAGESZ_64M;
1062 memsize=64;
1063 break;
1064 }
1065
1066 /*
1067 * Configure DDR TLB1 entries.
1068 * Starting at TLB1 8, use no more than 8 TLB1 entries.
1069 */
1070 ram_tlb_index = 8;
1071 ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
1072 while (ram_tlb_address < (memsize * 1024 * 1024)
1073 && ram_tlb_index < 16) {
1074 set_tlb(1, ram_tlb_address, ram_tlb_address,
1075 MAS3_SX|MAS3_SW|MAS3_SR, 0,
1076 0, ram_tlb_index, tlb_size, 1);
1077
1078 ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
1079 ram_tlb_index++;
1080 }
1081
1082
1083 /*
1084 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
1085 */
1086 law_size = 19 + __ilog2(memsize);
1087
1088 /*
1089 * Set up LAWBAR for all of DDR.
1090 */
1091
1092 #ifdef CONFIG_FSL_LAW
1093 set_next_law(CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
1094 #endif
1095
1096 /*
1097 * Confirm that the requested amount of memory was mapped.
1098 */
1099 return memsize;
1100 }
1101
1102 #endif /* CONFIG_SPD_EEPROM */
1103
1104
1105 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1106
1107 /*
1108 * Initialize all of memory for ECC, then enable errors.
1109 */
1110
1111 void
1112 ddr_enable_ecc(unsigned int dram_size)
1113 {
1114 uint *p = 0;
1115 uint i = 0;
1116 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
1117
1118 dma_init();
1119
1120 for (*p = 0; p < (uint *)(8 * 1024); p++) {
1121 if (((unsigned int)p & 0x1f) == 0) {
1122 ppcDcbz((unsigned long) p);
1123 }
1124 *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
1125 if (((unsigned int)p & 0x1c) == 0x1c) {
1126 ppcDcbf((unsigned long) p);
1127 }
1128 }
1129
1130 dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
1131 dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
1132 dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
1133 dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
1134 dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
1135 dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
1136 dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
1137 dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
1138 dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
1139 dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
1140
1141 for (i = 1; i < dram_size / 0x800000; i++) {
1142 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
1143 }
1144
1145 /*
1146 * Enable errors for ECC.
1147 */
1148 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
1149 ddr->err_disable = 0x00000000;
1150 asm("sync;isync;msync");
1151 debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
1152 }
1153
1154 #endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
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