cpu/mpc85xx/speed.c

   1 /*
   2  * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2003 Motorola Inc.
   5  * Xianghua Xiao, (X.Xiao@motorola.com)
   6  *
   7  * (C) Copyright 2000
   8  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <ppc_asm.tmpl>
  31 #include <asm/processor.h>
  32 #include <asm/io.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 /* --------------------------------------------------------------- */
  37
  38 void get_sys_info (sys_info_t * sysInfo)
  39 {
  40         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  41 #ifdef CONFIG_FSL_CORENET
  42         volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
  43
  44         const u8 core_cplx_PLL[16] = {
  45                 [ 0] = 0,       /* CC1 PPL / 1 */
  46                 [ 1] = 0,       /* CC1 PPL / 2 */
  47                 [ 2] = 0,       /* CC1 PPL / 4 */
  48                 [ 4] = 1,       /* CC2 PPL / 1 */
  49                 [ 5] = 1,       /* CC2 PPL / 2 */
  50                 [ 6] = 1,       /* CC2 PPL / 4 */
  51                 [ 8] = 2,       /* CC3 PPL / 1 */
  52                 [ 9] = 2,       /* CC3 PPL / 2 */
  53                 [10] = 2,       /* CC3 PPL / 4 */
  54                 [12] = 3,       /* CC4 PPL / 1 */
  55                 [13] = 3,       /* CC4 PPL / 2 */
  56                 [14] = 3,       /* CC4 PPL / 4 */
  57         };
  58
  59         const u8 core_cplx_PLL_div[16] = {
  60                 [ 0] = 1,       /* CC1 PPL / 1 */
  61                 [ 1] = 2,       /* CC1 PPL / 2 */
  62                 [ 2] = 4,       /* CC1 PPL / 4 */
  63                 [ 4] = 1,       /* CC2 PPL / 1 */
  64                 [ 5] = 2,       /* CC2 PPL / 2 */
  65                 [ 6] = 4,       /* CC2 PPL / 4 */
  66                 [ 8] = 1,       /* CC3 PPL / 1 */
  67                 [ 9] = 2,       /* CC3 PPL / 2 */
  68                 [10] = 4,       /* CC3 PPL / 4 */
  69                 [12] = 1,       /* CC4 PPL / 1 */
  70                 [13] = 2,       /* CC4 PPL / 2 */
  71                 [14] = 4,       /* CC4 PPL / 4 */
  72         };
  73         uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
  74         unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
  75
  76         sysInfo->freqSystemBus = sysclk;
  77         sysInfo->freqDDRBus = sysclk;
  78         freqCC_PLL[0] = sysclk;
  79         freqCC_PLL[1] = sysclk;
  80         freqCC_PLL[2] = sysclk;
  81         freqCC_PLL[3] = sysclk;
  82
  83         sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf;
  84         sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf);
  85         freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
  86         freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
  87         freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
  88         freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
  89
  90         rcw_tmp = in_be32(&gur->rcwsr[3]);
  91         for (i = 0; i < cpu_numcores(); i++) {
  92                 u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
  93                 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
  94
  95                 sysInfo->freqProcessor[i] =
  96                          freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
  97         }
  98
  99 #define PME_CLK_SEL     0x80000000
 100 #define FM1_CLK_SEL     0x40000000
 101 #define FM2_CLK_SEL     0x20000000
 102         rcw_tmp = in_be32(&gur->rcwsr[7]);
 103
 104 #ifdef CONFIG_SYS_DPAA_PME
 105         if (rcw_tmp & PME_CLK_SEL)
 106                 sysInfo->freqPME = freqCC_PLL[2] / 2;
 107         else
 108                 sysInfo->freqPME = sysInfo->freqSystemBus / 2;
 109 #endif
 110
 111 #ifdef CONFIG_SYS_DPAA_FMAN
 112         if (rcw_tmp & FM1_CLK_SEL)
 113                 sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
 114         else
 115                 sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
 116 #if (CONFIG_SYS_NUM_FMAN) == 2
 117         if (rcw_tmp & FM2_CLK_SEL)
 118                 sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
 119         else
 120                 sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
 121 #endif
 122 #endif
 123
 124 #else
 125         uint plat_ratio,e500_ratio,half_freqSystemBus;
 126         uint lcrr_div;
 127         int i;
 128 #ifdef CONFIG_QE
 129         u32 qe_ratio;
 130 #endif
 131
 132         plat_ratio = (gur->porpllsr) & 0x0000003e;
 133         plat_ratio >>= 1;
 134         sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
 135
 136         /* Divide before multiply to avoid integer
 137          * overflow for processor speeds above 2GHz */
 138         half_freqSystemBus = sysInfo->freqSystemBus/2;
 139         for (i = 0; i < cpu_numcores(); i++) {
 140                 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
 141                 sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
 142         }
 143
 144         /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
 145         sysInfo->freqDDRBus = sysInfo->freqSystemBus;
 146
 147 #ifdef CONFIG_DDR_CLK_FREQ
 148         {
 149                 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
 150                         >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 151                 if (ddr_ratio != 0x7)
 152                         sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
 153         }
 154 #endif
 155 #endif
 156
 157 #ifdef CONFIG_QE
 158         qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
 159                         >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
 160         sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
 161 #endif
 162
 163 #if defined(CONFIG_SYS_LBC_LCRR)
 164         /* We will program LCRR to this value later */
 165         lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
 166 #else
 167         {
 168             volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 169             lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
 170         }
 171 #endif
 172         if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
 173 #if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
 174     !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
 175                 /*
 176                  * Yes, the entire PQ38 family use the same
 177                  * bit-representation for twice the clock divider values.
 178                  */
 179                 lcrr_div *= 2;
 180 #endif
 181                 sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
 182         } else {
 183                 /* In case anyone cares what the unknown value is */
 184                 sysInfo->freqLocalBus = lcrr_div;
 185         }
 186 }
 187
 188
 189 int get_clocks (void)
 190 {
 191         sys_info_t sys_info;
 192 #ifdef CONFIG_MPC8544
 193         volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
 194 #endif
 195 #if defined(CONFIG_CPM2)
 196         volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
 197         uint sccr, dfbrg;
 198
 199         /* set VCO = 4 * BRG */
 200         cpm->im_cpm_intctl.sccr &= 0xfffffffc;
 201         sccr = cpm->im_cpm_intctl.sccr;
 202         dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
 203 #endif
 204         get_sys_info (&sys_info);
 205         gd->cpu_clk = sys_info.freqProcessor[0];
 206         gd->bus_clk = sys_info.freqSystemBus;
 207         gd->mem_clk = sys_info.freqDDRBus;
 208         gd->lbc_clk = sys_info.freqLocalBus;
 209
 210 #ifdef CONFIG_QE
 211         gd->qe_clk = sys_info.freqQE;
 212         gd->brg_clk = gd->qe_clk / 2;
 213 #endif
 214         /*
 215          * The base clock for I2C depends on the actual SOC.  Unfortunately,
 216          * there is no pattern that can be used to determine the frequency, so
 217          * the only choice is to look up the actual SOC number and use the value
 218          * for that SOC. This information is taken from application note
 219          * AN2919.
 220          */
 221 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
 222         defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
 223         gd->i2c1_clk = sys_info.freqSystemBus;
 224 #elif defined(CONFIG_MPC8544)
 225         /*
 226          * On the 8544, the I2C clock is the same as the SEC clock.  This can be
 227          * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
 228          * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
 229          * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
 230          * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
 231          */
 232         if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
 233                 gd->i2c1_clk = sys_info.freqSystemBus / 3;
 234         else
 235                 gd->i2c1_clk = sys_info.freqSystemBus / 2;
 236 #else
 237         /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
 238         gd->i2c1_clk = sys_info.freqSystemBus / 2;
 239 #endif
 240         gd->i2c2_clk = gd->i2c1_clk;
 241
 242 #if defined(CONFIG_FSL_ESDHC)
 243 #ifdef CONFIG_MPC8569
 244         gd->sdhc_clk = gd->bus_clk;
 245 #else
 246         gd->sdhc_clk = gd->bus_clk / 2;
 247 #endif
 248 #endif /* defined(CONFIG_FSL_ESDHC) */
 249
 250 #if defined(CONFIG_CPM2)
 251         gd->vco_out = 2*sys_info.freqSystemBus;
 252         gd->cpm_clk = gd->vco_out / 2;
 253         gd->scc_clk = gd->vco_out / 4;
 254         gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
 255 #endif
 256
 257         if(gd->cpu_clk != 0) return (0);
 258         else return (1);
 259 }
 260
 261
 262 /********************************************
 263  * get_bus_freq
 264  * return system bus freq in Hz
 265  *********************************************/
 266 ulong get_bus_freq (ulong dummy)
 267 {
 268         return gd->bus_clk;
 269 }
 270
 271 /********************************************
 272  * get_ddr_freq
 273  * return ddr bus freq in Hz
 274  *********************************************/
 275 ulong get_ddr_freq (ulong dummy)
 276 {
 277         return gd->mem_clk;
 278 }