cpu/mpc85xx/tlb.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/processor.h>
  28 #include <asm/mmu.h>
  29
  30 void set_tlb(u8 tlb, u32 epn, u64 rpn,
  31              u8 perms, u8 wimge,
  32              u8 ts, u8 esel, u8 tsize, u8 iprot)
  33 {
  34         u32 _mas0, _mas1, _mas2, _mas3, _mas7;
  35
  36         _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
  37         _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
  38         _mas2 = FSL_BOOKE_MAS2(epn, wimge);
  39         _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
  40         _mas7 = rpn >> 32;
  41
  42         mtspr(MAS0, _mas0);
  43         mtspr(MAS1, _mas1);
  44         mtspr(MAS2, _mas2);
  45         mtspr(MAS3, _mas3);
  46 #ifdef CONFIG_ENABLE_36BIT_PHYS
  47         mtspr(MAS7, _mas7);
  48 #endif
  49         asm volatile("isync;msync;tlbwe;isync");
  50 }
  51
  52 void disable_tlb(u8 esel)
  53 {
  54         u32 _mas0, _mas1, _mas2, _mas3, _mas7;
  55
  56         _mas0 = FSL_BOOKE_MAS0(1, esel, 0);
  57         _mas1 = 0;
  58         _mas2 = 0;
  59         _mas3 = 0;
  60         _mas7 = 0;
  61
  62         mtspr(MAS0, _mas0);
  63         mtspr(MAS1, _mas1);
  64         mtspr(MAS2, _mas2);
  65         mtspr(MAS3, _mas3);
  66 #ifdef CONFIG_ENABLE_36BIT_PHYS
  67         mtspr(MAS7, _mas7);
  68 #endif
  69         asm volatile("isync;msync;tlbwe;isync");
  70 }
  71
  72 void invalidate_tlb(u8 tlb)
  73 {
  74         if (tlb == 0)
  75                 mtspr(MMUCSR0, 0x4);
  76         if (tlb == 1)
  77                 mtspr(MMUCSR0, 0x2);
  78 }
  79
  80 void init_tlbs(void)
  81 {
  82         int i;
  83
  84         for (i = 0; i < num_tlb_entries; i++) {
  85                 set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn,
  86                         tlb_table[i].perms, tlb_table[i].wimge,
  87                         tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize,
  88                         tlb_table[i].iprot);
  89         }
  90
  91         return ;
  92 }
  93
  94 unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
  95 {
  96         unsigned int tlb_size;
  97         unsigned int ram_tlb_index;
  98         unsigned int ram_tlb_address;
  99
 100         /*
 101          * Determine size of each TLB1 entry.
 102          */
 103         switch (memsize_in_meg) {
 104         case 16:
 105         case 32:
 106                 tlb_size = BOOKE_PAGESZ_16M;
 107                 break;
 108         case 64:
 109         case 128:
 110                 tlb_size = BOOKE_PAGESZ_64M;
 111                 break;
 112         case 256:
 113         case 512:
 114                 tlb_size = BOOKE_PAGESZ_256M;
 115                 break;
 116         case 1024:
 117         case 2048:
 118                 if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
 119                         tlb_size = BOOKE_PAGESZ_1G;
 120                 else
 121                         tlb_size = BOOKE_PAGESZ_256M;
 122                 break;
 123         default:
 124                 puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G"
 125                         " and 2G are supported.\n");
 126
 127                 /*
 128                  * The memory was not able to be mapped.
 129                  * Default to a small size.
 130                  */
 131                 tlb_size = BOOKE_PAGESZ_64M;
 132                 memsize_in_meg = 64;
 133                 break;
 134         }
 135
 136         /*
 137          * Configure DDR TLB1 entries.
 138          * Starting at TLB1 8, use no more than 8 TLB1 entries.
 139          */
 140         ram_tlb_index = 8;
 141         ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
 142         while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
 143               && ram_tlb_index < 16) {
 144                 set_tlb(1, ram_tlb_address, ram_tlb_address,
 145                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
 146                         0, ram_tlb_index, tlb_size, 1);
 147
 148                 ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
 149                 ram_tlb_index++;
 150         }
 151
 152         /*
 153          * Confirm that the requested amount of memory was mapped.
 154          */
 155         return memsize_in_meg;
 156 }