cpu/mpc8xx/cpu.c

   1 /*
   2  * (C) Copyright 2000-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * m8xx.c
  26  *
  27  * CPU specific code
  28  *
  29  * written or collected and sometimes rewritten by
  30  * Magnus Damm <damm@bitsmart.com>
  31  *
  32  * minor modifications by
  33  * Wolfgang Denk <wd@denx.de>
  34  */
  35
  36 #include <common.h>
  37 #include <watchdog.h>
  38 #include <command.h>
  39 #include <mpc8xx.h>
  40 #include <asm/cache.h>
  41
  42 static char *cpu_warning = "\n         " \
  43         "*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
  44
  45 #if ((defined(CONFIG_MPC86x) || defined(CONFIG_MPC855)) && \
  46      !defined(CONFIG_MPC862))
  47
  48 static int check_CPU (long clock, uint pvr, uint immr)
  49 {
  50         char *id_str =
  51 # if defined(CONFIG_MPC855)
  52         "PC855";
  53 # elif defined(CONFIG_MPC860P)
  54         "PC860P";
  55 # else
  56         NULL;
  57 # endif
  58         volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
  59         uint k, m;
  60         char buf[32];
  61         char pre = 'X';
  62         char *mid = "xx";
  63         char *suf;
  64
  65         /* the highest 16 bits should be 0x0050 for a 860 */
  66
  67         if ((pvr >> 16) != 0x0050)
  68                 return -1;
  69
  70         k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
  71         m = 0;
  72         suf = "";
  73
  74         /*
  75          * Some boards use sockets so different CPUs can be used.
  76          * We have to check chip version in run time.
  77          */
  78         switch (k) {
  79         case 0x00020001: pre = 'P'; break;
  80         case 0x00030001: break;
  81         case 0x00120003: suf = "A"; break;
  82         case 0x00130003: suf = "A3"; break;
  83
  84         case 0x00200004: suf = "B"; break;
  85
  86         case 0x00300004: suf = "C"; break;
  87         case 0x00310004: suf = "C1"; m = 1; break;
  88
  89         case 0x00200064: mid = "SR"; suf = "B"; break;
  90         case 0x00300065: mid = "SR"; suf = "C"; break;
  91         case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
  92         case 0x05010000: suf = "D3"; m = 1; break;
  93         case 0x05020000: suf = "D4"; m = 1; break;
  94                 /* this value is not documented anywhere */
  95         case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
  96                 /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
  97         case 0x08010004:                /* Rev. A.0 */
  98                 suf = "A";
  99                 /* fall through */
 100         case 0x08000003:                /* Rev. 0.3 */
 101                 pre = 'M'; m = 1;
 102                 if (id_str == NULL)
 103                         id_str =
 104 # if defined(CONFIG_MPC852T)
 105                 "PC852T";
 106 # elif defined(CONFIG_MPC859T)
 107                 "PC859T";
 108 # elif defined(CONFIG_MPC859DSL)
 109                 "PC859DSL";
 110 # elif defined(CONFIG_MPC866T)
 111                 "PC866T";
 112 # else
 113                 "PC866x"; /* Unknown chip from MPC866 family */
 114 # endif
 115                 break;
 116         case 0x09000000: pre = 'M'; mid = suf = ""; m = 1;
 117                 if (id_str == NULL)
 118                         id_str = "PC885"; /* 870/875/880/885 */
 119                 break;
 120
 121         default: suf = NULL; break;
 122         }
 123
 124         if (id_str == NULL)
 125                 id_str = "PC86x";       /* Unknown 86x chip */
 126         if (suf)
 127                 printf ("%c%s%sZPnn%s", pre, id_str, mid, suf);
 128         else
 129                 printf ("unknown M%s (0x%08x)", id_str, k);
 130
 131
 132 #if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX)
 133         printf (" at %s MHz [%d.%d...%d.%d MHz]\n       ",
 134                 strmhz (buf, clock),
 135                 CFG_8xx_CPUCLK_MIN / 1000000,
 136                 ((CFG_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
 137                 CFG_8xx_CPUCLK_MAX / 1000000,
 138                 ((CFG_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
 139         );
 140 #else
 141         printf (" at %s MHz: ", strmhz (buf, clock));
 142 #endif
 143         printf ("%u kB I-Cache %u kB D-Cache",
 144                 checkicache () >> 10,
 145                 checkdcache () >> 10
 146         );
 147
 148         /* do we have a FEC (860T/P or 852/859/866/885)? */
 149
 150         immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
 151         if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
 152                 printf (" FEC present");
 153         }
 154
 155         if (!m) {
 156                 puts (cpu_warning);
 157         }
 158
 159         putc ('\n');
 160
 161 #ifdef DEBUG
 162         if(clock != measure_gclk()) {
 163             printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
 164         }
 165 #endif
 166
 167         return 0;
 168 }
 169
 170 #elif defined(CONFIG_MPC862)
 171
 172 static int check_CPU (long clock, uint pvr, uint immr)
 173 {
 174         volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
 175         uint k, m;
 176         char buf[32];
 177         char pre = 'X';
 178         char *mid = "xx";
 179         char *suf;
 180
 181         /* the highest 16 bits should be 0x0050 for a 8xx */
 182
 183         if ((pvr >> 16) != 0x0050)
 184                 return -1;
 185
 186         k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
 187         m = 0;
 188
 189         switch (k) {
 190
 191                 /* this value is not documented anywhere */
 192         case 0x06000000: mid = "P"; suf = "0"; break;
 193         case 0x06010001: mid = "P"; suf = "A"; m = 1; break;
 194         case 0x07000003: mid = "P"; suf = "B"; m = 1; break;
 195         default: suf = NULL; break;
 196         }
 197
 198 #ifndef CONFIG_MPC857
 199         if (suf)
 200                 printf ("%cPC862%sZPnn%s", pre, mid, suf);
 201         else
 202                 printf ("unknown MPC862 (0x%08x)", k);
 203 #else
 204         if (suf)
 205                 printf ("%cPC857TZPnn%s", pre, suf); /* only 857T tested right now! */
 206         else
 207                 printf ("unknown MPC857 (0x%08x)", k);
 208 #endif
 209
 210         printf (" at %s MHz:", strmhz (buf, clock));
 211
 212         printf (" %u kB I-Cache", checkicache () >> 10);
 213         printf (" %u kB D-Cache", checkdcache () >> 10);
 214
 215         /* lets check and see if we're running on a 862T (or P?) */
 216
 217         immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
 218         if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
 219                 printf (" FEC present");
 220         }
 221
 222         if (!m) {
 223                 puts (cpu_warning);
 224         }
 225
 226         putc ('\n');
 227
 228         return 0;
 229 }
 230
 231 #elif defined(CONFIG_MPC823)
 232
 233 static int check_CPU (long clock, uint pvr, uint immr)
 234 {
 235         volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
 236         uint k, m;
 237         char buf[32];
 238         char *suf;
 239
 240         /* the highest 16 bits should be 0x0050 for a 8xx */
 241
 242         if ((pvr >> 16) != 0x0050)
 243                 return -1;
 244
 245         k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
 246         m = 0;
 247
 248         switch (k) {
 249                 /* MPC823 */
 250         case 0x20000000: suf = "0"; break;
 251         case 0x20010000: suf = "0.1"; break;
 252         case 0x20020000: suf = "Z2/3"; break;
 253         case 0x20020001: suf = "Z3"; break;
 254         case 0x21000000: suf = "A"; break;
 255         case 0x21010000: suf = "B"; m = 1; break;
 256         case 0x21010001: suf = "B2"; m = 1; break;
 257                 /* MPC823E */
 258         case 0x24010000: suf = NULL;
 259                         puts ("PPC823EZTnnB2");
 260                         m = 1;
 261                         break;
 262         default:
 263                         suf = NULL;
 264                         printf ("unknown MPC823 (0x%08x)", k);
 265                         break;
 266         }
 267         if (suf)
 268                 printf ("PPC823ZTnn%s", suf);
 269
 270         printf (" at %s MHz:", strmhz (buf, clock));
 271
 272         printf (" %u kB I-Cache", checkicache () >> 10);
 273         printf (" %u kB D-Cache", checkdcache () >> 10);
 274
 275         /* lets check and see if we're running on a 860T (or P?) */
 276
 277         immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
 278         if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
 279                 puts (" FEC present");
 280         }
 281
 282         if (!m) {
 283                 puts (cpu_warning);
 284         }
 285
 286         putc ('\n');
 287
 288         return 0;
 289 }
 290
 291 #elif defined(CONFIG_MPC850)
 292
 293 static int check_CPU (long clock, uint pvr, uint immr)
 294 {
 295         volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
 296         uint k, m;
 297         char buf[32];
 298
 299         /* the highest 16 bits should be 0x0050 for a 8xx */
 300
 301         if ((pvr >> 16) != 0x0050)
 302                 return -1;
 303
 304         k = (immr << 16) | *((ushort *) & immap->im_cpm.cp_dparam[0xB0]);
 305         m = 0;
 306
 307         switch (k) {
 308         case 0x20020001:
 309                 printf ("XPC850xxZT");
 310                 break;
 311         case 0x21000065:
 312                 printf ("XPC850xxZTA");
 313                 break;
 314         case 0x21010067:
 315                 printf ("XPC850xxZTB");
 316                 m = 1;
 317                 break;
 318         case 0x21020068:
 319                 printf ("XPC850xxZTC");
 320                 m = 1;
 321                 break;
 322         default:
 323                 printf ("unknown MPC850 (0x%08x)", k);
 324         }
 325         printf (" at %s MHz:", strmhz (buf, clock));
 326
 327         printf (" %u kB I-Cache", checkicache () >> 10);
 328         printf (" %u kB D-Cache", checkdcache () >> 10);
 329
 330         /* lets check and see if we're running on a 850T (or P?) */
 331
 332         immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
 333         if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
 334                 printf (" FEC present");
 335         }
 336
 337         if (!m) {
 338                 puts (cpu_warning);
 339         }
 340
 341         putc ('\n');
 342
 343         return 0;
 344 }
 345 #else
 346 #error CPU undefined
 347 #endif
 348 /* ------------------------------------------------------------------------- */
 349
 350 int checkcpu (void)
 351 {
 352         DECLARE_GLOBAL_DATA_PTR;
 353
 354         ulong clock = gd->cpu_clk;
 355         uint immr = get_immr (0);       /* Return full IMMR contents */
 356         uint pvr = get_pvr ();
 357
 358         puts ("CPU:   ");
 359
 360         /* 850 has PARTNUM 20 */
 361         /* 801 has PARTNUM 10 */
 362         return check_CPU (clock, pvr, immr);
 363 }
 364
 365 /* ------------------------------------------------------------------------- */
 366 /* L1 i-cache                                                                */
 367 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB)              */
 368 /* the 860 P (plus) has 256 sets of 16 bytes in 4 ways (= 16 kB)             */
 369
 370 int checkicache (void)
 371 {
 372         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 373         volatile memctl8xx_t *memctl = &immap->im_memctl;
 374         u32 cacheon = rd_ic_cst () & IDC_ENABLED;
 375
 376 #ifdef CONFIG_IP86x
 377         u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
 378 #else
 379         u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
 380 #endif
 381         u32 m;
 382         u32 lines = -1;
 383
 384         wr_ic_cst (IDC_UNALL);
 385         wr_ic_cst (IDC_INVALL);
 386         wr_ic_cst (IDC_DISABLE);
 387         __asm__ volatile ("isync");
 388
 389         while (!((m = rd_ic_cst ()) & IDC_CERR2)) {
 390                 wr_ic_adr (k);
 391                 wr_ic_cst (IDC_LDLCK);
 392                 __asm__ volatile ("isync");
 393
 394                 lines++;
 395                 k += 0x10;                              /* the number of bytes in a cacheline */
 396         }
 397
 398         wr_ic_cst (IDC_UNALL);
 399         wr_ic_cst (IDC_INVALL);
 400
 401         if (cacheon)
 402                 wr_ic_cst (IDC_ENABLE);
 403         else
 404                 wr_ic_cst (IDC_DISABLE);
 405
 406         __asm__ volatile ("isync");
 407
 408         return lines << 4;
 409 };
 410
 411 /* ------------------------------------------------------------------------- */
 412 /* L1 d-cache                                                                */
 413 /* the standard 860 has 128 sets of 16 bytes in 2 ways (= 4 kB)              */
 414 /* the 860 P (plus) has 256 sets of 16 bytes in 2 ways (= 8 kB)              */
 415 /* call with cache disabled                                                  */
 416
 417 int checkdcache (void)
 418 {
 419         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 420         volatile memctl8xx_t *memctl = &immap->im_memctl;
 421         u32 cacheon = rd_dc_cst () & IDC_ENABLED;
 422
 423 #ifdef CONFIG_IP86x
 424         u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
 425 #else
 426         u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
 427 #endif
 428         u32 m;
 429         u32 lines = -1;
 430
 431         wr_dc_cst (IDC_UNALL);
 432         wr_dc_cst (IDC_INVALL);
 433         wr_dc_cst (IDC_DISABLE);
 434
 435         while (!((m = rd_dc_cst ()) & IDC_CERR2)) {
 436                 wr_dc_adr (k);
 437                 wr_dc_cst (IDC_LDLCK);
 438                 lines++;
 439                 k += 0x10;      /* the number of bytes in a cacheline */
 440         }
 441
 442         wr_dc_cst (IDC_UNALL);
 443         wr_dc_cst (IDC_INVALL);
 444
 445         if (cacheon)
 446                 wr_dc_cst (IDC_ENABLE);
 447         else
 448                 wr_dc_cst (IDC_DISABLE);
 449
 450         return lines << 4;
 451 };
 452
 453 /* ------------------------------------------------------------------------- */
 454
 455 void upmconfig (uint upm, uint * table, uint size)
 456 {
 457         uint i;
 458         uint addr = 0;
 459         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 460         volatile memctl8xx_t *memctl = &immap->im_memctl;
 461
 462         for (i = 0; i < size; i++) {
 463                 memctl->memc_mdr = table[i];    /* (16-15) */
 464                 memctl->memc_mcr = addr | upm;  /* (16-16) */
 465                 addr++;
 466         }
 467 }
 468
 469 /* ------------------------------------------------------------------------- */
 470
 471 #ifndef CONFIG_LWMON
 472
 473 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 474 {
 475         ulong msr, addr;
 476
 477         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 478
 479         immap->im_clkrst.car_plprcr |= PLPRCR_CSR;      /* Checkstop Reset enable */
 480
 481         /* Interrupts and MMU off */
 482         __asm__ volatile ("mtspr    81, 0");
 483         __asm__ volatile ("mfmsr    %0":"=r" (msr));
 484
 485         msr &= ~0x1030;
 486         __asm__ volatile ("mtmsr    %0"::"r" (msr));
 487
 488         /*
 489          * Trying to execute the next instruction at a non-existing address
 490          * should cause a machine check, resulting in reset
 491          */
 492 #ifdef CFG_RESET_ADDRESS
 493         addr = CFG_RESET_ADDRESS;
 494 #else
 495         /*
 496          * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
 497          * - sizeof (ulong) is usually a valid address. Better pick an address
 498          * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
 499          * "(ulong)-1" used to be a good choice for many systems...
 500          */
 501         addr = CFG_MONITOR_BASE - sizeof (ulong);
 502 #endif
 503         ((void (*)(void)) addr) ();
 504         return 1;
 505 }
 506
 507 #else   /* CONFIG_LWMON */
 508
 509 /*
 510  * On the LWMON board, the MCLR reset input of the PIC's on the board
 511  * uses a 47K/1n RC combination which has a 47us time  constant.  The
 512  * low  signal on the HRESET pin of the CPU is only 512 clocks = 8 us
 513  * and thus too short to reset the external hardware. So we  use  the
 514  * watchdog to reset the board.
 515  */
 516 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 517 {
 518         /* prevent triggering the watchdog */
 519         disable_interrupts ();
 520
 521         /* make sure the watchdog is running */
 522         reset_8xx_watchdog ((immap_t *) CFG_IMMR);
 523
 524         /* wait for watchdog reset */
 525         while (1) {};
 526
 527         /* NOTREACHED */
 528         return 1;
 529 }
 530
 531 #endif  /* CONFIG_LWMON */
 532
 533 /* ------------------------------------------------------------------------- */
 534
 535 /*
 536  * Get timebase clock frequency (like cpu_clk in Hz)
 537  *
 538  * See sections 14.2 and 14.6 of the User's Manual
 539  */
 540 unsigned long get_tbclk (void)
 541 {
 542         DECLARE_GLOBAL_DATA_PTR;
 543
 544         uint immr = get_immr (0);       /* Return full IMMR contents */
 545         volatile immap_t *immap = (volatile immap_t *)(immr & 0xFFFF0000);
 546         ulong oscclk, factor, pll;
 547
 548         if (immap->im_clkrst.car_sccr & SCCR_TBS) {
 549                 return (gd->cpu_clk / 16);
 550         }
 551
 552         pll = immap->im_clkrst.car_plprcr;
 553
 554 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
 555
 556         /*
 557          * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
 558          * factor is calculated as follows:
 559          *
 560          *                   MFN
 561          *           MFI + -------
 562          *                 MFD + 1
 563          * factor =  -----------------
 564          *           (PDF + 1) * 2^S
 565          *
 566          * For older chips, it's just MF field of PLPRCR plus one.
 567          */
 568         if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
 569                 factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
 570                         (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
 571         } else {
 572                 factor = PLPRCR_val(MF)+1;
 573         }
 574
 575         oscclk = gd->cpu_clk / factor;
 576
 577         if ((immap->im_clkrst.car_sccr & SCCR_RTSEL) == 0 || factor > 2) {
 578                 return (oscclk / 4);
 579         }
 580         return (oscclk / 16);
 581 }
 582
 583 /* ------------------------------------------------------------------------- */
 584
 585 #if defined(CONFIG_WATCHDOG)
 586 void watchdog_reset (void)
 587 {
 588         int re_enable = disable_interrupts ();
 589
 590         reset_8xx_watchdog ((immap_t *) CFG_IMMR);
 591         if (re_enable)
 592                 enable_interrupts ();
 593 }
 594 #endif /* CONFIG_WATCHDOG */
 595
 596 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_LWMON)
 597
 598 void reset_8xx_watchdog (volatile immap_t * immr)
 599 {
 600 # if defined(CONFIG_LWMON)
 601         /*
 602          * The LWMON board uses a MAX6301 Watchdog
 603          * with the trigger pin connected to port PA.7
 604          *
 605          * (The old board version used a MAX706TESA Watchdog, which
 606          * had to be handled exactly the same.)
 607          */
 608 # define WATCHDOG_BIT   0x0100
 609         immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT);   /* GPIO     */
 610         immr->im_ioport.iop_padir |= WATCHDOG_BIT;      /* Output   */
 611         immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT);   /* active output */
 612
 613         immr->im_ioport.iop_padat ^= WATCHDOG_BIT;      /* Toggle WDI   */
 614 # elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
 615         /*
 616          * The KUP4 boards uses a TPS3705 Watchdog
 617          * with the trigger pin connected to port PA.5
 618          */
 619 # define WATCHDOG_BIT   0x0400
 620         immr->im_ioport.iop_papar &= ~(WATCHDOG_BIT);   /* GPIO     */
 621         immr->im_ioport.iop_padir |= WATCHDOG_BIT;      /* Output   */
 622         immr->im_ioport.iop_paodr &= ~(WATCHDOG_BIT);   /* active output */
 623
 624         immr->im_ioport.iop_padat ^= WATCHDOG_BIT;      /* Toggle WDI   */
 625 # else
 626         /*
 627          * All other boards use the MPC8xx Internal Watchdog
 628          */
 629         immr->im_siu_conf.sc_swsr = 0x556c;     /* write magic1 */
 630         immr->im_siu_conf.sc_swsr = 0xaa39;     /* write magic2 */
 631 # endif /* CONFIG_LWMON */
 632 }
 633
 634 #endif /* CONFIG_WATCHDOG */
 635
 636 /* ------------------------------------------------------------------------- */