cpu/mpc8xx/fec.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <malloc.h>
  26 #include <commproc.h>
  27 #include <net.h>
  28 #include <command.h>
  29
  30 #undef  ET_DEBUG
  31
  32 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
  33
  34 #ifdef CFG_DISCOVER_PHY
  35 #include <miiphy.h>
  36 static void mii_discover_phy(void);
  37 #endif
  38
  39 /* Ethernet Transmit and Receive Buffers */
  40 #define DBUF_LENGTH  1520
  41
  42 #define TX_BUF_CNT 2
  43
  44 #define TOUT_LOOP 100
  45
  46 #define PKT_MAXBUF_SIZE         1518
  47 #define PKT_MINBUF_SIZE         64
  48 #define PKT_MAXBLR_SIZE         1520
  49
  50
  51 static char txbuf[DBUF_LENGTH];
  52
  53 static uint rxIdx;      /* index of the current RX buffer */
  54 static uint txIdx;      /* index of the current TX buffer */
  55
  56 /*
  57   * FEC Ethernet Tx and Rx buffer descriptors allocated at the
  58   *  immr->udata_bd address on Dual-Port RAM
  59   * Provide for Double Buffering
  60   */
  61
  62 typedef volatile struct CommonBufferDescriptor {
  63     cbd_t rxbd[PKTBUFSRX];              /* Rx BD */
  64     cbd_t txbd[TX_BUF_CNT];             /* Tx BD */
  65 } RTXBD;
  66
  67 static RTXBD *rtx = NULL;
  68
  69 static int fec_send(struct eth_device* dev, volatile void *packet, int length);
  70 static int fec_recv(struct eth_device* dev);
  71 static int fec_init(struct eth_device* dev, bd_t * bd);
  72 static void fec_halt(struct eth_device* dev);
  73
  74 int fec_initialize(bd_t *bis)
  75 {
  76         struct eth_device* dev;
  77
  78         dev = (struct eth_device*) malloc(sizeof *dev);
  79         memset(dev, 0, sizeof *dev);
  80
  81         sprintf(dev->name, "FEC ETHERNET");
  82         dev->iobase = 0;
  83         dev->priv   = 0;
  84         dev->init   = fec_init;
  85         dev->halt   = fec_halt;
  86         dev->send   = fec_send;
  87         dev->recv   = fec_recv;
  88
  89         eth_register(dev);
  90
  91         return 1;
  92 }
  93
  94 static int fec_send(struct eth_device* dev, volatile void *packet, int length)
  95 {
  96         int j, rc;
  97         volatile immap_t *immr = (immap_t *) CFG_IMMR;
  98         volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
  99
 100         /* section 16.9.23.3
 101          * Wait for ready
 102          */
 103         j = 0;
 104         while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
 105                 udelay(1);
 106                 j++;
 107         }
 108         if (j>=TOUT_LOOP) {
 109                 printf("TX not ready\n");
 110         }
 111
 112         rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
 113         rtx->txbd[txIdx].cbd_datlen  = length;
 114         rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
 115         __asm__ ("eieio");
 116
 117         /* Activate transmit Buffer Descriptor polling */
 118         fecp->fec_x_des_active = 0x01000000;    /* Descriptor polling active    */
 119
 120         j = 0;
 121         while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
 122 #if defined(CONFIG_ICU862)
 123                 udelay(10);
 124 #else
 125                 udelay(1);
 126 #endif
 127                 j++;
 128         }
 129         if (j>=TOUT_LOOP) {
 130                 printf("TX timeout\n");
 131         }
 132 #ifdef ET_DEBUG
 133         printf("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
 134         __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
 135         (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
 136 #endif
 137         /* return only status bits */;
 138         rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
 139
 140         txIdx = (txIdx + 1) % TX_BUF_CNT;
 141
 142         return rc;
 143 }
 144
 145 static int fec_recv(struct eth_device* dev)
 146 {
 147         int length;
 148         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 149         volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
 150
 151    for (;;) {
 152         /* section 16.9.23.2 */
 153         if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
 154                 length = -1;
 155                 break;     /* nothing received - leave for() loop */
 156         }
 157
 158         length = rtx->rxbd[rxIdx].cbd_datlen;
 159
 160         if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
 161 #ifdef ET_DEBUG
 162                 printf("%s[%d] err: %x\n",
 163                 __FUNCTION__,__LINE__,rtx->rxbd[rxIdx].cbd_sc);
 164 #endif
 165         } else {
 166                 /* Pass the packet up to the protocol layers. */
 167                 NetReceive(NetRxPackets[rxIdx], length - 4);
 168         }
 169
 170         /* Give the buffer back to the FEC. */
 171         rtx->rxbd[rxIdx].cbd_datlen = 0;
 172
 173         /* wrap around buffer index when necessary */
 174         if ((rxIdx + 1) >= PKTBUFSRX) {
 175                 rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
 176                 rxIdx = 0;
 177         } else {
 178                 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
 179                 rxIdx++;
 180         }
 181
 182         __asm__ ("eieio");
 183
 184         /* Try to fill Buffer Descriptors */
 185         fecp->fec_r_des_active = 0x01000000;    /* Descriptor polling active    */
 186    }
 187
 188    return length;
 189 }
 190
 191 /**************************************************************
 192  *
 193  * FEC Ethernet Initialization Routine
 194  *
 195  *************************************************************/
 196
 197 #define FEC_ECNTRL_PINMUX       0x00000004
 198 #define FEC_ECNTRL_ETHER_EN     0x00000002
 199 #define FEC_ECNTRL_RESET        0x00000001
 200
 201 #define FEC_RCNTRL_BC_REJ       0x00000010
 202 #define FEC_RCNTRL_PROM         0x00000008
 203 #define FEC_RCNTRL_MII_MODE     0x00000004
 204 #define FEC_RCNTRL_DRT          0x00000002
 205 #define FEC_RCNTRL_LOOP         0x00000001
 206
 207 #define FEC_TCNTRL_FDEN         0x00000004
 208 #define FEC_TCNTRL_HBC          0x00000002
 209 #define FEC_TCNTRL_GTS          0x00000001
 210
 211 #define FEC_RESET_DELAY         50
 212
 213 static int fec_init(struct eth_device* dev, bd_t * bd)
 214 {
 215
 216         int i;
 217         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 218         volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
 219
 220 #if defined(CONFIG_FADS) && defined(CONFIG_MPC860T)
 221         /* configure FADS for fast (FEC) ethernet, half-duplex */
 222         /* The LXT970 needs about 50ms to recover from reset, so
 223          * wait for it by discovering the PHY before leaving eth_init().
 224          */
 225         {
 226                 volatile uint *bcsr4 = (volatile uint *) BCSR4;
 227                 *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
 228                         | (BCSR4_FETHCFG0 | BCSR4_FETHFDE | BCSR4_FETHRST);
 229
 230                 /* reset the LXT970 PHY */
 231                 *bcsr4 &= ~BCSR4_FETHRST;
 232                 udelay (10);
 233                 *bcsr4 |= BCSR4_FETHRST;
 234                 udelay (10);
 235         }
 236 #endif
 237         /* Whack a reset.
 238          * A delay is required between a reset of the FEC block and
 239          * initialization of other FEC registers because the reset takes
 240          * some time to complete. If you don't delay, subsequent writes
 241          * to FEC registers might get killed by the reset routine which is
 242          * still in progress.
 243          */
 244         fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
 245         for (i = 0;
 246              (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
 247              ++i) {
 248                 udelay (1);
 249         }
 250         if (i == FEC_RESET_DELAY) {
 251                 printf ("FEC_RESET_DELAY timeout\n");
 252                 return 0;
 253         }
 254
 255         /* We use strictly polling mode only
 256          */
 257         fecp->fec_imask = 0;
 258
 259         /* Clear any pending interrupt
 260          */
 261         fecp->fec_ievent = 0xffc0;
 262
 263         /* No need to set the IVEC register */
 264
 265         /* Set station address
 266          */
 267 #define ea eth_get_dev()->enetaddr
 268         fecp->fec_addr_low   =  (ea[0] << 24) | (ea[1] << 16) |
 269                                 (ea[2] <<  8) | (ea[3]      ) ;
 270         fecp->fec_addr_high  =  (ea[4] <<  8) | (ea[5]      ) ;
 271 #undef ea
 272
 273         /* Clear multicast address hash table
 274          */
 275         fecp->fec_hash_table_high = 0;
 276         fecp->fec_hash_table_low  = 0;
 277
 278         /* Set maximum receive buffer size.
 279          */
 280         fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
 281
 282         /* Set maximum frame length
 283          */
 284         fecp->fec_r_hash = PKT_MAXBUF_SIZE;
 285
 286         /*
 287          * Setup Buffers and Buffer Desriptors
 288          */
 289         rxIdx = 0;
 290         txIdx = 0;
 291
 292         if (!rtx) {
 293 #ifdef CFG_ALLOC_DPRAM
 294             rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + dpram_alloc_align(sizeof(RTXBD),8));
 295 #else
 296             rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
 297 #endif
 298         }
 299         /*
 300          * Setup Receiver Buffer Descriptors (13.14.24.18)
 301          * Settings:
 302          *     Empty, Wrap
 303          */
 304         for (i = 0; i < PKTBUFSRX; i++) {
 305                 rtx->rxbd[i].cbd_sc      = BD_ENET_RX_EMPTY;
 306                 rtx->rxbd[i].cbd_datlen  = 0;   /* Reset */
 307                 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
 308         }
 309         rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
 310
 311         /*
 312          * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
 313          * Settings:
 314          *    Last, Tx CRC
 315          */
 316         for (i = 0; i < TX_BUF_CNT; i++) {
 317                 rtx->txbd[i].cbd_sc      = BD_ENET_TX_LAST | BD_ENET_TX_TC;
 318                 rtx->txbd[i].cbd_datlen  = 0;   /* Reset */
 319                 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
 320         }
 321         rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
 322
 323         /* Set receive and transmit descriptor base
 324          */
 325         fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
 326         fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
 327
 328         /* Enable MII mode
 329          */
 330 #if 0   /* Full duplex mode */
 331         fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
 332         fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
 333 #else   /* Half duplex mode */
 334         fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
 335         fecp->fec_x_cntrl = 0;
 336 #endif
 337
 338         /* Enable big endian and don't care about SDMA FC.
 339          */
 340         fecp->fec_fun_code = 0x78000000;
 341
 342         /* Set MII speed to 2.5 MHz or slightly below.
 343          * According to the MPC860T (Rev. D) Fast ethernet controller user
 344          * manual (6.2.14),
 345          * the MII management interface clock must be less than or equal
 346          * to 2.5 MHz.
 347          * This MDC frequency is equal to system clock / (2 * MII_SPEED).
 348          * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
 349          */
 350         fecp->fec_mii_speed = ((bd->bi_busfreq + 4999999) / 5000000) << 1;
 351
 352 #if !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
 353         /* Configure all of port D for MII.
 354          */
 355         immr->im_ioport.iop_pdpar = 0x1fff;
 356
 357         /* Bits moved from Rev. D onward */
 358         if ((get_immr (0) & 0xffff) < 0x0501) {
 359                 immr->im_ioport.iop_pddir = 0x1c58;     /* Pre rev. D */
 360         } else {
 361                 immr->im_ioport.iop_pddir = 0x1fff;     /* Rev. D and later */
 362         }
 363 #else
 364         /* Configure port A for MII.
 365         */
 366
 367 #if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY)
 368
 369         /* On the ICU862 board the MII-MDC pin is routed to PD8 pin
 370          * of CPU, so for this board we need to configure Utopia and
 371          * enable PD8 to MII-MDC function */
 372         immr->im_ioport.iop_pdpar |= 0x4080;
 373 #endif
 374
 375         /* Has Utopia been configured? */
 376         if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
 377                 /*
 378                  * YES - Use MUXED mode for UTOPIA bus.
 379                  * This frees Port A for use by MII (see 862UM table 41-6).
 380                  */
 381                 immr->im_ioport.utmode &= ~0x80;
 382         } else {
 383                 /*
 384                  * NO - set SPLIT mode for UTOPIA bus.
 385                  *
 386                  * This doesn't really effect UTOPIA (which isn't
 387                  * enabled anyway) but just tells the 862
 388                  * to use port A for MII (see 862UM table 41-6).
 389                  */
 390                 immr->im_ioport.utmode |= 0x80;
 391         }
 392 #endif  /* !defined(CONFIG_ICU862) */
 393
 394         rxIdx = 0;
 395         txIdx = 0;
 396
 397         /* Now enable the transmit and receive processing
 398          */
 399         fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
 400
 401 #ifdef CFG_DISCOVER_PHY
 402         /* wait for the PHY to wake up after reset
 403          */
 404         mii_discover_phy();
 405 #endif
 406
 407         /* And last, try to fill Rx Buffer Descriptors */
 408         fecp->fec_r_des_active = 0x01000000;    /* Descriptor polling active    */
 409
 410         return 1;
 411 }
 412
 413
 414 static void fec_halt(struct eth_device* dev)
 415 {
 416 #if 0
 417     volatile immap_t *immr = (immap_t *)CFG_IMMR;
 418     immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 419 #endif
 420 }
 421
 422 #if 0
 423 void restart(void)
 424 {
 425    volatile immap_t *immr = (immap_t *)CFG_IMMR;
 426    immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 427 }
 428 #endif
 429
 430 #if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
 431
 432 static  int     phyaddr = -1;   /* didn't find a PHY yet */
 433 static  uint    phytype;
 434
 435 /* Make MII read/write commands for the FEC.
 436 */
 437
 438 #define mk_mii_read(ADDR, REG)  (0x60020000 | ((ADDR << 23) | \
 439                                                 (REG & 0x1f) << 18))
 440
 441 #define mk_mii_write(ADDR, REG, VAL)    (0x50020000 | ((ADDR << 23) | \
 442                                                 (REG & 0x1f) << 18) | \
 443                                                 (VAL & 0xffff))
 444
 445 /* Interrupt events/masks.
 446 */
 447 #define FEC_ENET_HBERR  ((uint)0x80000000)      /* Heartbeat error */
 448 #define FEC_ENET_BABR   ((uint)0x40000000)      /* Babbling receiver */
 449 #define FEC_ENET_BABT   ((uint)0x20000000)      /* Babbling transmitter */
 450 #define FEC_ENET_GRA    ((uint)0x10000000)      /* Graceful stop complete */
 451 #define FEC_ENET_TXF    ((uint)0x08000000)      /* Full frame transmitted */
 452 #define FEC_ENET_TXB    ((uint)0x04000000)      /* A buffer was transmitted */
 453 #define FEC_ENET_RXF    ((uint)0x02000000)      /* Full frame received */
 454 #define FEC_ENET_RXB    ((uint)0x01000000)      /* A buffer was received */
 455 #define FEC_ENET_MII    ((uint)0x00800000)      /* MII interrupt */
 456 #define FEC_ENET_EBERR  ((uint)0x00400000)      /* SDMA bus error */
 457
 458 /* PHY identification
 459  */
 460 #define PHY_ID_LXT970           0x78100000      /* LXT970 */
 461 #define PHY_ID_LXT971           0x001378e0      /* LXT971 and 972 */
 462 #define PHY_ID_82555            0x02a80150      /* Intel 82555 */
 463 #define PHY_ID_QS6612           0x01814400      /* QS6612 */
 464 #define PHY_ID_AMD79C784        0x00225610      /* AMD 79C784 */
 465 #define PHY_ID_LSI80225         0x0016f870      /* LSI 80225 */
 466 #define PHY_ID_LSI80225B        0x0016f880      /* LSI 80225/B */
 467
 468
 469 /* send command to phy using mii, wait for result */
 470 static uint
 471 mii_send(uint mii_cmd)
 472 {
 473         uint mii_reply;
 474         volatile fec_t  *ep;
 475
 476         ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec);
 477
 478         ep->fec_mii_data = mii_cmd;     /* command to phy */
 479
 480         /* wait for mii complete */
 481         while (!(ep->fec_ievent & FEC_ENET_MII))
 482                 ;       /* spin until done */
 483         mii_reply = ep->fec_mii_data;           /* result from phy */
 484         ep->fec_ievent = FEC_ENET_MII;          /* clear MII complete */
 485 #if 0
 486         printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
 487                 __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
 488 #endif
 489         return (mii_reply & 0xffff);            /* data read from phy */
 490 }
 491 #endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
 492
 493 #if defined(CFG_DISCOVER_PHY)
 494 static void
 495 mii_discover_phy(void)
 496 {
 497 #define MAX_PHY_PASSES 11
 498         uint phyno;
 499         int  pass;
 500
 501         phyaddr = -1;   /* didn't find a PHY yet */
 502         for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
 503                 if (pass > 1) {
 504                         /* PHY may need more time to recover from reset.
 505                          * The LXT970 needs 50ms typical, no maximum is
 506                          * specified, so wait 10ms before try again.
 507                          * With 11 passes this gives it 100ms to wake up.
 508                          */
 509                         udelay(10000);  /* wait 10ms */
 510                 }
 511                 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
 512                         phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
 513 #ifdef ET_DEBUG
 514                         printf("PHY type 0x%x pass %d type ", phytype, pass);
 515 #endif
 516                         if (phytype != 0xffff) {
 517                                 phyaddr = phyno;
 518                                 phytype <<= 16;
 519                                 phytype |= mii_send(mk_mii_read(phyno,
 520                                                                 PHY_PHYIDR2));
 521
 522 #ifdef ET_DEBUG
 523                                 printf("PHY @ 0x%x pass %d type ",phyno,pass);
 524                                 switch (phytype & 0xfffffff0) {
 525                                 case PHY_ID_LXT970:
 526                                         printf("LXT970\n");
 527                                         break;
 528                                 case PHY_ID_LXT971:
 529                                         printf("LXT971\n");
 530                                         break;
 531                                 case PHY_ID_82555:
 532                                         printf("82555\n");
 533                                         break;
 534                                 case PHY_ID_QS6612:
 535                                         printf("QS6612\n");
 536                                         break;
 537                                 case PHY_ID_AMD79C784:
 538                                         printf("AMD79C784\n");
 539                                         break;
 540                                 case PHY_ID_LSI80225B:
 541                                         printf("LSI L80225/B\n");
 542                                         break;
 543                                 default:
 544                                         printf("0x%08x\n", phytype);
 545                                         break;
 546                                 }
 547 #endif
 548                         }
 549                 }
 550         }
 551         if (phyaddr < 0) {
 552                 printf("No PHY device found.\n");
 553         }
 554 }
 555 #endif  /* CFG_DISCOVER_PHY */
 556
 557 #if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
 558
 559 static int mii_init_done = 0;
 560
 561 /****************************************************************************
 562  * mii_init -- Initialize the MII for MII command without ethernet
 563  * This function is a subset of eth_init
 564  ****************************************************************************
 565  */
 566 void mii_init (void)
 567 {
 568         DECLARE_GLOBAL_DATA_PTR;
 569         bd_t *bd = gd->bd;
 570
 571         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 572         volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
 573         int i;
 574
 575         if (mii_init_done != 0) {
 576                 return;
 577         }
 578
 579         /* Whack a reset.
 580          * A delay is required between a reset of the FEC block and
 581          * initialization of other FEC registers because the reset takes
 582          * some time to complete. If you don't delay, subsequent writes
 583          * to FEC registers might get killed by the reset routine which is
 584          * still in progress.
 585          */
 586
 587         fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
 588         for (i = 0;
 589              (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
 590              ++i) {
 591                 udelay (1);
 592         }
 593         if (i == FEC_RESET_DELAY) {
 594                 printf ("FEC_RESET_DELAY timeout\n");
 595                 return;
 596         }
 597
 598         /* We use strictly polling mode only
 599          */
 600         fecp->fec_imask = 0;
 601
 602         /* Clear any pending interrupt
 603          */
 604         fecp->fec_ievent = 0xffc0;
 605
 606         /* Set MII speed to 2.5 MHz or slightly below.
 607          * According to the MPC860T (Rev. D) Fast ethernet controller user
 608          * manual (6.2.14),
 609          * the MII management interface clock must be less than or equal
 610          * to 2.5 MHz.
 611          * This MDC frequency is equal to system clock / (2 * MII_SPEED).
 612          * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
 613          */
 614         fecp->fec_mii_speed = ((bd->bi_busfreq + 4999999) / 5000000) << 1;
 615
 616 #if !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
 617         /* Configure all of port D for MII.
 618          */
 619         immr->im_ioport.iop_pdpar = 0x1fff;
 620
 621         /* Bits moved from Rev. D onward */
 622         if ((get_immr (0) & 0xffff) < 0x0501) {
 623                 immr->im_ioport.iop_pddir = 0x1c58;     /* Pre rev. D */
 624         } else {
 625                 immr->im_ioport.iop_pddir = 0x1fff;     /* Rev. D and later */
 626         }
 627 #else
 628         /* Configure port A for MII.
 629         */
 630
 631 #if defined(CONFIG_ICU862)
 632
 633         /* On the ICU862 board the MII-MDC pin is routed to PD8 pin
 634          * of CPU, so for this board we need to configure Utopia and
 635          * enable PD8 to MII-MDC function */
 636         immr->im_ioport.iop_pdpar |= 0x4080;
 637 #endif
 638
 639         /* Has Utopia been configured? */
 640         if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
 641                 /*
 642                  * YES - Use MUXED mode for UTOPIA bus.
 643                  * This frees Port A for use by MII (see 862UM table 41-6).
 644                  */
 645                 immr->im_ioport.utmode &= ~0x80;
 646         } else {
 647                 /*
 648                  * NO - set SPLIT mode for UTOPIA bus.
 649                  *
 650                  * This doesn't really effect UTOPIA (which isn't
 651                  * enabled anyway) but just tells the 862
 652                  * to use port A for MII (see 862UM table 41-6).
 653                  */
 654                 immr->im_ioport.utmode |= 0x80;
 655         }
 656 #endif  /* !defined(CONFIG_ICU862) */
 657         /* Now enable the transmit and receive processing
 658          */
 659         fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
 660
 661         mii_init_done = 1;
 662 }
 663 /*****************************************************************************
 664  * Read and write a MII PHY register, routines used by MII Utilities
 665  *
 666  * FIXME: These routines are expected to return 0 on success, but mii_send
 667  *        does _not_ return an error code. Maybe 0xFFFF means error, i.e.
 668  *        no PHY connected...
 669  *        For now always return 0.
 670  * FIXME: These routines only work after calling eth_init() at least once!
 671  *        Otherwise they hang in mii_send() !!! Sorry!
 672  *****************************************************************************/
 673
 674 int miiphy_read(unsigned char addr, unsigned char  reg, unsigned short *value)
 675 {
 676         short rdreg;    /* register working value */
 677
 678 #ifdef MII_DEBUG
 679         printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
 680 #endif
 681         rdreg = mii_send(mk_mii_read(addr, reg));
 682
 683         *value = rdreg;
 684
 685 #ifdef MII_DEBUG
 686         printf ("0x%04x\n", *value);
 687 #endif
 688
 689         return 0;
 690 }
 691
 692 int miiphy_write(unsigned char  addr, unsigned char  reg, unsigned short value)
 693 {
 694         short rdreg;    /* register working value */
 695
 696 #ifdef MII_DEBUG
 697         printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
 698 #endif
 699
 700         rdreg = mii_send(mk_mii_write(addr, reg, value));
 701
 702 #ifdef MII_DEBUG
 703         printf ("0x%04x\n", value);
 704 #endif
 705
 706         return 0;
 707 }
 708 #endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/
 709
 710 #endif  /* CFG_CMD_NET, FEC_ENET */