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1 /*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <malloc.h>
26 #include <commproc.h>
27 #include <net.h>
28 #include <command.h>
29
30 #undef ET_DEBUG
31
32 #if (CONFIG_COMMANDS & CFG_CMD_NET) && \
33 (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
34
35 /* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
36 #if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
37 #define CONFIG_ETHER_ON_FEC1 1
38 #endif
39
40 /* define WANT_MII when MII support is required */
41 #if defined(CFG_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
42 #define WANT_MII
43 #else
44 #undef WANT_MII
45 #endif
46
47 #if defined(WANT_MII)
48 #include <miiphy.h>
49
50 #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
51 #error "CONFIG_MII has to be defined!"
52 #endif
53
54 #endif
55
56 #if defined(CONFIG_RMII) && !defined(WANT_MII)
57 #error RMII support is unusable without a working PHY.
58 #endif
59
60 #ifdef CFG_DISCOVER_PHY
61 static int mii_discover_phy(struct eth_device *dev);
62 #endif
63
64 int fec8xx_miiphy_read(char *devname, unsigned char addr,
65 unsigned char reg, unsigned short *value);
66 int fec8xx_miiphy_write(char *devname, unsigned char addr,
67 unsigned char reg, unsigned short value);
68
69 static struct ether_fcc_info_s
70 {
71 int ether_index;
72 int fecp_offset;
73 int phy_addr;
74 int actual_phy_addr;
75 int initialized;
76 }
77 ether_fcc_info[] = {
78 #if defined(CONFIG_ETHER_ON_FEC1)
79 {
80 0,
81 offsetof(immap_t, im_cpm.cp_fec1),
82 #if defined(CONFIG_FEC1_PHY)
83 CONFIG_FEC1_PHY,
84 #else
85 -1, /* discover */
86 #endif
87 -1,
88 0,
89
90 },
91 #endif
92 #if defined(CONFIG_ETHER_ON_FEC2)
93 {
94 1,
95 offsetof(immap_t, im_cpm.cp_fec2),
96 #if defined(CONFIG_FEC2_PHY)
97 CONFIG_FEC2_PHY,
98 #else
99 -1,
100 #endif
101 -1,
102 0,
103 },
104 #endif
105 };
106
107 /* Ethernet Transmit and Receive Buffers */
108 #define DBUF_LENGTH 1520
109
110 #define TX_BUF_CNT 2
111
112 #define TOUT_LOOP 100
113
114 #define PKT_MAXBUF_SIZE 1518
115 #define PKT_MINBUF_SIZE 64
116 #define PKT_MAXBLR_SIZE 1520
117
118 #ifdef __GNUC__
119 static char txbuf[DBUF_LENGTH] __attribute__ ((aligned(8)));
120 #else
121 #error txbuf must be aligned.
122 #endif
123
124 static uint rxIdx; /* index of the current RX buffer */
125 static uint txIdx; /* index of the current TX buffer */
126
127 /*
128 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
129 * immr->udata_bd address on Dual-Port RAM
130 * Provide for Double Buffering
131 */
132
133 typedef volatile struct CommonBufferDescriptor {
134 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
135 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
136 } RTXBD;
137
138 static RTXBD *rtx = NULL;
139
140 static int fec_send(struct eth_device* dev, volatile void *packet, int length);
141 static int fec_recv(struct eth_device* dev);
142 static int fec_init(struct eth_device* dev, bd_t * bd);
143 static void fec_halt(struct eth_device* dev);
144
145 int fec_initialize(bd_t *bis)
146 {
147 struct eth_device* dev;
148 struct ether_fcc_info_s *efis;
149 int i;
150
151 for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
152
153 dev = malloc(sizeof(*dev));
154 if (dev == NULL)
155 hang();
156
157 memset(dev, 0, sizeof(*dev));
158
159 /* for FEC1 make sure that the name of the interface is the same
160 as the old one for compatibility reasons */
161 if (i == 0) {
162 sprintf (dev->name, "FEC ETHERNET");
163 } else {
164 sprintf (dev->name, "FEC%d ETHERNET",
165 ether_fcc_info[i].ether_index + 1);
166 }
167
168 efis = &ether_fcc_info[i];
169
170 /*
171 * reset actual phy addr
172 */
173 efis->actual_phy_addr = -1;
174
175 dev->priv = efis;
176 dev->init = fec_init;
177 dev->halt = fec_halt;
178 dev->send = fec_send;
179 dev->recv = fec_recv;
180
181 eth_register(dev);
182
183 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
184 miiphy_register(dev->name,
185 fec8xx_miiphy_read, fec8xx_miiphy_write);
186 #endif
187 }
188 return 1;
189 }
190
191 static int fec_send(struct eth_device* dev, volatile void *packet, int length)
192 {
193 int j, rc;
194 struct ether_fcc_info_s *efis = dev->priv;
195 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
196
197 /* section 16.9.23.3
198 * Wait for ready
199 */
200 j = 0;
201 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
202 udelay(1);
203 j++;
204 }
205 if (j>=TOUT_LOOP) {
206 printf("TX not ready\n");
207 }
208
209 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
210 rtx->txbd[txIdx].cbd_datlen = length;
211 rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
212 __asm__ ("eieio");
213
214 /* Activate transmit Buffer Descriptor polling */
215 fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
216
217 j = 0;
218 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
219 #if defined(CONFIG_ICU862)
220 udelay(10);
221 #else
222 udelay(1);
223 #endif
224 j++;
225 }
226 if (j>=TOUT_LOOP) {
227 printf("TX timeout\n");
228 }
229 #ifdef ET_DEBUG
230 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
231 __FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
232 (rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
233 #endif
234 /* return only status bits */;
235 rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
236
237 txIdx = (txIdx + 1) % TX_BUF_CNT;
238
239 return rc;
240 }
241
242 static int fec_recv (struct eth_device *dev)
243 {
244 struct ether_fcc_info_s *efis = dev->priv;
245 volatile fec_t *fecp =
246 (volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
247 int length;
248
249 for (;;) {
250 /* section 16.9.23.2 */
251 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
252 length = -1;
253 break; /* nothing received - leave for() loop */
254 }
255
256 length = rtx->rxbd[rxIdx].cbd_datlen;
257
258 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
259 #ifdef ET_DEBUG
260 printf ("%s[%d] err: %x\n",
261 __FUNCTION__, __LINE__,
262 rtx->rxbd[rxIdx].cbd_sc);
263 #endif
264 } else {
265 volatile uchar *rx = NetRxPackets[rxIdx];
266
267 length -= 4;
268
269 #if (CONFIG_COMMANDS & CFG_CMD_CDP)
270 if ((rx[0] & 1) != 0
271 && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0
272 && memcmp ((uchar *) rx, NetCDPAddr, 6) != 0)
273 rx = NULL;
274 #endif
275 /*
276 * Pass the packet up to the protocol layers.
277 */
278 if (rx != NULL)
279 NetReceive (rx, length);
280 }
281
282 /* Give the buffer back to the FEC. */
283 rtx->rxbd[rxIdx].cbd_datlen = 0;
284
285 /* wrap around buffer index when necessary */
286 if ((rxIdx + 1) >= PKTBUFSRX) {
287 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
288 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
289 rxIdx = 0;
290 } else {
291 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
292 rxIdx++;
293 }
294
295 __asm__ ("eieio");
296
297 /* Try to fill Buffer Descriptors */
298 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
299 }
300
301 return length;
302 }
303
304 /**************************************************************
305 *
306 * FEC Ethernet Initialization Routine
307 *
308 *************************************************************/
309
310 #define FEC_ECNTRL_PINMUX 0x00000004
311 #define FEC_ECNTRL_ETHER_EN 0x00000002
312 #define FEC_ECNTRL_RESET 0x00000001
313
314 #define FEC_RCNTRL_BC_REJ 0x00000010
315 #define FEC_RCNTRL_PROM 0x00000008
316 #define FEC_RCNTRL_MII_MODE 0x00000004
317 #define FEC_RCNTRL_DRT 0x00000002
318 #define FEC_RCNTRL_LOOP 0x00000001
319
320 #define FEC_TCNTRL_FDEN 0x00000004
321 #define FEC_TCNTRL_HBC 0x00000002
322 #define FEC_TCNTRL_GTS 0x00000001
323
324 #define FEC_RESET_DELAY 50
325
326 #if defined(CONFIG_RMII)
327
328 static inline void fec_10Mbps(struct eth_device *dev)
329 {
330 struct ether_fcc_info_s *efis = dev->priv;
331 int fecidx = efis->ether_index;
332 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
333
334 if ((unsigned int)fecidx >= 2)
335 hang();
336
337 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr |= mask;
338 }
339
340 static inline void fec_100Mbps(struct eth_device *dev)
341 {
342 struct ether_fcc_info_s *efis = dev->priv;
343 int fecidx = efis->ether_index;
344 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008;
345
346 if ((unsigned int)fecidx >= 2)
347 hang();
348
349 ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_cptr &= ~mask;
350 }
351
352 #endif
353
354 static inline void fec_full_duplex(struct eth_device *dev)
355 {
356 struct ether_fcc_info_s *efis = dev->priv;
357 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
358
359 fecp->fec_r_cntrl &= ~FEC_RCNTRL_DRT;
360 fecp->fec_x_cntrl |= FEC_TCNTRL_FDEN; /* FD enable */
361 }
362
363 static inline void fec_half_duplex(struct eth_device *dev)
364 {
365 struct ether_fcc_info_s *efis = dev->priv;
366 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
367
368 fecp->fec_r_cntrl |= FEC_RCNTRL_DRT;
369 fecp->fec_x_cntrl &= ~FEC_TCNTRL_FDEN; /* FD disable */
370 }
371
372 static void fec_pin_init(int fecidx)
373 {
374 DECLARE_GLOBAL_DATA_PTR;
375 bd_t *bd = gd->bd;
376 volatile immap_t *immr = (immap_t *) CFG_IMMR;
377 volatile fec_t *fecp;
378
379 /*
380 * only two FECs please
381 */
382 if ((unsigned int)fecidx >= 2)
383 hang();
384
385 if (fecidx == 0)
386 fecp = &immr->im_cpm.cp_fec1;
387 else
388 fecp = &immr->im_cpm.cp_fec2;
389
390 /*
391 * Set MII speed to 2.5 MHz or slightly below.
392 * * According to the MPC860T (Rev. D) Fast ethernet controller user
393 * * manual (6.2.14),
394 * * the MII management interface clock must be less than or equal
395 * * to 2.5 MHz.
396 * * This MDC frequency is equal to system clock / (2 * MII_SPEED).
397 * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
398 */
399 fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
400
401 #if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
402 /* our PHYs are the limit at 2.5 MHz */
403 fecp->fec_mii_speed <<= 1;
404 #endif
405
406 #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
407 /* use MDC for MII */
408 immr->im_ioport.iop_pdpar |= 0x0080;
409 immr->im_ioport.iop_pddir &= ~0x0080;
410 #endif
411
412 if (fecidx == 0) {
413 #if defined(CONFIG_ETHER_ON_FEC1)
414
415 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
416
417 #if !defined(CONFIG_RMII)
418
419 immr->im_ioport.iop_papar |= 0xf830;
420 immr->im_ioport.iop_padir |= 0x0830;
421 immr->im_ioport.iop_padir &= ~0xf000;
422
423 immr->im_cpm.cp_pbpar |= 0x00001001;
424 immr->im_cpm.cp_pbdir &= ~0x00001001;
425
426 immr->im_ioport.iop_pcpar |= 0x000c;
427 immr->im_ioport.iop_pcdir &= ~0x000c;
428
429 immr->im_cpm.cp_pepar |= 0x00000003;
430 immr->im_cpm.cp_pedir |= 0x00000003;
431 immr->im_cpm.cp_peso &= ~0x00000003;
432
433 immr->im_cpm.cp_cptr &= ~0x00000100;
434
435 #else
436
437 #if !defined(CONFIG_FEC1_PHY_NORXERR)
438 immr->im_ioport.iop_papar |= 0x1000;
439 immr->im_ioport.iop_padir &= ~0x1000;
440 #endif
441 immr->im_ioport.iop_papar |= 0xe810;
442 immr->im_ioport.iop_padir |= 0x0810;
443 immr->im_ioport.iop_padir &= ~0xe000;
444
445 immr->im_cpm.cp_pbpar |= 0x00000001;
446 immr->im_cpm.cp_pbdir &= ~0x00000001;
447
448 immr->im_cpm.cp_cptr |= 0x00000100;
449 immr->im_cpm.cp_cptr &= ~0x00000050;
450
451 #endif /* !CONFIG_RMII */
452
453 #elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
454 /*
455 * Configure all of port D for MII.
456 */
457 immr->im_ioport.iop_pdpar = 0x1fff;
458
459 /*
460 * Bits moved from Rev. D onward
461 */
462 if ((get_immr(0) & 0xffff) < 0x0501)
463 immr->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
464 else
465 immr->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
466 #else
467 /*
468 * Configure port A for MII.
469 */
470
471 #if defined(CONFIG_ICU862) && defined(CFG_DISCOVER_PHY)
472
473 /*
474 * On the ICU862 board the MII-MDC pin is routed to PD8 pin
475 * * of CPU, so for this board we need to configure Utopia and
476 * * enable PD8 to MII-MDC function
477 */
478 immr->im_ioport.iop_pdpar |= 0x4080;
479 #endif
480
481 /*
482 * Has Utopia been configured?
483 */
484 if (immr->im_ioport.iop_pdpar & (0x8000 >> 1)) {
485 /*
486 * YES - Use MUXED mode for UTOPIA bus.
487 * This frees Port A for use by MII (see 862UM table 41-6).
488 */
489 immr->im_ioport.utmode &= ~0x80;
490 } else {
491 /*
492 * NO - set SPLIT mode for UTOPIA bus.
493 *
494 * This doesn't really effect UTOPIA (which isn't
495 * enabled anyway) but just tells the 862
496 * to use port A for MII (see 862UM table 41-6).
497 */
498 immr->im_ioport.utmode |= 0x80;
499 }
500 #endif /* !defined(CONFIG_ICU862) */
501
502 #endif /* CONFIG_ETHER_ON_FEC1 */
503 } else if (fecidx == 1) {
504
505 #if defined(CONFIG_ETHER_ON_FEC2)
506
507 #if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
508
509 #if !defined(CONFIG_RMII)
510
511 #warning this configuration is not tested; please report if it works
512 immr->im_cpm.cp_pepar |= 0x0003fffc;
513 immr->im_cpm.cp_pedir |= 0x0003fffc;
514 immr->im_cpm.cp_peso &= ~0x000087fc;
515 immr->im_cpm.cp_peso |= 0x00037800;
516
517 immr->im_cpm.cp_cptr &= ~0x00000080;
518 #else
519
520 #if !defined(CONFIG_FEC2_PHY_NORXERR)
521 immr->im_cpm.cp_pepar |= 0x00000010;
522 immr->im_cpm.cp_pedir |= 0x00000010;
523 immr->im_cpm.cp_peso &= ~0x00000010;
524 #endif
525 immr->im_cpm.cp_pepar |= 0x00039620;
526 immr->im_cpm.cp_pedir |= 0x00039620;
527 immr->im_cpm.cp_peso |= 0x00031000;
528 immr->im_cpm.cp_peso &= ~0x00008620;
529
530 immr->im_cpm.cp_cptr |= 0x00000080;
531 immr->im_cpm.cp_cptr &= ~0x00000028;
532 #endif /* CONFIG_RMII */
533
534 #endif /* CONFIG_MPC885_FAMILY */
535
536 #endif /* CONFIG_ETHER_ON_FEC2 */
537
538 }
539 }
540
541 static int fec_init (struct eth_device *dev, bd_t * bd)
542 {
543 struct ether_fcc_info_s *efis = dev->priv;
544 volatile immap_t *immr = (immap_t *) CFG_IMMR;
545 volatile fec_t *fecp =
546 (volatile fec_t *) (CFG_IMMR + efis->fecp_offset);
547 int i;
548
549 if (efis->ether_index == 0) {
550 #if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */
551 #if defined(CONFIG_MPC885ADS)
552 *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST);
553 #else
554 /* configure FADS for fast (FEC) ethernet, half-duplex */
555 /* The LXT970 needs about 50ms to recover from reset, so
556 * wait for it by discovering the PHY before leaving eth_init().
557 */
558 {
559 volatile uint *bcsr4 = (volatile uint *) BCSR4;
560
561 *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
562 | (BCSR4_FETHCFG0 | BCSR4_FETHFDE |
563 BCSR4_FETHRST);
564
565 /* reset the LXT970 PHY */
566 *bcsr4 &= ~BCSR4_FETHRST;
567 udelay (10);
568 *bcsr4 |= BCSR4_FETHRST;
569 udelay (10);
570 }
571 #endif /* CONFIG_MPC885ADS */
572 #endif /* CONFIG_FADS */
573 }
574
575 /* Whack a reset.
576 * A delay is required between a reset of the FEC block and
577 * initialization of other FEC registers because the reset takes
578 * some time to complete. If you don't delay, subsequent writes
579 * to FEC registers might get killed by the reset routine which is
580 * still in progress.
581 */
582 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
583 for (i = 0;
584 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
585 ++i) {
586 udelay (1);
587 }
588 if (i == FEC_RESET_DELAY) {
589 printf ("FEC_RESET_DELAY timeout\n");
590 return 0;
591 }
592
593 /* We use strictly polling mode only
594 */
595 fecp->fec_imask = 0;
596
597 /* Clear any pending interrupt
598 */
599 fecp->fec_ievent = 0xffc0;
600
601 /* No need to set the IVEC register */
602
603 /* Set station address
604 */
605 #define ea eth_get_dev()->enetaddr
606 fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
607 fecp->fec_addr_high = (ea[4] << 8) | (ea[5]);
608 #undef ea
609
610 #if (CONFIG_COMMANDS & CFG_CMD_CDP)
611 /*
612 * Turn on multicast address hash table
613 */
614 fecp->fec_hash_table_high = 0xffffffff;
615 fecp->fec_hash_table_low = 0xffffffff;
616 #else
617 /* Clear multicast address hash table
618 */
619 fecp->fec_hash_table_high = 0;
620 fecp->fec_hash_table_low = 0;
621 #endif
622
623 /* Set maximum receive buffer size.
624 */
625 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
626
627 /* Set maximum frame length
628 */
629 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
630
631 /*
632 * Setup Buffers and Buffer Desriptors
633 */
634 rxIdx = 0;
635 txIdx = 0;
636
637 if (!rtx) {
638 #ifdef CFG_ALLOC_DPRAM
639 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
640 dpram_alloc_align (sizeof (RTXBD), 8));
641 #else
642 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
643 #endif
644 }
645 /*
646 * Setup Receiver Buffer Descriptors (13.14.24.18)
647 * Settings:
648 * Empty, Wrap
649 */
650 for (i = 0; i < PKTBUFSRX; i++) {
651 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
652 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
653 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
654 }
655 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
656
657 /*
658 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
659 * Settings:
660 * Last, Tx CRC
661 */
662 for (i = 0; i < TX_BUF_CNT; i++) {
663 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
664 rtx->txbd[i].cbd_datlen = 0; /* Reset */
665 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
666 }
667 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
668
669 /* Set receive and transmit descriptor base
670 */
671 fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
672 fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
673
674 /* Enable MII mode
675 */
676 #if 0 /* Full duplex mode */
677 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
678 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
679 #else /* Half duplex mode */
680 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
681 fecp->fec_x_cntrl = 0;
682 #endif
683
684 /* Enable big endian and don't care about SDMA FC.
685 */
686 fecp->fec_fun_code = 0x78000000;
687
688 /*
689 * Setup the pin configuration of the FEC
690 */
691 fec_pin_init (efis->ether_index);
692
693 rxIdx = 0;
694 txIdx = 0;
695
696 /*
697 * Now enable the transmit and receive processing
698 */
699 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
700
701 if (efis->phy_addr == -1) {
702 #ifdef CFG_DISCOVER_PHY
703 /*
704 * wait for the PHY to wake up after reset
705 */
706 efis->actual_phy_addr = mii_discover_phy (dev);
707
708 if (efis->actual_phy_addr == -1) {
709 printf ("Unable to discover phy!\n");
710 return 0;
711 }
712 #else
713 efis->actual_phy_addr = -1;
714 #endif
715 } else {
716 efis->actual_phy_addr = efis->phy_addr;
717 }
718 #if defined(CONFIG_MII) && defined(CONFIG_RMII)
719
720 /* the MII interface is connected to FEC1
721 * so for the miiphy_xxx function to work we must
722 * call mii_init since fec_halt messes the thing up
723 */
724 if (efis->ether_index != 0)
725 mii_init();
726
727 /*
728 * adapt the RMII speed to the speed of the phy
729 */
730 if (miiphy_speed (dev->name, efis->actual_phy_addr) == _100BASET) {
731 fec_100Mbps (dev);
732 } else {
733 fec_10Mbps (dev);
734 }
735 #endif
736
737 #if defined(CONFIG_MII)
738 /*
739 * adapt to the half/full speed settings
740 */
741 if (miiphy_duplex (dev->name, efis->actual_phy_addr) == FULL) {
742 fec_full_duplex (dev);
743 } else {
744 fec_half_duplex (dev);
745 }
746 #endif
747
748 /* And last, try to fill Rx Buffer Descriptors */
749 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
750
751 efis->initialized = 1;
752
753 return 1;
754 }
755
756
757 static void fec_halt(struct eth_device* dev)
758 {
759 struct ether_fcc_info_s *efis = dev->priv;
760 volatile fec_t *fecp = (volatile fec_t *)(CFG_IMMR + efis->fecp_offset);
761 int i;
762
763 /* avoid halt if initialized; mii gets stuck otherwise */
764 if (!efis->initialized)
765 return;
766
767 /* Whack a reset.
768 * A delay is required between a reset of the FEC block and
769 * initialization of other FEC registers because the reset takes
770 * some time to complete. If you don't delay, subsequent writes
771 * to FEC registers might get killed by the reset routine which is
772 * still in progress.
773 */
774
775 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
776 for (i = 0;
777 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
778 ++i) {
779 udelay (1);
780 }
781 if (i == FEC_RESET_DELAY) {
782 printf ("FEC_RESET_DELAY timeout\n");
783 return;
784 }
785
786 efis->initialized = 0;
787 }
788
789 #if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
790
791 /* Make MII read/write commands for the FEC.
792 */
793
794 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
795 (REG & 0x1f) << 18))
796
797 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
798 (REG & 0x1f) << 18) | \
799 (VAL & 0xffff))
800
801 /* Interrupt events/masks.
802 */
803 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
804 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
805 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
806 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
807 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
808 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
809 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
810 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
811 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
812 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
813
814 /* PHY identification
815 */
816 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
817 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
818 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
819 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
820 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
821 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
822 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
823 #define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
824
825 /* send command to phy using mii, wait for result */
826 static uint
827 mii_send(uint mii_cmd)
828 {
829 uint mii_reply;
830 volatile fec_t *ep;
831 int cnt;
832
833 ep = &(((immap_t *)CFG_IMMR)->im_cpm.cp_fec);
834
835 ep->fec_mii_data = mii_cmd; /* command to phy */
836
837 /* wait for mii complete */
838 cnt = 0;
839 while (!(ep->fec_ievent & FEC_ENET_MII)) {
840 if (++cnt > 1000) {
841 printf("mii_send STUCK!\n");
842 break;
843 }
844 }
845 mii_reply = ep->fec_mii_data; /* result from phy */
846 ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
847 #if 0
848 printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
849 __FILE__,__LINE__,__FUNCTION__,mii_cmd,mii_reply);
850 #endif
851 return (mii_reply & 0xffff); /* data read from phy */
852 }
853 #endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
854
855 #if defined(CFG_DISCOVER_PHY)
856 static int mii_discover_phy(struct eth_device *dev)
857 {
858 #define MAX_PHY_PASSES 11
859 uint phyno;
860 int pass;
861 uint phytype;
862 int phyaddr;
863
864 phyaddr = -1; /* didn't find a PHY yet */
865 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
866 if (pass > 1) {
867 /* PHY may need more time to recover from reset.
868 * The LXT970 needs 50ms typical, no maximum is
869 * specified, so wait 10ms before try again.
870 * With 11 passes this gives it 100ms to wake up.
871 */
872 udelay(10000); /* wait 10ms */
873 }
874 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
875 phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1));
876 #ifdef ET_DEBUG
877 printf("PHY type 0x%x pass %d type ", phytype, pass);
878 #endif
879 if (phytype != 0xffff) {
880 phyaddr = phyno;
881 phytype <<= 16;
882 phytype |= mii_send(mk_mii_read(phyno,
883 PHY_PHYIDR2));
884
885 #ifdef ET_DEBUG
886 printf("PHY @ 0x%x pass %d type ",phyno,pass);
887 switch (phytype & 0xfffffff0) {
888 case PHY_ID_LXT970:
889 printf("LXT970\n");
890 break;
891 case PHY_ID_LXT971:
892 printf("LXT971\n");
893 break;
894 case PHY_ID_82555:
895 printf("82555\n");
896 break;
897 case PHY_ID_QS6612:
898 printf("QS6612\n");
899 break;
900 case PHY_ID_AMD79C784:
901 printf("AMD79C784\n");
902 break;
903 case PHY_ID_LSI80225B:
904 printf("LSI L80225/B\n");
905 break;
906 case PHY_ID_DM9161:
907 printf("Davicom DM9161\n");
908 break;
909 default:
910 printf("0x%08x\n", phytype);
911 break;
912 }
913 #endif
914 }
915 }
916 }
917 if (phyaddr < 0) {
918 printf("No PHY device found.\n");
919 }
920 return phyaddr;
921 }
922 #endif /* CFG_DISCOVER_PHY */
923
924 #if (defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
925
926 /****************************************************************************
927 * mii_init -- Initialize the MII for MII command without ethernet
928 * This function is a subset of eth_init
929 ****************************************************************************
930 */
931 void mii_init (void)
932 {
933 volatile immap_t *immr = (immap_t *) CFG_IMMR;
934 volatile fec_t *fecp = &(immr->im_cpm.cp_fec);
935 int i, j;
936
937 for (j = 0; j < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); j++) {
938
939 /* Whack a reset.
940 * A delay is required between a reset of the FEC block and
941 * initialization of other FEC registers because the reset takes
942 * some time to complete. If you don't delay, subsequent writes
943 * to FEC registers might get killed by the reset routine which is
944 * still in progress.
945 */
946
947 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET;
948 for (i = 0;
949 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
950 ++i) {
951 udelay (1);
952 }
953 if (i == FEC_RESET_DELAY) {
954 printf ("FEC_RESET_DELAY timeout\n");
955 return;
956 }
957
958 /* We use strictly polling mode only
959 */
960 fecp->fec_imask = 0;
961
962 /* Clear any pending interrupt
963 */
964 fecp->fec_ievent = 0xffc0;
965
966 /* Setup the pin configuration of the FEC(s)
967 */
968 fec_pin_init(ether_fcc_info[i].ether_index);
969
970 /* Now enable the transmit and receive processing
971 */
972 fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
973 }
974 }
975
976 /*****************************************************************************
977 * Read and write a MII PHY register, routines used by MII Utilities
978 *
979 * FIXME: These routines are expected to return 0 on success, but mii_send
980 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
981 * no PHY connected...
982 * For now always return 0.
983 * FIXME: These routines only work after calling eth_init() at least once!
984 * Otherwise they hang in mii_send() !!! Sorry!
985 *****************************************************************************/
986
987 int fec8xx_miiphy_read(char *devname, unsigned char addr,
988 unsigned char reg, unsigned short *value)
989 {
990 short rdreg; /* register working value */
991
992 #ifdef MII_DEBUG
993 printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
994 #endif
995 rdreg = mii_send(mk_mii_read(addr, reg));
996
997 *value = rdreg;
998 #ifdef MII_DEBUG
999 printf ("0x%04x\n", *value);
1000 #endif
1001 return 0;
1002 }
1003
1004 int fec8xx_miiphy_write(char *devname, unsigned char addr,
1005 unsigned char reg, unsigned short value)
1006 {
1007 short rdreg; /* register working value */
1008 #ifdef MII_DEBUG
1009 printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
1010 #endif
1011 rdreg = mii_send(mk_mii_write(addr, reg, value));
1012
1013 #ifdef MII_DEBUG
1014 printf ("0x%04x\n", value);
1015 #endif
1016 return 0;
1017 }
1018 #endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)*/
1019
1020 #endif /* CFG_CMD_NET, FEC_ENET */
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