cpu/mpc8xx/serial.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <commproc.h>
  26 #include <command.h>
  27 #include <serial.h>
  28 #include <watchdog.h>
  29
  30 #if !defined(CONFIG_8xx_CONS_NONE)      /* No Console at all */
  31
  32 #if defined(CONFIG_8xx_CONS_SMC1)       /* Console on SMC1 */
  33 #define SMC_INDEX       0
  34 #define PROFF_SMC       PROFF_SMC1
  35 #define CPM_CR_CH_SMC   CPM_CR_CH_SMC1
  36
  37 #elif defined(CONFIG_8xx_CONS_SMC2)     /* Console on SMC2 */
  38 #define SMC_INDEX       1
  39 #define PROFF_SMC       PROFF_SMC2
  40 #define CPM_CR_CH_SMC   CPM_CR_CH_SMC2
  41
  42 #endif /* CONFIG_8xx_CONS_SMCx */
  43
  44 #if defined(CONFIG_8xx_CONS_SCC1)       /* Console on SCC1 */
  45 #define SCC_INDEX       0
  46 #define PROFF_SCC       PROFF_SCC1
  47 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC1
  48
  49 #elif defined(CONFIG_8xx_CONS_SCC2)     /* Console on SCC2 */
  50 #define SCC_INDEX       1
  51 #define PROFF_SCC       PROFF_SCC2
  52 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC2
  53
  54 #elif defined(CONFIG_8xx_CONS_SCC3)     /* Console on SCC3 */
  55 #define SCC_INDEX       2
  56 #define PROFF_SCC       PROFF_SCC3
  57 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC3
  58
  59 #elif defined(CONFIG_8xx_CONS_SCC4)     /* Console on SCC4 */
  60 #define SCC_INDEX       3
  61 #define PROFF_SCC       PROFF_SCC4
  62 #define CPM_CR_CH_SCC   CPM_CR_CH_SCC4
  63
  64 #endif /* CONFIG_8xx_CONS_SCCx */
  65
  66 static void serial_setdivisor(volatile cpm8xx_t *cp)
  67 {
  68         DECLARE_GLOBAL_DATA_PTR;
  69         int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
  70
  71         if(divisor/16>0x1000) {
  72                 /* bad divisor, assume 50Mhz clock and 9600 baud */
  73                 divisor=(50*1000*1000 + 8*9600)/16/9600;
  74         }
  75
  76 #ifdef CFG_BRGCLK_PRESCALE
  77         divisor /= CFG_BRGCLK_PRESCALE;
  78 #endif
  79
  80         if(divisor<=0x1000) {
  81                 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
  82         } else {
  83                 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
  84         }
  85 }
  86
  87 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
  88
  89 /*
  90  * Minimal serial functions needed to use one of the SMC ports
  91  * as serial console interface.
  92  */
  93
  94 static void smc_setbrg (void)
  95 {
  96         volatile immap_t *im = (immap_t *)CFG_IMMR;
  97         volatile cpm8xx_t *cp = &(im->im_cpm);
  98
  99         /* Set up the baud rate generator.
 100          * See 8xx_io/commproc.c for details.
 101          *
 102          * Wire BRG1 to SMCx
 103          */
 104
 105         cp->cp_simode = 0x00000000;
 106
 107         serial_setdivisor(cp);
 108 }
 109
 110 static int smc_init (void)
 111 {
 112         volatile immap_t *im = (immap_t *)CFG_IMMR;
 113         volatile smc_t *sp;
 114         volatile smc_uart_t *up;
 115         volatile cbd_t *tbdf, *rbdf;
 116         volatile cpm8xx_t *cp = &(im->im_cpm);
 117 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
 118         volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
 119 #endif
 120         uint    dpaddr;
 121
 122         /* initialize pointers to SMC */
 123
 124         sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
 125         up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
 126
 127         /* Disable transmitter/receiver.
 128         */
 129         sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
 130
 131         /* Enable SDMA.
 132         */
 133         im->im_siu_conf.sc_sdcr = 1;
 134
 135         /* clear error conditions */
 136 #ifdef  CFG_SDSR
 137         im->im_sdma.sdma_sdsr = CFG_SDSR;
 138 #else
 139         im->im_sdma.sdma_sdsr = 0x83;
 140 #endif
 141
 142         /* clear SDMA interrupt mask */
 143 #ifdef  CFG_SDMR
 144         im->im_sdma.sdma_sdmr = CFG_SDMR;
 145 #else
 146         im->im_sdma.sdma_sdmr = 0x00;
 147 #endif
 148
 149 #if defined(CONFIG_8xx_CONS_SMC1)
 150         /* Use Port B for SMC1 instead of other functions.
 151         */
 152         cp->cp_pbpar |=  0x000000c0;
 153         cp->cp_pbdir &= ~0x000000c0;
 154         cp->cp_pbodr &= ~0x000000c0;
 155 #else   /* CONFIG_8xx_CONS_SMC2 */
 156 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
 157         /* Use Port A for SMC2 instead of other functions.
 158         */
 159         ip->iop_papar |=  0x00c0;
 160         ip->iop_padir &= ~0x00c0;
 161         ip->iop_paodr &= ~0x00c0;
 162 # else  /* must be a 860 then */
 163         /* Use Port B for SMC2 instead of other functions.
 164         */
 165         cp->cp_pbpar |=  0x00000c00;
 166         cp->cp_pbdir &= ~0x00000c00;
 167         cp->cp_pbodr &= ~0x00000c00;
 168 # endif
 169 #endif
 170
 171 #if defined(CONFIG_FADS) || defined(CONFIG_ADS)
 172         /* Enable RS232 */
 173 #if defined(CONFIG_8xx_CONS_SMC1)
 174         *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
 175 #else
 176         *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
 177 #endif
 178 #endif  /* CONFIG_FADS */
 179
 180 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
 181         /* Enable Monitor Port Transceiver */
 182         *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
 183 #endif /* CONFIG_RPXLITE */
 184
 185         /* Set the physical address of the host memory buffers in
 186          * the buffer descriptors.
 187          */
 188
 189 #ifdef CFG_ALLOC_DPRAM
 190         dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
 191 #else
 192         dpaddr = CPM_SERIAL_BASE ;
 193 #endif
 194
 195         /* Allocate space for two buffer descriptors in the DP ram.
 196          * For now, this address seems OK, but it may have to
 197          * change with newer versions of the firmware.
 198          * damm: allocating space after the two buffers for rx/tx data
 199          */
 200
 201         rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
 202         rbdf->cbd_bufaddr = (uint) (rbdf+2);
 203         rbdf->cbd_sc = 0;
 204         tbdf = rbdf + 1;
 205         tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
 206         tbdf->cbd_sc = 0;
 207
 208         /* Set up the uart parameters in the parameter ram.
 209         */
 210         up->smc_rbase = dpaddr;
 211         up->smc_tbase = dpaddr+sizeof(cbd_t);
 212         up->smc_rfcr = SMC_EB;
 213         up->smc_tfcr = SMC_EB;
 214
 215 #if defined(CONFIG_MBX)
 216         board_serial_init();
 217 #endif  /* CONFIG_MBX */
 218
 219         /* Set UART mode, 8 bit, no parity, one stop.
 220          * Enable receive and transmit.
 221          */
 222         sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
 223
 224         /* Mask all interrupts and remove anything pending.
 225         */
 226         sp->smc_smcm = 0;
 227         sp->smc_smce = 0xff;
 228
 229         /* Set up the baud rate generator.
 230         */
 231         smc_setbrg ();
 232
 233         /* Make the first buffer the only buffer.
 234         */
 235         tbdf->cbd_sc |= BD_SC_WRAP;
 236         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 237
 238         /* Single character receive.
 239         */
 240         up->smc_mrblr = 1;
 241         up->smc_maxidl = 0;
 242
 243         /* Initialize Tx/Rx parameters.
 244         */
 245
 246         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 247           ;
 248
 249         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 250
 251         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 252           ;
 253
 254         /* Enable transmitter/receiver.
 255         */
 256         sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
 257
 258         return (0);
 259 }
 260
 261 static void
 262 smc_putc(const char c)
 263 {
 264         volatile cbd_t          *tbdf;
 265         volatile char           *buf;
 266         volatile smc_uart_t     *up;
 267         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 268         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 269
 270 #ifdef CONFIG_MODEM_SUPPORT
 271         DECLARE_GLOBAL_DATA_PTR;
 272
 273         if (gd->be_quiet)
 274                 return;
 275 #endif
 276
 277         if (c == '\n')
 278                 smc_putc ('\r');
 279
 280         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 281
 282         tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
 283
 284         /* Wait for last character to go.
 285         */
 286
 287         buf = (char *)tbdf->cbd_bufaddr;
 288
 289         *buf = c;
 290         tbdf->cbd_datlen = 1;
 291         tbdf->cbd_sc |= BD_SC_READY;
 292         __asm__("eieio");
 293
 294         while (tbdf->cbd_sc & BD_SC_READY) {
 295                 WATCHDOG_RESET ();
 296                 __asm__("eieio");
 297         }
 298 }
 299
 300 static void
 301 smc_puts (const char *s)
 302 {
 303         while (*s) {
 304                 smc_putc (*s++);
 305         }
 306 }
 307
 308 static int
 309 smc_getc(void)
 310 {
 311         volatile cbd_t          *rbdf;
 312         volatile unsigned char  *buf;
 313         volatile smc_uart_t     *up;
 314         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 315         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 316         unsigned char           c;
 317
 318         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 319
 320         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
 321
 322         /* Wait for character to show up.
 323         */
 324         buf = (unsigned char *)rbdf->cbd_bufaddr;
 325
 326         while (rbdf->cbd_sc & BD_SC_EMPTY)
 327                 WATCHDOG_RESET ();
 328
 329         c = *buf;
 330         rbdf->cbd_sc |= BD_SC_EMPTY;
 331
 332         return(c);
 333 }
 334
 335 static int
 336 smc_tstc(void)
 337 {
 338         volatile cbd_t          *rbdf;
 339         volatile smc_uart_t     *up;
 340         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 341         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 342
 343         up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
 344
 345         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
 346
 347         return(!(rbdf->cbd_sc & BD_SC_EMPTY));
 348 }
 349
 350 struct serial_device serial_smc_device =
 351 {
 352         "serial_smc",
 353         "SMC",
 354         smc_init,
 355         smc_setbrg,
 356         smc_getc,
 357         smc_tstc,
 358         smc_putc,
 359         smc_puts,
 360 };
 361
 362 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
 363
 364 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
 365     defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
 366
 367 static void
 368 scc_setbrg (void)
 369 {
 370         volatile immap_t *im = (immap_t *)CFG_IMMR;
 371         volatile cpm8xx_t *cp = &(im->im_cpm);
 372
 373         /* Set up the baud rate generator.
 374          * See 8xx_io/commproc.c for details.
 375          *
 376          * Wire BRG1 to SCCx
 377          */
 378
 379         cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
 380
 381         serial_setdivisor(cp);
 382 }
 383
 384 static int scc_init (void)
 385 {
 386         volatile immap_t *im = (immap_t *)CFG_IMMR;
 387         volatile scc_t *sp;
 388         volatile scc_uart_t *up;
 389         volatile cbd_t *tbdf, *rbdf;
 390         volatile cpm8xx_t *cp = &(im->im_cpm);
 391         uint     dpaddr;
 392 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
 393         volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
 394 #endif
 395
 396         /* initialize pointers to SCC */
 397
 398         sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
 399         up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
 400
 401 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
 402     {   /* Disable Ethernet, enable Serial */
 403         uchar c;
 404
 405         c = pic_read  (0x61);
 406         c &= ~0x40;     /* enable COM3 */
 407         c |=  0x80;     /* disable Ethernet */
 408         pic_write (0x61, c);
 409
 410         /* enable RTS2 */
 411         cp->cp_pbpar |=  0x2000;
 412         cp->cp_pbdat |=  0x2000;
 413         cp->cp_pbdir |=  0x2000;
 414     }
 415 #endif  /* CONFIG_LWMON */
 416
 417         /* Disable transmitter/receiver.
 418         */
 419         sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 420
 421 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
 422         /*
 423          * The MPC850 has SCC3 on Port B
 424          */
 425         cp->cp_pbpar |=  0x06;
 426         cp->cp_pbdir &= ~0x06;
 427         cp->cp_pbodr &= ~0x06;
 428
 429 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
 430         /*
 431          * Standard configuration for SCC's is on Part A
 432          */
 433         ip->iop_papar |=  ((3 << (2 * SCC_INDEX)));
 434         ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
 435         ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
 436 #else
 437         /*
 438          * The IP860 has SCC3 and SCC4 on Port D
 439          */
 440         ip->iop_pdpar |=  ((3 << (2 * SCC_INDEX)));
 441 #endif
 442
 443         /* Allocate space for two buffer descriptors in the DP ram.
 444          */
 445
 446 #ifdef CFG_ALLOC_DPRAM
 447         dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
 448 #else
 449         dpaddr = CPM_SERIAL2_BASE ;
 450 #endif
 451
 452         /* Enable SDMA.
 453         */
 454         im->im_siu_conf.sc_sdcr = 0x0001;
 455
 456         /* Set the physical address of the host memory buffers in
 457          * the buffer descriptors.
 458          */
 459
 460         rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
 461         rbdf->cbd_bufaddr = (uint) (rbdf+2);
 462         rbdf->cbd_sc = 0;
 463         tbdf = rbdf + 1;
 464         tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
 465         tbdf->cbd_sc = 0;
 466
 467         /* Set up the baud rate generator.
 468         */
 469         scc_setbrg ();
 470
 471         /* Set up the uart parameters in the parameter ram.
 472         */
 473         up->scc_genscc.scc_rbase = dpaddr;
 474         up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
 475
 476         /* Initialize Tx/Rx parameters.
 477         */
 478         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 479                 ;
 480         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 481
 482         while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
 483                 ;
 484
 485         up->scc_genscc.scc_rfcr  = SCC_EB | 0x05;
 486         up->scc_genscc.scc_tfcr  = SCC_EB | 0x05;
 487
 488         up->scc_genscc.scc_mrblr = 1;   /* Single character receive */
 489         up->scc_maxidl = 0;             /* disable max idle */
 490         up->scc_brkcr  = 1;             /* send one break character on stop TX */
 491         up->scc_parec  = 0;
 492         up->scc_frmec  = 0;
 493         up->scc_nosec  = 0;
 494         up->scc_brkec  = 0;
 495         up->scc_uaddr1 = 0;
 496         up->scc_uaddr2 = 0;
 497         up->scc_toseq  = 0;
 498         up->scc_char1  = 0x8000;
 499         up->scc_char2  = 0x8000;
 500         up->scc_char3  = 0x8000;
 501         up->scc_char4  = 0x8000;
 502         up->scc_char5  = 0x8000;
 503         up->scc_char6  = 0x8000;
 504         up->scc_char7  = 0x8000;
 505         up->scc_char8  = 0x8000;
 506         up->scc_rccm   = 0xc0ff;
 507
 508         /* Set low latency / small fifo.
 509          */
 510         sp->scc_gsmrh = SCC_GSMRH_RFW;
 511
 512         /* Set SCC(x) clock mode to 16x
 513          * See 8xx_io/commproc.c for details.
 514          *
 515          * Wire BRG1 to SCCn
 516          */
 517
 518         /* Set UART mode, clock divider 16 on Tx and Rx
 519          */
 520         sp->scc_gsmrl &= ~0xF;
 521         sp->scc_gsmrl |=
 522                 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
 523
 524         sp->scc_psmr  = 0;
 525         sp->scc_psmr  |= SCU_PSMR_CL;
 526
 527         /* Mask all interrupts and remove anything pending.
 528         */
 529         sp->scc_sccm = 0;
 530         sp->scc_scce = 0xffff;
 531         sp->scc_dsr  = 0x7e7e;
 532         sp->scc_psmr = 0x3000;
 533
 534         /* Make the first buffer the only buffer.
 535         */
 536         tbdf->cbd_sc |= BD_SC_WRAP;
 537         rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
 538
 539         /* Enable transmitter/receiver.
 540         */
 541         sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 542
 543         return (0);
 544 }
 545
 546 static void
 547 scc_putc(const char c)
 548 {
 549         volatile cbd_t          *tbdf;
 550         volatile char           *buf;
 551         volatile scc_uart_t     *up;
 552         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 553         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 554
 555 #ifdef CONFIG_MODEM_SUPPORT
 556         DECLARE_GLOBAL_DATA_PTR;
 557
 558         if (gd->be_quiet)
 559                 return;
 560 #endif
 561
 562         if (c == '\n')
 563                 scc_putc ('\r');
 564
 565         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 566
 567         tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
 568
 569         /* Wait for last character to go.
 570         */
 571
 572         buf = (char *)tbdf->cbd_bufaddr;
 573
 574         *buf = c;
 575         tbdf->cbd_datlen = 1;
 576         tbdf->cbd_sc |= BD_SC_READY;
 577         __asm__("eieio");
 578
 579         while (tbdf->cbd_sc & BD_SC_READY) {
 580                 __asm__("eieio");
 581                 WATCHDOG_RESET ();
 582         }
 583 }
 584
 585 static void
 586 scc_puts (const char *s)
 587 {
 588         while (*s) {
 589                 scc_putc (*s++);
 590         }
 591 }
 592
 593 static int
 594 scc_getc(void)
 595 {
 596         volatile cbd_t          *rbdf;
 597         volatile unsigned char  *buf;
 598         volatile scc_uart_t     *up;
 599         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 600         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 601         unsigned char           c;
 602
 603         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 604
 605         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 606
 607         /* Wait for character to show up.
 608         */
 609         buf = (unsigned char *)rbdf->cbd_bufaddr;
 610
 611         while (rbdf->cbd_sc & BD_SC_EMPTY)
 612                 WATCHDOG_RESET ();
 613
 614         c = *buf;
 615         rbdf->cbd_sc |= BD_SC_EMPTY;
 616
 617         return(c);
 618 }
 619
 620 static int
 621 scc_tstc(void)
 622 {
 623         volatile cbd_t          *rbdf;
 624         volatile scc_uart_t     *up;
 625         volatile immap_t        *im = (immap_t *)CFG_IMMR;
 626         volatile cpm8xx_t       *cpmp = &(im->im_cpm);
 627
 628         up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
 629
 630         rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
 631
 632         return(!(rbdf->cbd_sc & BD_SC_EMPTY));
 633 }
 634
 635 struct serial_device serial_scc_device =
 636 {
 637         "serial_scc",
 638         "SCC",
 639         scc_init,
 640         scc_setbrg,
 641         scc_getc,
 642         scc_tstc,
 643         scc_putc,
 644         scc_puts,
 645 };
 646
 647 #endif  /* CONFIG_8xx_CONS_SCCx */
 648
 649 #ifdef CONFIG_MODEM_SUPPORT
 650 void disable_putc(void)
 651 {
 652         DECLARE_GLOBAL_DATA_PTR;
 653         gd->be_quiet = 1;
 654 }
 655
 656 void enable_putc(void)
 657 {
 658         DECLARE_GLOBAL_DATA_PTR;
 659         gd->be_quiet = 0;
 660 }
 661 #endif
 662
 663 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 664
 665 void
 666 kgdb_serial_init(void)
 667 {
 668         int i = -1;
 669
 670         if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
 671         {
 672 #if defined(CONFIG_8xx_CONS_SMC1)
 673                 i = 1;
 674 #elif defined(CONFIG_8xx_CONS_SMC2)
 675                 i = 2;
 676 #endif
 677         }
 678         else if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
 679         {
 680 #if defined(CONFIG_8xx_CONS_SCC1)
 681                 i = 1;
 682 #elif defined(CONFIG_8xx_CONS_SCC2)
 683                 i = 2;
 684 #elif defined(CONFIG_8xx_CONS_SCC3)
 685                 i = 3;
 686 #elif defined(CONFIG_8xx_CONS_SCC4)
 687                 i = 4;
 688 #endif
 689         }
 690
 691         if (i >= 0)
 692         {
 693                 serial_printf("[on %s%d] ", default_serial_console()->ctlr, i);
 694         }
 695 }
 696
 697 void
 698 putDebugChar (int c)
 699 {
 700         serial_putc (c);
 701 }
 702
 703 void
 704 putDebugStr (const char *str)
 705 {
 706         serial_puts (str);
 707 }
 708
 709 int
 710 getDebugChar (void)
 711 {
 712         return serial_getc();
 713 }
 714
 715 void
 716 kgdb_interruptible (int yes)
 717 {
 718         return;
 719 }
 720 #endif  /* CFG_CMD_KGDB */
 721
 722 #endif  /* CONFIG_8xx_CONS_NONE */