cpu/mpc8xx/speed.c

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <mpc8xx.h>
  26 #include <asm/processor.h>
  27
  28 #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK) || defined(DEBUG)
  29
  30 #define PITC_SHIFT 16
  31 #define PITR_SHIFT 16
  32 /* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */
  33 #define SPEED_PIT_COUNTS 58
  34 #define SPEED_PITC       ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT)
  35 #define SPEED_PITC_INIT  ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT)
  36
  37 /* Access functions for the Machine State Register */
  38 static __inline__ unsigned long get_msr(void)
  39 {
  40         unsigned long msr;
  41
  42         asm volatile("mfmsr %0" : "=r" (msr) :);
  43         return msr;
  44 }
  45
  46 static __inline__ void set_msr(unsigned long msr)
  47 {
  48         asm volatile("mtmsr %0" : : "r" (msr));
  49 }
  50
  51 /* ------------------------------------------------------------------------- */
  52
  53 /*
  54  * Measure CPU clock speed (core clock GCLK1, GCLK2),
  55  * also determine bus clock speed (checking bus divider factor)
  56  *
  57  * (Approx. GCLK frequency in Hz)
  58  *
  59  * Initializes timer 2 and PIT, but disables them before return.
  60  * [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4]
  61  *
  62  * When measuring the CPU clock against the PIT, we count cpu clocks
  63  * for 58/8192 seconds with a prescale divide by 177 for the cpu clock.
  64  * These strange values for the timing interval and prescaling are used
  65  * because the formula for the CPU clock is:
  66  *
  67  *    CPU clock = count * (177 * (8192 / 58))
  68  *
  69  *              = count * 24999.7241
  70  *
  71  *    which is very close to
  72  *
  73  *              = count * 25000
  74  *
  75  * Since the count gives the CPU clock divided by 25000, we can get
  76  * the CPU clock rounded to the nearest 0.1 MHz by
  77  *
  78  *    CPU clock = ((count + 2) / 4) * 100000;
  79  *
  80  * The rounding is important since the measurement is sometimes going
  81  * to be high or low by 0.025 MHz, depending on exactly how the clocks
  82  * and counters interact. By rounding we get the exact answer for any
  83  * CPU clock that is an even multiple of 0.1 MHz.
  84  */
  85
  86 unsigned long measure_gclk(void)
  87 {
  88         volatile immap_t *immr = (immap_t *) CFG_IMMR;
  89         volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
  90         ulong timer2_val;
  91         ulong msr_val;
  92
  93 #ifdef CFG_8XX_XIN
  94         /* dont use OSCM, only use EXTCLK/512 */
  95         immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
  96 #else
  97         immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV);
  98 #endif
  99
 100         /* Reset + Stop Timer 2, no cascading
 101          */
 102         timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2);
 103
 104         /* Keep stopped, halt in debug mode
 105          */
 106         timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2);
 107
 108         /* Timer 2 setup:
 109          * Output ref. interrupt disable, int. clock
 110          * Prescale by 177. Note that prescaler divides by value + 1
 111          * so we must subtract 1 here.
 112          */
 113         timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN;
 114
 115         timerp->cpmt_tcn2 = 0;          /* reset state          */
 116         timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2       */
 117
 118         /*
 119          * PIT setup:
 120          *
 121          * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz),
 122          * so the count value would be SPEED_PITC_COUNTS - 1.
 123          * But there would be an uncertainty in the start time of 1/4
 124          * count since when we enable the PIT the count is not
 125          * synchronized to the 32768 Hz oscillator. The trick here is
 126          * to start the count higher and wait until the PIT count
 127          * changes to the required value before starting timer 2.
 128          *
 129          * One count high should be enough, but occasionally the start
 130          * is off by 1 or 2 counts of 32768 Hz. With the start value
 131          * set two counts high it seems very reliable.
 132          */
 133
 134         immr->im_sitk.sitk_pitck = KAPWR_KEY;   /* PIT initialization */
 135         immr->im_sit.sit_pitc = SPEED_PITC_INIT;
 136
 137         immr->im_sitk.sitk_piscrk = KAPWR_KEY;
 138         immr->im_sit.sit_piscr = CFG_PISCR;
 139
 140         /*
 141          * Start measurement - disable interrupts, just in case
 142          */
 143         msr_val = get_msr ();
 144         set_msr (msr_val & ~MSR_EE);
 145
 146         immr->im_sit.sit_piscr |= PISCR_PTE;
 147
 148         /* spin until get exact count when we want to start */
 149         while (immr->im_sit.sit_pitr > SPEED_PITC);
 150
 151         timerp->cpmt_tgcr &= ~TGCR_STP2;        /* Start Timer 2        */
 152         while ((immr->im_sit.sit_piscr & PISCR_PS) == 0);
 153         timerp->cpmt_tgcr |= TGCR_STP2;         /* Stop  Timer 2        */
 154
 155         /* re-enable external interrupts if they were on */
 156         set_msr (msr_val);
 157
 158         /* Disable timer and PIT
 159          */
 160         timer2_val = timerp->cpmt_tcn2;         /* save before reset timer */
 161
 162         timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
 163         immr->im_sit.sit_piscr &= ~PISCR_PTE;
 164
 165 #if defined(CFG_8XX_XIN)
 166         /* not using OSCM, using XIN, so scale appropriately */
 167         return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
 168 #else
 169         return ((timer2_val + 2) / 4) * 100000L;        /* convert to Hz        */
 170 #endif
 171 }
 172
 173 #endif
 174
 175 #if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
 176
 177 /*
 178  * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
 179  * or (if it is not defined) measure_gclk() (which uses the ref clock)
 180  * from above.
 181  */
 182 int get_clocks (void)
 183 {
 184         DECLARE_GLOBAL_DATA_PTR;
 185
 186         uint immr = get_immr (0);       /* Return full IMMR contents */
 187         volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000);
 188         uint sccr = immap->im_clkrst.car_sccr;
 189         /*
 190          * If for some reason measuring the gclk frequency won't
 191          * work, we return the hardwired value.
 192          * (For example, the cogent CMA286-60 CPU module has no
 193          * separate oscillator for PITRTCLK)
 194          */
 195 #if defined(CONFIG_8xx_GCLK_FREQ)
 196         gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
 197 #elif defined(CONFIG_8xx_OSCLK)
 198 #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
 199         uint pll = immap->im_clkrst.car_plprcr;
 200         uint clk;
 201
 202         if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */
 203                 clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) *
 204                        (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) /
 205                         (1<<PLPRCR_val(S));
 206         } else {
 207                 clk = CONFIG_8xx_OSCLK * (PLPRCR_val(MF)+1);
 208         }
 209         if (pll & PLPRCR_CSRC) {        /* Low frequency division factor is used  */
 210                 gd->cpu_clk = clk / (2 << ((sccr >> 8) & 7));
 211         } else {                        /* High frequency division factor is used */
 212                 gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7));
 213         }
 214 #else
 215         gd->cpu_clk = measure_gclk();
 216 #endif /* CONFIG_8xx_GCLK_FREQ */
 217
 218         if ((sccr & SCCR_EBDF11) == 0) {
 219                 /* No Bus Divider active */
 220                 gd->bus_clk = gd->cpu_clk;
 221         } else {
 222                 /* The MPC8xx has only one BDF: half clock speed */
 223                 gd->bus_clk = gd->cpu_clk / 2;
 224         }
 225
 226         return (0);
 227 }
 228
 229 #else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */
 230
 231 static long init_pll_866 (long clk);
 232
 233 /* This function sets up PLL (init_pll_866() is called) and
 234  * fills gd->cpu_clk and gd->bus_clk according to the environment
 235  * variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk'
 236  * contains invalid value).
 237  * This functions requires an MPC866 or newer series CPU.
 238  */
 239 int get_clocks_866 (void)
 240 {
 241         DECLARE_GLOBAL_DATA_PTR;
 242
 243         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 244         char              tmp[64];
 245         long              cpuclk = 0;
 246         long              sccr_reg;
 247
 248         if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
 249                 cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
 250
 251         if ((CFG_8xx_CPUCLK_MIN > cpuclk) || (CFG_8xx_CPUCLK_MAX < cpuclk))
 252                 cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;
 253
 254         gd->cpu_clk = init_pll_866 (cpuclk);
 255 #if defined(CFG_MEASURE_CPUCLK)
 256         gd->cpu_clk = measure_gclk ();
 257 #endif
 258
 259         /* if cpu clock <= 66 MHz then set bus division factor to 1,
 260          * otherwise set it to 2
 261          */
 262         sccr_reg = immr->im_clkrst.car_sccr;
 263         sccr_reg &= ~SCCR_EBDF11;
 264         if (gd->cpu_clk <= 66000000) {
 265                 sccr_reg |= SCCR_EBDF00;        /* bus division factor = 1 */
 266                 gd->bus_clk = gd->cpu_clk;
 267         } else {
 268                 sccr_reg |= SCCR_EBDF01;        /* bus division factor = 2 */
 269                 gd->bus_clk = gd->cpu_clk / 2;
 270         }
 271         immr->im_clkrst.car_sccr = sccr_reg;
 272
 273         return (0);
 274 }
 275
 276 /* Adjust sdram refresh rate to actual CPU clock.
 277  */
 278 int sdram_adjust_866 (void)
 279 {
 280         DECLARE_GLOBAL_DATA_PTR;
 281
 282         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 283         long              mamr;
 284
 285         mamr = immr->im_memctl.memc_mamr;
 286         mamr &= ~MAMR_PTA_MSK;
 287         mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
 288         immr->im_memctl.memc_mamr = mamr;
 289
 290         return (0);
 291 }
 292
 293 /* Configure PLL for MPC866/859/885 CPU series
 294  * PLL multiplication factor is set to the value nearest to the desired clk,
 295  * assuming a oscclk of 10 MHz.
 296  */
 297 static long init_pll_866 (long clk)
 298 {
 299         extern void plprcr_write_866 (long);
 300
 301         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 302         long              n, plprcr;
 303         char              mfi, mfn, mfd, s, pdf;
 304         long              step_mfi, step_mfn;
 305
 306         if (clk < 20000000) {
 307                 clk *= 2;
 308                 pdf = 1;
 309         } else {
 310                 pdf = 0;
 311         }
 312
 313         if (clk < 40000000) {
 314                 s = 2;
 315                 step_mfi = CONFIG_8xx_OSCLK / 4;
 316                 mfd = 7;
 317                 step_mfn = CONFIG_8xx_OSCLK / 30;
 318         } else if (clk < 80000000) {
 319                 s = 1;
 320                 step_mfi = CONFIG_8xx_OSCLK / 2;
 321                 mfd = 14;
 322                 step_mfn = CONFIG_8xx_OSCLK / 30;
 323         } else {
 324                 s = 0;
 325                 step_mfi = CONFIG_8xx_OSCLK;
 326                 mfd = 29;
 327                 step_mfn = CONFIG_8xx_OSCLK / 30;
 328         }
 329
 330         /* Calculate integer part of multiplication factor
 331          */
 332         n = clk / step_mfi;
 333         mfi = (char)n;
 334
 335         /* Calculate numerator of fractional part of multiplication factor
 336          */
 337         n = clk - (n * step_mfi);
 338         mfn = (char)(n / step_mfn);
 339
 340         /* Calculate effective clk
 341          */
 342         n = ((mfi * step_mfi) + (mfn * step_mfn)) / (pdf + 1);
 343
 344         immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
 345
 346         plprcr = (immr->im_clkrst.car_plprcr & ~(PLPRCR_MFN_MSK
 347                         | PLPRCR_MFD_MSK | PLPRCR_S_MSK
 348                         | PLPRCR_MFI_MSK | PLPRCR_DBRMO
 349                         | PLPRCR_PDF_MSK))
 350                         | (mfn << PLPRCR_MFN_SHIFT)
 351                         | (mfd << PLPRCR_MFD_SHIFT)
 352                         | (s << PLPRCR_S_SHIFT)
 353                         | (mfi << PLPRCR_MFI_SHIFT)
 354                         | (pdf << PLPRCR_PDF_SHIFT);
 355
 356         if( (mfn > 0) && ((mfd / mfn) > 10) )
 357                 plprcr |= PLPRCR_DBRMO;
 358
 359         plprcr_write_866 (plprcr);              /* set value using SIU4/9 workaround */
 360         immr->im_clkrstk.cark_plprcrk = 0x00000000;
 361
 362         return (n);
 363 }
 364
 365 #endif /* CONFIG_8xx_CPUCLK_DEFAULT */
 366
 367 #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
 368 /*
 369  * Adjust sdram refresh rate to actual CPU clock
 370  * and set timebase source according to actual CPU clock
 371  */
 372 int adjust_sdram_tbs_8xx (void)
 373 {
 374         DECLARE_GLOBAL_DATA_PTR;
 375
 376         volatile immap_t *immr = (immap_t *) CFG_IMMR;
 377         long              mamr;
 378         long              sccr;
 379
 380         mamr = immr->im_memctl.memc_mamr;
 381         mamr &= ~MAMR_PTA_MSK;
 382         mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
 383         immr->im_memctl.memc_mamr = mamr;
 384
 385         if (gd->cpu_clk < 67000000) {
 386                 sccr = immr->im_clkrst.car_sccr;
 387                 sccr |= SCCR_TBS;
 388                 immr->im_clkrst.car_sccr = sccr;
 389         }
 390
 391         return (0);
 392 }
 393 #endif /* CONFIG_TQM8xxL/M, !TQM866M */
 394
 395 /* ------------------------------------------------------------------------- */