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1 /*-----------------------------------------------------------------------------+
2 *
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
9 *
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
13 *
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
17 *
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
22 *
23 * File Name: enetemac.c
24 *
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
26 *
27 * Author: Mark Wisner
28 *
29 * Change Activity-
30 *
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
48 * include/net.h
49 * - Receive buffer descriptor ring is used to send buffers
50 * to the user
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
66 * used anymore)
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 * 21-Nov-03 pavel.bartusek@sysgo.com
71 * - set ZMII bridge speed on 440
72 *
73 *-----------------------------------------------------------------------------*/
74
75 #include <common.h>
76 #include <asm/processor.h>
77 #include <ppc4xx.h>
78 #include <commproc.h>
79 #include <405gp_enet.h>
80 #include <405_mal.h>
81 #include <miiphy.h>
82 #include <net.h>
83 #include <malloc.h>
84 #include "vecnum.h"
85
86 #if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
87
88 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
89 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
90
91 #define NUM_TX_BUFF 1
92 /* AS.HARNOIS
93 * Use PKTBUFSRX (include/net.h) instead of setting NUM_RX_BUFF again
94 * These both variables are used to define the same thing!
95 * #define NUM_RX_BUFF 4
96 */
97 #define NUM_RX_BUFF PKTBUFSRX
98
99 /* Ethernet Transmit and Receive Buffers */
100 /* AS.HARNOIS
101 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
102 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
103 */
104 #define ENET_MAX_MTU PKTSIZE
105 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
106
107 static char *txbuf_ptr;
108
109 /* define the number of channels implemented */
110 #define EMAC_RXCHL 1
111 #define EMAC_TXCHL 1
112
113 /*-----------------------------------------------------------------------------+
114 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
115 * Interrupt Controller).
116 *-----------------------------------------------------------------------------*/
117 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
118 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
119 #define EMAC_UIC_DEF UIC_ENET
120
121 /*-----------------------------------------------------------------------------+
122 * Global variables. TX and RX descriptors and buffers.
123 *-----------------------------------------------------------------------------*/
124 static volatile mal_desc_t *tx;
125 static volatile mal_desc_t *rx;
126 static mal_desc_t *alloc_tx_buf = NULL;
127 static mal_desc_t *alloc_rx_buf = NULL;
128
129 /* IER globals */
130 static unsigned long emac_ier;
131 static unsigned long mal_ier;
132
133
134 /* Statistic Areas */
135 #define MAX_ERR_LOG 10
136 struct emac_stats {
137 int data_len_err;
138 int rx_frames;
139 int rx;
140 int rx_prot_err;
141 };
142
143 static struct stats { /* Statistic Block */
144 struct emac_stats emac;
145 int int_err;
146 short tx_err_log[MAX_ERR_LOG];
147 short rx_err_log[MAX_ERR_LOG];
148 } stats;
149
150 static int first_init = 0;
151
152 static int tx_err_index = 0; /* Transmit Error Index for tx_err_log */
153 static int rx_err_index = 0; /* Receive Error Index for rx_err_log */
154
155 static int rx_slot = 0; /* MAL Receive Slot */
156 static int rx_i_index = 0; /* Receive Interrupt Queue Index */
157 static int rx_u_index = 0; /* Receive User Queue Index */
158 static int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
159
160 static int tx_slot = 0; /* MAL Transmit Slot */
161 static int tx_i_index = 0; /* Transmit Interrupt Queue Index */
162 static int tx_u_index = 0; /* Transmit User Queue Index */
163 static int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
164
165 #undef INFO_405_ENET
166 #ifdef INFO_405_ENET
167 static int packetSent = 0;
168 static int packetReceived = 0;
169 static int packetHandled = 0;
170 #endif
171
172 static char emac_hwd_addr[ENET_ADDR_LENGTH];
173
174 static bd_t *bis_save = NULL; /* for eth_init upon mal error */
175
176 static int is_receiving = 0; /* sync with eth interrupt */
177 static int print_speed = 1; /* print speed message upon start */
178
179 /*-----------------------------------------------------------------------------+
180 * Prototypes and externals.
181 *-----------------------------------------------------------------------------*/
182 static void enet_rcv (unsigned long malisr);
183 static int enetInt(void);
184 static void mal_err (unsigned long isr, unsigned long uic, unsigned long mal_def,
185 unsigned long mal_errr);
186 static void emac_err (unsigned long isr);
187
188 static void ppc_4xx_eth_halt (struct eth_device *dev)
189 {
190 mtdcr (malier, 0x00000000); /* disable mal interrupts */
191 out32 (EMAC_IER, 0x00000000); /* disable emac interrupts */
192
193 /* 1st reset MAL */
194 mtdcr (malmcr, MAL_CR_MMSR);
195
196 /* wait for reset */
197 while (mfdcr (malmcr) & MAL_CR_MMSR) {
198 };
199
200 /* EMAC RESET */
201 out32 (EMAC_M0, EMAC_M0_SRST);
202
203 print_speed = 1; /* print speed message again next time */
204 }
205
206
207 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
208 {
209 int i;
210 unsigned long reg;
211 unsigned long msr;
212 unsigned long speed;
213 unsigned long duplex;
214 unsigned mode_reg;
215 unsigned short reg_short;
216
217 msr = mfmsr ();
218 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
219
220 #ifdef INFO_405_ENET
221 /* AS.HARNOIS
222 * We should have :
223 * packetHandled <= packetReceived <= packetHandled+PKTBUFSRX
224 * In the most cases packetHandled = packetReceived, but it
225 * is possible that new packets (without relationship with
226 * current transfer) have got the time to arrived before
227 * netloop calls eth_halt
228 */
229 printf ("About preceeding transfer:\n"
230 "- Sent packet number %d\n"
231 "- Received packet number %d\n"
232 "- Handled packet number %d\n",
233 packetSent, packetReceived, packetHandled);
234 packetSent = 0;
235 packetReceived = 0;
236 packetHandled = 0;
237 #endif
238
239 /* MAL RESET */
240 mtdcr (malmcr, MAL_CR_MMSR);
241 /* wait for reset */
242 while (mfdcr (malmcr) & MAL_CR_MMSR) {
243 };
244
245 tx_err_index = 0; /* Transmit Error Index for tx_err_log */
246 rx_err_index = 0; /* Receive Error Index for rx_err_log */
247
248 rx_slot = 0; /* MAL Receive Slot */
249 rx_i_index = 0; /* Receive Interrupt Queue Index */
250 rx_u_index = 0; /* Receive User Queue Index */
251
252 tx_slot = 0; /* MAL Transmit Slot */
253 tx_i_index = 0; /* Transmit Interrupt Queue Index */
254 tx_u_index = 0; /* Transmit User Queue Index */
255
256 #if defined(CONFIG_440)
257 /* set RMII mode */
258 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
259 #endif /* CONFIG_440 */
260
261 /* EMAC RESET */
262 out32 (EMAC_M0, EMAC_M0_SRST);
263
264 /* wait for PHY to complete auto negotiation */
265 reg_short = 0;
266 #ifndef CONFIG_CS8952_PHY
267 miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, &reg_short);
268
269 /*
270 * Wait if PHY is able of autonegotiation and autonegotiation is not complete
271 */
272 if ((reg_short & PHY_BMSR_AUTN_ABLE)
273 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
274 puts ("Waiting for PHY auto negotiation to complete");
275 i = 0;
276 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
277 /*
278 * Timeout reached ?
279 */
280 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
281 puts (" TIMEOUT !\n");
282 break;
283 }
284
285 if ((i++ % 1000) == 0)
286 putc ('.');
287 udelay (1000); /* 1 ms */
288 miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, &reg_short);
289 }
290 puts (" done\n");
291 udelay (500000); /* another 500 ms (results in faster booting) */
292 }
293 #endif
294 speed = miiphy_speed (CONFIG_PHY_ADDR);
295 duplex = miiphy_duplex (CONFIG_PHY_ADDR);
296 if (print_speed) {
297 print_speed = 0;
298 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
299 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
300 }
301
302 /* set the Mal configuration reg */
303 #if defined(CONFIG_440)
304 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
305 if( get_pvr() == PVR_440GP_RB )
306 mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
307 else
308 #else
309 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
310 #endif
311
312 /* Free "old" buffers */
313 if (alloc_tx_buf) free(alloc_tx_buf);
314 if (alloc_rx_buf) free(alloc_rx_buf);
315
316 /*
317 * Malloc MAL buffer desciptors, make sure they are
318 * aligned on cache line boundary size
319 * (401/403/IOP480 = 16, 405 = 32)
320 * and doesn't cross cache block boundaries.
321 */
322 alloc_tx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_TX_BUFF) +
323 ((2 * CFG_CACHELINE_SIZE) - 2));
324 if (((int)alloc_tx_buf & CACHELINE_MASK) != 0) {
325 tx = (mal_desc_t *)((int)alloc_tx_buf + CFG_CACHELINE_SIZE -
326 ((int)alloc_tx_buf & CACHELINE_MASK));
327 } else {
328 tx = alloc_tx_buf;
329 }
330
331 alloc_rx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_RX_BUFF) +
332 ((2 * CFG_CACHELINE_SIZE) - 2));
333 if (((int)alloc_rx_buf & CACHELINE_MASK) != 0) {
334 rx = (mal_desc_t *)((int)alloc_rx_buf + CFG_CACHELINE_SIZE -
335 ((int)alloc_rx_buf & CACHELINE_MASK));
336 } else {
337 rx = alloc_rx_buf;
338 }
339
340 for (i = 0; i < NUM_TX_BUFF; i++) {
341 tx[i].ctrl = 0;
342 tx[i].data_len = 0;
343 if (first_init == 0)
344 txbuf_ptr = (char *) malloc (ENET_MAX_MTU_ALIGNED);
345 tx[i].data_ptr = txbuf_ptr;
346 if ((NUM_TX_BUFF - 1) == i)
347 tx[i].ctrl |= MAL_TX_CTRL_WRAP;
348 tx_run[i] = -1;
349 #if 0
350 printf ("TX_BUFF %d @ 0x%08lx\n", i, (ulong) tx[i].data_ptr);
351 #endif
352 }
353
354 for (i = 0; i < NUM_RX_BUFF; i++) {
355 rx[i].ctrl = 0;
356 rx[i].data_len = 0;
357 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
358 rx[i].data_ptr = (char *) NetRxPackets[i];
359 if ((NUM_RX_BUFF - 1) == i)
360 rx[i].ctrl |= MAL_RX_CTRL_WRAP;
361 rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
362 rx_ready[i] = -1;
363 #if 0
364 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
365 #endif
366 }
367
368 memcpy (emac_hwd_addr, bis->bi_enetaddr, ENET_ADDR_LENGTH);
369
370 reg = 0x00000000;
371
372 reg |= emac_hwd_addr[0]; /* set high address */
373 reg = reg << 8;
374 reg |= emac_hwd_addr[1];
375
376 out32 (EMAC_IAH, reg);
377
378 reg = 0x00000000;
379 reg |= emac_hwd_addr[2]; /* set low address */
380 reg = reg << 8;
381 reg |= emac_hwd_addr[3];
382 reg = reg << 8;
383 reg |= emac_hwd_addr[4];
384 reg = reg << 8;
385 reg |= emac_hwd_addr[5];
386
387 out32 (EMAC_IAL, reg);
388
389 /* setup MAL tx & rx channel pointers */
390 mtdcr (maltxctp0r, tx);
391 mtdcr (malrxctp0r, rx);
392
393 /* Reset transmit and receive channels */
394 mtdcr (malrxcarr, 0x80000000); /* 2 channels */
395 mtdcr (maltxcarr, 0x80000000); /* 2 channels */
396
397 /* Enable MAL transmit and receive channels */
398 mtdcr (maltxcasr, 0x80000000); /* 1 channel */
399 mtdcr (malrxcasr, 0x80000000); /* 1 channel */
400
401 /* set RX buffer size */
402 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
403
404 /* set transmit enable & receive enable */
405 out32 (EMAC_M0, EMAC_M0_TXE | EMAC_M0_RXE);
406
407 /* set receive fifo to 4k and tx fifo to 2k */
408 mode_reg = EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
409
410 /* set speed */
411 if (speed == _100BASET)
412 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
413 else
414 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
415 if (duplex == FULL)
416 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
417
418 out32 (EMAC_M1, mode_reg);
419
420 #if defined(CONFIG_440)
421 /* set speed in the ZMII bridge */
422 if (speed == _100BASET)
423 out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
424 else
425 out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
426 #endif
427
428 /* Enable broadcast and indvidual address */
429 out32 (EMAC_RXM, EMAC_RMR_BAE | EMAC_RMR_IAE
430 /*| EMAC_RMR_ARRP| EMAC_RMR_SFCS | EMAC_RMR_SP */ );
431
432 /* we probably need to set the tx mode1 reg? maybe at tx time */
433
434 /* set transmit request threshold register */
435 out32 (EMAC_TRTR, 0x18000000); /* 256 byte threshold */
436
437 /* set receive low/high water mark register */
438 #if defined(CONFIG_440)
439 /* 440GP has a 64 byte burst length */
440 out32 (EMAC_RX_HI_LO_WMARK, 0x80009000);
441 out32 (EMAC_TXM1, 0xf8640000);
442 #else /* CONFIG_440 */
443 /* 405s have a 16 byte burst length */
444 out32 (EMAC_RX_HI_LO_WMARK, 0x0f002000);
445 #endif /* CONFIG_440 */
446
447 /* Frame gap set */
448 out32 (EMAC_I_FRAME_GAP_REG, 0x00000008);
449
450 if (first_init == 0) {
451 /*
452 * Connect interrupt service routines
453 */
454 irq_install_handler (VECNUM_EWU0, (interrupt_handler_t *) enetInt, NULL);
455 irq_install_handler (VECNUM_MS, (interrupt_handler_t *) enetInt, NULL);
456 irq_install_handler (VECNUM_MTE, (interrupt_handler_t *) enetInt, NULL);
457 irq_install_handler (VECNUM_MRE, (interrupt_handler_t *) enetInt, NULL);
458 irq_install_handler (VECNUM_TXDE, (interrupt_handler_t *) enetInt, NULL);
459 irq_install_handler (VECNUM_RXDE, (interrupt_handler_t *) enetInt, NULL);
460 irq_install_handler (VECNUM_ETH0, (interrupt_handler_t *) enetInt, NULL);
461 }
462
463 /* set up interrupt handler */
464 /* setup interrupt controler to take interrupts from the MAL &
465 EMAC */
466 mtdcr (uicsr, 0xffffffff); /* clear pending interrupts */
467 mtdcr (uicer, mfdcr (uicer) | MAL_UIC_DEF | EMAC_UIC_DEF);
468
469 /* set the MAL IER ??? names may change with new spec ??? */
470 mal_ier = MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | MAL_IER_OPBE |
471 MAL_IER_PLBE;
472 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
473 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
474 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
475 mtdcr (malier, mal_ier);
476
477 /* Set EMAC IER */
478 emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
479 EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
480 if (speed == _100BASET)
481 emac_ier = emac_ier | EMAC_ISR_SYE;
482
483 out32 (EMAC_ISR, 0xffffffff); /* clear pending interrupts */
484 out32 (EMAC_IER, emac_ier);
485
486 mtmsr (msr); /* enable interrupts again */
487
488 bis_save = bis;
489 first_init = 1;
490
491 return (1);
492 }
493
494
495 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, int len)
496 {
497 struct enet_frame *ef_ptr;
498 ulong time_start, time_now;
499 unsigned long temp_txm0;
500
501 ef_ptr = (struct enet_frame *) ptr;
502
503 /*-----------------------------------------------------------------------+
504 * Copy in our address into the frame.
505 *-----------------------------------------------------------------------*/
506 (void) memcpy (ef_ptr->source_addr, emac_hwd_addr, ENET_ADDR_LENGTH);
507
508 /*-----------------------------------------------------------------------+
509 * If frame is too long or too short, modify length.
510 *-----------------------------------------------------------------------*/
511 if (len > ENET_MAX_MTU)
512 len = ENET_MAX_MTU;
513
514 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
515 memcpy ((void *) txbuf_ptr, (const void *) ptr, len);
516
517 /*-----------------------------------------------------------------------+
518 * set TX Buffer busy, and send it
519 *-----------------------------------------------------------------------*/
520 tx[tx_slot].ctrl = (MAL_TX_CTRL_LAST |
521 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
522 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
523 if ((NUM_TX_BUFF - 1) == tx_slot)
524 tx[tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
525
526 tx[tx_slot].data_len = (short) len;
527 tx[tx_slot].ctrl |= MAL_TX_CTRL_READY;
528
529 __asm__ volatile ("eieio");
530 out32 (EMAC_TXM0, in32 (EMAC_TXM0) | EMAC_TXM0_GNP0);
531 #ifdef INFO_405_ENET
532 packetSent++;
533 #endif
534
535 /*-----------------------------------------------------------------------+
536 * poll unitl the packet is sent and then make sure it is OK
537 *-----------------------------------------------------------------------*/
538 time_start = get_timer (0);
539 while (1) {
540 temp_txm0 = in32 (EMAC_TXM0);
541 /* loop until either TINT turns on or 3 seconds elapse */
542 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
543 /* transmit is done, so now check for errors
544 * If there is an error, an interrupt should
545 * happen when we return
546 */
547 time_now = get_timer (0);
548 if ((time_now - time_start) > 3000) {
549 return (-1);
550 }
551 } else {
552 return (len);
553 }
554 }
555 }
556
557
558 #if defined(CONFIG_440)
559 /*-----------------------------------------------------------------------------+
560 | EnetInt.
561 | EnetInt is the interrupt handler. It will determine the
562 | cause of the interrupt and call the apporpriate servive
563 | routine.
564 +-----------------------------------------------------------------------------*/
565 int enetInt ()
566 {
567 int serviced;
568 int rc = -1; /* default to not us */
569 unsigned long mal_isr;
570 unsigned long emac_isr = 0;
571 unsigned long mal_rx_eob;
572 unsigned long my_uic0msr, my_uic1msr;
573
574 /* enter loop that stays in interrupt code until nothing to service */
575 do {
576 serviced = 0;
577
578 my_uic0msr = mfdcr (uic0msr);
579 my_uic1msr = mfdcr (uic1msr);
580
581 if (!(my_uic0msr & UIC_MRE)
582 && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
583 /* not for us */
584 return (rc);
585 }
586
587 /* get and clear controller status interrupts */
588 /* look at Mal and EMAC interrupts */
589 if ((my_uic0msr & UIC_MRE)
590 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
591 /* we have a MAL interrupt */
592 mal_isr = mfdcr (malesr);
593 /* look for mal error */
594 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
595 mal_err (mal_isr, my_uic0msr, MAL_UIC_DEF, MAL_UIC_ERR);
596 serviced = 1;
597 rc = 0;
598 }
599 }
600 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
601 emac_isr = in32 (EMAC_ISR);
602 if ((emac_ier & emac_isr) != 0) {
603 emac_err (emac_isr);
604 serviced = 1;
605 rc = 0;
606 }
607 }
608 if ((emac_ier & emac_isr)
609 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
610 mtdcr (uic0sr, UIC_MRE); /* Clear */
611 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
612 return (rc); /* we had errors so get out */
613 }
614
615 /* handle MAL RX EOB interupt from a receive */
616 /* check for EOB on valid channels */
617 if (my_uic0msr & UIC_MRE) {
618 mal_rx_eob = mfdcr (malrxeobisr);
619 if ((mal_rx_eob & 0x80000000) != 0) { /* call emac routine for channel 0 */
620 /* clear EOB
621 mtdcr(malrxeobisr, mal_rx_eob); */
622 enet_rcv (emac_isr);
623 /* indicate that we serviced an interrupt */
624 serviced = 1;
625 rc = 0;
626 }
627 }
628 mtdcr (uic0sr, UIC_MRE); /* Clear */
629 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
630 } while (serviced);
631
632 return (rc);
633 }
634 #else /* CONFIG_440 */
635 /*-----------------------------------------------------------------------------+
636 * EnetInt.
637 * EnetInt is the interrupt handler. It will determine the
638 * cause of the interrupt and call the apporpriate servive
639 * routine.
640 *-----------------------------------------------------------------------------*/
641 int enetInt ()
642 {
643 int serviced;
644 int rc = -1; /* default to not us */
645 unsigned long mal_isr;
646 unsigned long emac_isr = 0;
647 unsigned long mal_rx_eob;
648 unsigned long my_uicmsr;
649
650 /* enter loop that stays in interrupt code until nothing to service */
651 do {
652 serviced = 0;
653
654 my_uicmsr = mfdcr (uicmsr);
655 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
656 return (rc);
657 }
658
659
660 /* get and clear controller status interrupts */
661 /* look at Mal and EMAC interrupts */
662 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
663 mal_isr = mfdcr (malesr);
664 /* look for mal error */
665 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
666 mal_err (mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
667 serviced = 1;
668 rc = 0;
669 }
670 }
671 if ((EMAC_UIC_DEF & my_uicmsr) != 0) { /* look for EMAC errors */
672 emac_isr = in32 (EMAC_ISR);
673 if ((emac_ier & emac_isr) != 0) {
674 emac_err (emac_isr);
675 serviced = 1;
676 rc = 0;
677 }
678 }
679 if (((emac_ier & emac_isr) != 0) | ((MAL_UIC_ERR & my_uicmsr) != 0)) {
680 mtdcr (uicsr, MAL_UIC_DEF | EMAC_UIC_DEF); /* Clear */
681 return (rc); /* we had errors so get out */
682 }
683
684
685 /* handle MAL RX EOB interupt from a receive */
686 /* check for EOB on valid channels */
687 if ((my_uicmsr & UIC_MAL_RXEOB) != 0) {
688 mal_rx_eob = mfdcr (malrxeobisr);
689 if ((mal_rx_eob & 0x80000000) != 0) { /* call emac routine for channel 0 */
690 /* clear EOB
691 mtdcr(malrxeobisr, mal_rx_eob); */
692 enet_rcv (emac_isr);
693 /* indicate that we serviced an interrupt */
694 serviced = 1;
695 rc = 0;
696 }
697 }
698 mtdcr (uicsr, MAL_UIC_DEF | EMAC_UIC_DEF); /* Clear */
699 }
700 while (serviced);
701
702 return (rc);
703 }
704 #endif /* CONFIG_440 */
705
706 /*-----------------------------------------------------------------------------+
707 * MAL Error Routine
708 *-----------------------------------------------------------------------------*/
709 static void mal_err (unsigned long isr, unsigned long uic, unsigned long maldef,
710 unsigned long mal_errr)
711 {
712 mtdcr (malesr, isr); /* clear interrupt */
713
714 /* clear DE interrupt */
715 mtdcr (maltxdeir, 0xC0000000);
716 mtdcr (malrxdeir, 0x80000000);
717
718 #ifdef INFO_405_ENET
719 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n",
720 isr, uic, maldef, mal_errr);
721 #else
722 #if 0
723 /*
724 * MAL error is RX DE error (out of rx buffers)! This is OK here, upon
725 * many incoming packets with only 4 rx buffers.
726 */
727 printf ("M"); /* just to see something upon mal error */
728 #endif
729 #endif
730
731 eth_init (bis_save); /* start again... */
732 }
733
734 /*-----------------------------------------------------------------------------+
735 * EMAC Error Routine
736 *-----------------------------------------------------------------------------*/
737 static void emac_err (unsigned long isr)
738 {
739 printf ("EMAC error occured.... ISR = %lx\n", isr);
740 out32 (EMAC_ISR, isr);
741 }
742
743 /*-----------------------------------------------------------------------------+
744 * enet_rcv() handles the ethernet receive data
745 *-----------------------------------------------------------------------------*/
746 static void enet_rcv (unsigned long malisr)
747 {
748 struct enet_frame *ef_ptr;
749 unsigned long data_len;
750 unsigned long rx_eob_isr;
751
752 int handled = 0;
753 int i;
754 int loop_count = 0;
755
756 rx_eob_isr = mfdcr (malrxeobisr);
757 if ((0x80000000 >> (EMAC_RXCHL - 1)) & rx_eob_isr) {
758 /* clear EOB */
759 mtdcr (malrxeobisr, rx_eob_isr);
760
761 /* EMAC RX done */
762 while (1) { /* do all */
763 i = rx_slot;
764
765 if ((MAL_RX_CTRL_EMPTY & rx[i].ctrl)
766 || (loop_count >= NUM_RX_BUFF))
767 break;
768 loop_count++;
769 rx_slot++;
770 if (NUM_RX_BUFF == rx_slot)
771 rx_slot = 0;
772 handled++;
773 data_len = (unsigned long) rx[i].data_len; /* Get len */
774 if (data_len) {
775 if (data_len > ENET_MAX_MTU) /* Check len */
776 data_len = 0;
777 else {
778 if (EMAC_RX_ERRORS & rx[i].ctrl) { /* Check Errors */
779 data_len = 0;
780 stats.rx_err_log[rx_err_index] = rx[i].ctrl;
781 rx_err_index++;
782 if (rx_err_index == MAX_ERR_LOG)
783 rx_err_index = 0;
784 } /* emac_erros */
785 } /* data_len < max mtu */
786 } /* if data_len */
787 if (!data_len) { /* no data */
788 rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
789
790 stats.emac.data_len_err++; /* Error at Rx */
791 }
792
793 /* !data_len */
794 /* AS.HARNOIS */
795 /* Check if user has already eaten buffer */
796 /* if not => ERROR */
797 else if (rx_ready[rx_i_index] != -1) {
798 if (is_receiving)
799 printf ("ERROR : Receive buffers are full!\n");
800 break;
801 } else {
802 stats.emac.rx_frames++;
803 stats.emac.rx += data_len;
804 ef_ptr = (struct enet_frame *) rx[i].data_ptr;
805 #ifdef INFO_405_ENET
806 packetReceived++;
807 #endif
808 /* AS.HARNOIS
809 * use ring buffer
810 */
811 rx_ready[rx_i_index] = i;
812 rx_i_index++;
813 if (NUM_RX_BUFF == rx_i_index)
814 rx_i_index = 0;
815
816 /* printf("X"); /|* test-only *|/ */
817
818 /* AS.HARNOIS
819 * free receive buffer only when
820 * buffer has been handled (eth_rx)
821 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
822 */
823 } /* if data_len */
824 } /* while */
825 } /* if EMACK_RXCHL */
826 }
827
828
829 static int ppc_4xx_eth_rx (struct eth_device *dev)
830 {
831 int length;
832 int user_index;
833 unsigned long msr;
834
835 is_receiving = 1; /* tell driver */
836
837 for (;;) {
838 /* AS.HARNOIS
839 * use ring buffer and
840 * get index from rx buffer desciptor queue
841 */
842 user_index = rx_ready[rx_u_index];
843 if (user_index == -1) {
844 length = -1;
845 break; /* nothing received - leave for() loop */
846 }
847
848 msr = mfmsr ();
849 mtmsr (msr & ~(MSR_EE));
850
851 length = rx[user_index].data_len;
852
853 /* Pass the packet up to the protocol layers. */
854 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
855 /* NetReceive(NetRxPackets[i], length); */
856 NetReceive (NetRxPackets[user_index], length - 4);
857 /* Free Recv Buffer */
858 rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
859 /* Free rx buffer descriptor queue */
860 rx_ready[rx_u_index] = -1;
861 rx_u_index++;
862 if (NUM_RX_BUFF == rx_u_index)
863 rx_u_index = 0;
864
865 #ifdef INFO_405_ENET
866 packetHandled++;
867 #endif
868
869 mtmsr (msr); /* Enable IRQ's */
870 }
871
872 is_receiving = 0; /* tell driver */
873
874 return length;
875 }
876
877 #if defined(CONFIG_NET_MULTI)
878 int ppc_4xx_eth_initialize(bd_t *bis)
879 {
880 struct eth_device *dev;
881 int eth_num = 0;
882
883 dev = malloc (sizeof *dev);
884 if (dev == NULL) {
885 printf(__FUNCTION__ ": Cannot allocate eth_device\n");
886 return (-1);
887 }
888
889 sprintf(dev->name, "ppc_4xx_eth%d", eth_num);
890 dev->priv = (void *) eth_num;
891 dev->init = ppc_4xx_eth_init;
892 dev->halt = ppc_4xx_eth_halt;
893 dev->send = ppc_4xx_eth_send;
894 dev->recv = ppc_4xx_eth_rx;
895
896 eth_register (dev);
897 }
898 #else /* !defined(CONFIG_NET_MULTI) */
899 void eth_halt (void)
900 {
901 ppc_4xx_eth_halt(NULL);
902 }
903
904 int eth_init (bd_t *bis)
905 {
906 return (ppc_4xx_eth_init(NULL, bis));
907 }
908 int eth_send(volatile void *packet, int length)
909 {
910 return (ppc_4xx_eth_send(NULL, packet, length));
911 }
912
913 int eth_rx(void)
914 {
915 return (ppc_4xx_eth_rx(NULL));
916 }
917 #endif /* !defined(CONFIG_NET_MULTI) */
918
919 #endif /* CONFIG_405GP */
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