cpu/ppc4xx/405gp_pci.c

   1 /*-----------------------------------------------------------------------------+
   2  *
   3  *       This source code has been made available to you by IBM on an AS-IS
   4  *       basis.  Anyone receiving this source is licensed under IBM
   5  *       copyrights to use it in any way he or she deems fit, including
   6  *       copying it, modifying it, compiling it, and redistributing it either
   7  *       with or without modifications.  No license under IBM patents or
   8  *       patent applications is to be implied by the copyright license.
   9  *
  10  *       Any user of this software should understand that IBM cannot provide
  11  *       technical support for this software and will not be responsible for
  12  *       any consequences resulting from the use of this software.
  13  *
  14  *       Any person who transfers this source code or any derivative work
  15  *       must include the IBM copyright notice, this paragraph, and the
  16  *       preceding two paragraphs in the transferred software.
  17  *
  18  *       COPYRIGHT   I B M   CORPORATION 1995
  19  *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  20  *-----------------------------------------------------------------------------*/
  21 /*----------------------------------------------------------------------------+
  22  *
  23  *  File Name:   405gp_pci.c
  24  *
  25  *  Function:    Initialization code for the 405GP PCI Configuration regs.
  26  *
  27  *  Author:      Mark Game
  28  *
  29  *  Change Activity-
  30  *
  31  *  Date        Description of Change                                       BY
  32  *  ---------   ---------------------                                       ---
  33  *  09-Sep-98   Created                                                     MCG
  34  *  02-Nov-98   Removed External arbiter selected message                   JWB
  35  *  27-Nov-98   Zero out PTMBAR2 and disable in PTM2MS                      JWB
  36  *  04-Jan-99   Zero out other unused PMM and PTM regs. Change bus scan     MCG
  37  *              from (0 to n) to (1 to n).
  38  *  17-May-99   Port to Walnut                                              JWB
  39  *  17-Jun-99   Updated for VGA support                                     JWB
  40  *  21-Jun-99   Updated to allow SRAM region to be a target from PCI bus    JWB
  41  *  19-Jul-99   Updated for 405GP pass 1 errata #26 (Low PCI subsequent     MCG
  42  *              target latency timer values are not supported).
  43  *              Should be fixed in pass 2.
  44  *  09-Sep-99   Removed use of PTM2 since the SRAM region no longer needs   JWB
  45  *              to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
  46  *  10-Dec-99   Updated PCI_Write_CFG_Reg for pass2 errata #6               JWB
  47  *  11-Jan-00   Ensure PMMxMAs disabled before setting PMMxLAs. This is not
  48  *              really required after a reset since PMMxMAs are already
  49  *              disabled but is a good practice nonetheless.                JWB
  50  *  12-Jun-01   stefan.roese@esd-electronics.com
  51  *              - PCI host/adapter handling reworked
  52  *  09-Jul-01   stefan.roese@esd-electronics.com
  53  *              - PCI host now configures from device 0 (not 1) to max_dev,
  54  *                (host configures itself)
  55  *              - On CPCI-405 pci base address and size is generated from
  56  *                SDRAM and FLASH size (CFG regs not used anymore)
  57  *              - Some minor changes for CPCI-405-A (adapter version)
  58  *  14-Sep-01   stefan.roese@esd-electronics.com
  59  *              - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
  60  *  28-Sep-01   stefan.roese@esd-electronics.com
  61  *              - Changed pci master configuration for linux compatibility
  62  *                (no need for bios_fixup() anymore)
  63  *  26-Feb-02   stefan.roese@esd-electronics.com
  64  *              - Bug fixed in pci configuration (Andrew May)
  65  *              - Removed pci class code init for CPCI405 board
  66  *  15-May-02   stefan.roese@esd-electronics.com
  67  *              - New vga device handling
  68  *  29-May-02   stefan.roese@esd-electronics.com
  69  *              - PCI class code init added (if defined)
  70  *----------------------------------------------------------------------------*/
  71
  72 #include <common.h>
  73 #include <command.h>
  74 #if !defined(CONFIG_440)
  75 #include <405gp_pci.h>
  76 #endif
  77 #include <asm/processor.h>
  78 #include <pci.h>
  79
  80 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
  81
  82 #ifdef CONFIG_PCI
  83
  84 /*#define DEBUG*/
  85
  86 /*-----------------------------------------------------------------------------+
  87  * pci_init.  Initializes the 405GP PCI Configuration regs.
  88  *-----------------------------------------------------------------------------*/
  89 void pci_405gp_init(struct pci_controller *hose)
  90 {
  91         DECLARE_GLOBAL_DATA_PTR;
  92
  93         int i, reg_num = 0;
  94         bd_t *bd = gd->bd;
  95
  96         unsigned short temp_short;
  97         unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
  98 #if defined(CONFIG_CPCI405)
  99         unsigned long ptmla[2]    = {bd->bi_memstart, bd->bi_flashstart};
 100         unsigned long ptmms[2]    = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1};
 101 #else
 102         unsigned long ptmla[2]    = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
 103         unsigned long ptmms[2]    = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
 104 #endif
 105 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
 106         unsigned long pmmla[3]    = {0x80000000, 0xA0000000, 0};
 107         unsigned long pmmma[3]    = {0xE0000001, 0xE0000001, 0};
 108         unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
 109         unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
 110 #else
 111         unsigned long pmmla[3]    = {0x80000000, 0,0};
 112         unsigned long pmmma[3]    = {0xC0000001, 0,0};
 113         unsigned long pmmpcila[3] = {0x80000000, 0,0};
 114         unsigned long pmmpciha[3] = {0x00000000, 0,0};
 115 #endif
 116
 117         /*
 118          * Register the hose
 119          */
 120         hose->first_busno = 0;
 121         hose->last_busno = 0xff;
 122
 123         /* ISA/PCI I/O space */
 124         pci_set_region(hose->regions + reg_num++,
 125                        MIN_PCI_PCI_IOADDR,
 126                        MIN_PLB_PCI_IOADDR,
 127                        0x10000,
 128                        PCI_REGION_IO);
 129
 130         /* PCI I/O space */
 131         pci_set_region(hose->regions + reg_num++,
 132                        0x00800000,
 133                        0xe8800000,
 134                        0x03800000,
 135                        PCI_REGION_IO);
 136
 137         reg_num = 2;
 138
 139         /* Memory spaces */
 140         for (i=0; i<2; i++)
 141                 if (ptmms[i] & 1)
 142                 {
 143                         if (!i) hose->pci_fb = hose->regions + reg_num;
 144
 145                         pci_set_region(hose->regions + reg_num++,
 146                                        ptmpcila[i], ptmla[i],
 147                                        ~(ptmms[i] & 0xfffff000) + 1,
 148                                        PCI_REGION_MEM |
 149                                        PCI_REGION_MEMORY);
 150                 }
 151
 152         /* PCI memory spaces */
 153         for (i=0; i<3; i++)
 154                 if (pmmma[i] & 1)
 155                 {
 156                         pci_set_region(hose->regions + reg_num++,
 157                                        pmmpcila[i], pmmla[i],
 158                                        ~(pmmma[i] & 0xfffff000) + 1,
 159                                        PCI_REGION_MEM);
 160                 }
 161
 162         hose->region_count = reg_num;
 163
 164         pci_setup_indirect(hose,
 165                            PCICFGADR,
 166                            PCICFGDATA);
 167
 168         if (hose->pci_fb)
 169                 pciauto_region_init(hose->pci_fb);
 170
 171         pci_register_hose(hose);
 172
 173         /*--------------------------------------------------------------------------+
 174          * 405GP PCI Master configuration.
 175          * Map one 512 MB range of PLB/processor addresses to PCI memory space.
 176          * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
 177          * Use byte reversed out routines to handle endianess.
 178          *--------------------------------------------------------------------------*/
 179         out32r(PMM0MA,    (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
 180         out32r(PMM0LA,    pmmla[0]);
 181         out32r(PMM0PCILA, pmmpcila[0]);
 182         out32r(PMM0PCIHA, pmmpciha[0]);
 183         out32r(PMM0MA,    pmmma[0]);
 184
 185         /*--------------------------------------------------------------------------+
 186          * PMM1 is not used.  Initialize them to zero.
 187          *--------------------------------------------------------------------------*/
 188         out32r(PMM1MA,    (pmmma[1]&~0x1));
 189         out32r(PMM1LA,    pmmla[1]);
 190         out32r(PMM1PCILA, pmmpcila[1]);
 191         out32r(PMM1PCIHA, pmmpciha[1]);
 192         out32r(PMM1MA,    pmmma[1]);
 193
 194         /*--------------------------------------------------------------------------+
 195          * PMM2 is not used.  Initialize them to zero.
 196          *--------------------------------------------------------------------------*/
 197         out32r(PMM2MA,    (pmmma[2]&~0x1));
 198         out32r(PMM2LA,    pmmla[2]);
 199         out32r(PMM2PCILA, pmmpcila[2]);
 200         out32r(PMM2PCIHA, pmmpciha[2]);
 201         out32r(PMM2MA,    pmmma[2]);
 202
 203         /*--------------------------------------------------------------------------+
 204          * 405GP PCI Target configuration.  (PTM1)
 205          * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
 206          *--------------------------------------------------------------------------*/
 207         out32r(PTM1LA,    ptmla[0]);         /* insert address                     */
 208         out32r(PTM1MS,    ptmms[0]);         /* insert size, enable bit is 1       */
 209
 210         /*--------------------------------------------------------------------------+
 211          * 405GP PCI Target configuration.  (PTM2)
 212          *--------------------------------------------------------------------------*/
 213         out32r(PTM2LA, ptmla[1]);            /* insert address                     */
 214         if (ptmms[1] == 0)
 215         {
 216                 out32r(PTM2MS,    0x00000001);   /* set enable bit                     */
 217                 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
 218                 out32r(PTM2MS,    0x00000000);   /* disable                            */
 219         }
 220         else
 221         {
 222                 out32r(PTM2MS, ptmms[1]);        /* insert size, enable bit is 1       */
 223         }
 224
 225         /*
 226          * Insert Subsystem Vendor and Device ID
 227          */
 228         pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID);
 229 #ifdef CONFIG_CPCI405
 230         if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
 231                 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
 232         else
 233                 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2);
 234 #else
 235         pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID);
 236 #endif
 237
 238         /*
 239          * Insert Class-code
 240          */
 241 #ifdef CFG_PCI_CLASSCODE
 242         pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE);
 243 #endif /* CFG_PCI_CLASSCODE */
 244
 245         /*--------------------------------------------------------------------------+
 246          * If PCI speed = 66Mhz, set 66Mhz capable bit.
 247          *--------------------------------------------------------------------------*/
 248         if (bd->bi_pci_busfreq >= 66000000) {
 249                 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
 250                 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
 251         }
 252
 253 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
 254 #if (CONFIG_PCI_HOSE == PCI_HOST_AUTO)
 255         if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
 256 #endif
 257         {
 258                 /*--------------------------------------------------------------------------+
 259                  * Write the 405GP PCI Configuration regs.
 260                  * Enable 405GP to be a master on the PCI bus (PMM).
 261                  * Enable 405GP to act as a PCI memory target (PTM).
 262                  *--------------------------------------------------------------------------*/
 263                 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
 264                 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
 265                                       PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 266         }
 267 #endif
 268
 269         /*
 270          * Set HCE bit (Host Configuration Enabled)
 271          */
 272         pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
 273         pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
 274
 275 #ifdef CONFIG_PCI_PNP
 276         /*--------------------------------------------------------------------------+
 277          * Scan the PCI bus and configure devices found.
 278          *--------------------------------------------------------------------------*/
 279 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
 280         if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
 281 #endif
 282         {
 283 #ifdef CONFIG_PCI_SCAN_SHOW
 284                 printf("PCI:   Bus Dev VenId DevId Class Int\n");
 285 #endif
 286
 287                 hose->last_busno = pci_hose_scan(hose);
 288         }
 289 #endif  /* CONFIG_PCI_PNP */
 290
 291 }
 292
 293 /*
 294  * drivers/pci.c skips every host bridge but the 405GP since it could
 295  * be set as an Adapter.
 296  *
 297  * I (Andrew May) don't know what we should do here, but I don't want
 298  * the auto setup of a PCI device disabling what is done pci_405gp_init
 299  * as has happened before.
 300  */
 301 void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
 302                             struct pci_config_table *entry)
 303 {
 304 #ifdef DEBUG
 305         printf("405gp_setup_bridge\n");
 306 #endif
 307 }
 308
 309 /*
 310  *
 311  */
 312
 313 void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 314 {
 315         unsigned char int_line = 0xff;
 316
 317         /*
 318          * Write pci interrupt line register (cpci405 specific)
 319          */
 320         switch (PCI_DEV(dev) & 0x03)
 321         {
 322         case 0:
 323                 int_line = 27 + 2;
 324                 break;
 325         case 1:
 326                 int_line = 27 + 3;
 327                 break;
 328         case 2:
 329                 int_line = 27 + 0;
 330                 break;
 331         case 3:
 332                 int_line = 27 + 1;
 333                 break;
 334         }
 335
 336         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
 337 }
 338
 339 void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
 340                          struct pci_config_table *entry)
 341 {
 342         unsigned int cmdstat = 0;
 343
 344         pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
 345
 346         /* always enable io space on vga boards */
 347         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
 348         cmdstat |= PCI_COMMAND_IO;
 349         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
 350 }
 351
 352 #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))
 353
 354 /*
 355  *As is these functs get called out of flash Not a horrible
 356  *thing, but something to keep in mind. (no statics?)
 357  */
 358 static struct pci_config_table pci_405gp_config_table[] = {
 359 /*if VendID is 0 it terminates the table search (ie Walnut)*/
 360 #if CFG_PCI_SUBSYS_VENDORID
 361         {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
 362          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
 363 #endif
 364         {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
 365          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
 366
 367         {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
 368          PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
 369
 370         { }
 371 };
 372
 373 static struct pci_controller hose = {
 374         fixup_irq: pci_405gp_fixup_irq,
 375         config_table: pci_405gp_config_table,
 376 };
 377
 378 void pci_init_board(void)
 379 {
 380         /*we want the ptrs to RAM not flash (ie don't use init list)*/
 381         hose.fixup_irq    = pci_405gp_fixup_irq;
 382         hose.config_table = pci_405gp_config_table;
 383         pci_405gp_init(&hose);
 384 }
 385
 386 #endif
 387
 388 #endif /* CONFIG_PCI */
 389
 390 #endif /* CONFIG_405GP */
 391
 392 /*-----------------------------------------------------------------------------+
 393  * CONFIG_440
 394  *-----------------------------------------------------------------------------*/
 395 #if defined(CONFIG_440) && defined(CONFIG_PCI)
 396
 397 static struct pci_controller ppc440_hose = {0};
 398
 399
 400 void pci_440_init (struct pci_controller *hose)
 401 {
 402         int reg_num = 0;
 403         unsigned long strap;
 404
 405         /*--------------------------------------------------------------------------+
 406          * The PCI initialization sequence enable bit must be set ... if not abort
 407      * pci setup since updating the bit requires chip reset.
 408          *--------------------------------------------------------------------------*/
 409     strap = mfdcr(cpc0_strp1);
 410     if( (strap & 0x00040000) == 0 ){
 411         printf("PCI: CPC0_STRP1[PISE] not set.\n");
 412         printf("PCI: Configuration aborted.\n");
 413         return;
 414     }
 415
 416         /*--------------------------------------------------------------------------+
 417          * PCI controller init
 418          *--------------------------------------------------------------------------*/
 419         hose->first_busno = 0;
 420         hose->last_busno = 0xff;
 421
 422         pci_set_region(hose->regions + reg_num++,
 423                        0x00000000,
 424                            PCIX0_IOBASE,
 425                            0x10000,
 426                            PCI_REGION_IO);
 427
 428         pci_set_region(hose->regions + reg_num++,
 429                        CFG_PCI_TARGBASE,
 430                            CFG_PCI_MEMBASE,
 431                            0x10000000,
 432                            PCI_REGION_MEM );
 433         hose->region_count = reg_num;
 434
 435         pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
 436
 437 #if defined(CFG_PCI_PRE_INIT)
 438     /* Let board change/modify hose & do initial checks */
 439     if( pci_pre_init (hose) == 0 ){
 440         printf("PCI: Board-specific initialization failed.\n");
 441         printf("PCI: Configuration aborted.\n");
 442         return;
 443     }
 444 #endif
 445
 446         pci_register_hose( hose );
 447
 448         /*--------------------------------------------------------------------------+
 449          * PCI target init
 450          *--------------------------------------------------------------------------*/
 451 #if defined(CFG_PCI_TARGET_INIT)
 452         pci_target_init(hose);                /* Let board setup pci target */
 453 #else
 454     out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 455     out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
 456     out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
 457 #endif
 458
 459     out32r( PCIX0_BRDGOPT1, 0x10000060 );               /* PLB Rq pri highest   */
 460     out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config   */
 461
 462         /*--------------------------------------------------------------------------+
 463          * PCI master init: default is one 256MB region for PCI memory:
 464          * 0x3_00000000 - 0x3_0FFFFFFF  ==> CFG_PCI_MEMBASE
 465          *--------------------------------------------------------------------------*/
 466 #if defined(CFG_PCI_MASTER_INIT)
 467         pci_master_init(hose);          /* Let board setup pci master */
 468 #else
 469         out32r( PCIX0_POM0SA, 0 ); /* disable */
 470         out32r( PCIX0_POM1SA, 0 ); /* disable */
 471         out32r( PCIX0_POM2SA, 0 ); /* disable */
 472         out32r( PCIX0_POM0LAL, 0x00000000 );
 473         out32r( PCIX0_POM0LAH, 0x00000003 );
 474         out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
 475         out32r( PCIX0_POM0PCIAH, 0x00000000 );
 476         out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
 477     out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
 478 #endif
 479
 480         /*--------------------------------------------------------------------------+
 481          * PCI host configuration -- we don't make any assumptions here ... the
 482      * _board_must_indicate_ what to do -- there's just too many runtime
 483      * scenarios in environments like cPCI, PPMC, etc. to make a determination
 484      * based on hard-coded values or state of arbiter enable.
 485          *--------------------------------------------------------------------------*/
 486     if( is_pci_host(hose) ){
 487 #ifdef CONFIG_PCI_SCAN_SHOW
 488         printf("PCI:   Bus Dev VenId DevId Class Int\n");
 489 #endif
 490         out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
 491         hose->last_busno = pci_hose_scan(hose);
 492     }
 493 }
 494
 495
 496 void pci_init_board(void)
 497 {
 498         pci_440_init (&ppc440_hose);
 499 }
 500
 501 #endif /* CONFIG_440 & CONFIG_PCI */