1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*----------------------------------------------------------------------------+
23 * File Name: 405gp_pci.c
25 * Function: Initialization code for the 405GP PCI Configuration regs.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 09-Sep-98 Created MCG
34 * 02-Nov-98 Removed External arbiter selected message JWB
35 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
36 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
37 * from (0 to n) to (1 to n).
38 * 17-May-99 Port to Walnut JWB
39 * 17-Jun-99 Updated for VGA support JWB
40 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
41 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
42 * target latency timer values are not supported).
43 * Should be fixed in pass 2.
44 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
45 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
46 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
47 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
48 * really required after a reset since PMMxMAs are already
49 * disabled but is a good practice nonetheless. JWB
50 * 12-Jun-01 stefan.roese@esd-electronics.com
51 * - PCI host/adapter handling reworked
52 * 09-Jul-01 stefan.roese@esd-electronics.com
53 * - PCI host now configures from device 0 (not 1) to max_dev,
54 * (host configures itself)
55 * - On CPCI-405 pci base address and size is generated from
56 * SDRAM and FLASH size (CFG regs not used anymore)
57 * - Some minor changes for CPCI-405-A (adapter version)
58 * 14-Sep-01 stefan.roese@esd-electronics.com
59 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
60 * 28-Sep-01 stefan.roese@esd-electronics.com
61 * - Changed pci master configuration for linux compatibility
62 * (no need for bios_fixup() anymore)
63 * 26-Feb-02 stefan.roese@esd-electronics.com
64 * - Bug fixed in pci configuration (Andrew May)
65 * - Removed pci class code init for CPCI405 board
66 * 15-May-02 stefan.roese@esd-electronics.com
67 * - New vga device handling
68 * 29-May-02 stefan.roese@esd-electronics.com
69 * - PCI class code init added (if defined)
70 *----------------------------------------------------------------------------*/
74 #if !defined(CONFIG_440)
75 #include <405gp_pci.h>
77 #include <asm/processor.h>
80 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
84 #if defined(CONFIG_PMC405)
85 ushort
pmc405_pci_subsys_deviceid(void);
90 /*-----------------------------------------------------------------------------+
91 * pci_init. Initializes the 405GP PCI Configuration regs.
92 *-----------------------------------------------------------------------------*/
93 void pci_405gp_init(struct pci_controller
*hose
)
95 DECLARE_GLOBAL_DATA_PTR
;
100 unsigned short temp_short
;
101 unsigned long ptmpcila
[2] = {CFG_PCI_PTM1PCI
, CFG_PCI_PTM2PCI
};
102 #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
103 char *ptmla_str
, *ptmms_str
;
105 unsigned long ptmla
[2] = {CFG_PCI_PTM1LA
, CFG_PCI_PTM2LA
};
106 unsigned long ptmms
[2] = {CFG_PCI_PTM1MS
, CFG_PCI_PTM2MS
};
107 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
108 unsigned long pmmla
[3] = {0x80000000, 0xA0000000, 0};
109 unsigned long pmmma
[3] = {0xE0000001, 0xE0000001, 0};
110 unsigned long pmmpcila
[3] = {0x80000000, 0x00000000, 0};
111 unsigned long pmmpciha
[3] = {0x00000000, 0x00000000, 0};
113 unsigned long pmmla
[3] = {0x80000000, 0,0};
114 unsigned long pmmma
[3] = {0xC0000001, 0,0};
115 unsigned long pmmpcila
[3] = {0x80000000, 0,0};
116 unsigned long pmmpciha
[3] = {0x00000000, 0,0};
118 #ifdef CONFIG_PCI_PNP
119 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
124 #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
125 ptmla_str
= getenv("ptm1la");
126 ptmms_str
= getenv("ptm1ms");
127 if(NULL
!= ptmla_str
&& NULL
!= ptmms_str
) {
128 ptmla
[0] = simple_strtoul (ptmla_str
, NULL
, 16);
129 ptmms
[0] = simple_strtoul (ptmms_str
, NULL
, 16);
132 ptmla_str
= getenv("ptm2la");
133 ptmms_str
= getenv("ptm2ms");
134 if(NULL
!= ptmla_str
&& NULL
!= ptmms_str
) {
135 ptmla
[1] = simple_strtoul (ptmla_str
, NULL
, 16);
136 ptmms
[1] = simple_strtoul (ptmms_str
, NULL
, 16);
143 hose
->first_busno
= 0;
144 hose
->last_busno
= 0xff;
146 /* ISA/PCI I/O space */
147 pci_set_region(hose
->regions
+ reg_num
++,
154 pci_set_region(hose
->regions
+ reg_num
++,
166 if (!i
) hose
->pci_fb
= hose
->regions
+ reg_num
;
168 pci_set_region(hose
->regions
+ reg_num
++,
169 ptmpcila
[i
], ptmla
[i
],
170 ~(ptmms
[i
] & 0xfffff000) + 1,
175 /* PCI memory spaces */
179 pci_set_region(hose
->regions
+ reg_num
++,
180 pmmpcila
[i
], pmmla
[i
],
181 ~(pmmma
[i
] & 0xfffff000) + 1,
185 hose
->region_count
= reg_num
;
187 pci_setup_indirect(hose
,
192 pciauto_region_init(hose
->pci_fb
);
194 pci_register_hose(hose
);
196 /*--------------------------------------------------------------------------+
197 * 405GP PCI Master configuration.
198 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
199 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
200 * Use byte reversed out routines to handle endianess.
201 *--------------------------------------------------------------------------*/
202 out32r(PMM0MA
, (pmmma
[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
203 out32r(PMM0LA
, pmmla
[0]);
204 out32r(PMM0PCILA
, pmmpcila
[0]);
205 out32r(PMM0PCIHA
, pmmpciha
[0]);
206 out32r(PMM0MA
, pmmma
[0]);
208 /*--------------------------------------------------------------------------+
209 * PMM1 is not used. Initialize them to zero.
210 *--------------------------------------------------------------------------*/
211 out32r(PMM1MA
, (pmmma
[1]&~0x1));
212 out32r(PMM1LA
, pmmla
[1]);
213 out32r(PMM1PCILA
, pmmpcila
[1]);
214 out32r(PMM1PCIHA
, pmmpciha
[1]);
215 out32r(PMM1MA
, pmmma
[1]);
217 /*--------------------------------------------------------------------------+
218 * PMM2 is not used. Initialize them to zero.
219 *--------------------------------------------------------------------------*/
220 out32r(PMM2MA
, (pmmma
[2]&~0x1));
221 out32r(PMM2LA
, pmmla
[2]);
222 out32r(PMM2PCILA
, pmmpcila
[2]);
223 out32r(PMM2PCIHA
, pmmpciha
[2]);
224 out32r(PMM2MA
, pmmma
[2]);
226 /*--------------------------------------------------------------------------+
227 * 405GP PCI Target configuration. (PTM1)
228 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
229 *--------------------------------------------------------------------------*/
230 out32r(PTM1LA
, ptmla
[0]); /* insert address */
231 out32r(PTM1MS
, ptmms
[0]); /* insert size, enable bit is 1 */
232 pci_write_config_dword(PCIDEVID_405GP
, PCI_BASE_ADDRESS_1
, ptmpcila
[0]);
234 /*--------------------------------------------------------------------------+
235 * 405GP PCI Target configuration. (PTM2)
236 *--------------------------------------------------------------------------*/
237 out32r(PTM2LA
, ptmla
[1]); /* insert address */
238 pci_write_config_dword(PCIDEVID_405GP
, PCI_BASE_ADDRESS_2
, ptmpcila
[1]);
242 out32r(PTM2MS
, 0x00000001); /* set enable bit */
243 pci_write_config_dword(PCIDEVID_405GP
, PCI_BASE_ADDRESS_2
, 0x00000000);
244 out32r(PTM2MS
, 0x00000000); /* disable */
248 out32r(PTM2MS
, ptmms
[1]); /* insert size, enable bit is 1 */
252 * Insert Subsystem Vendor and Device ID
254 pci_write_config_word(PCIDEVID_405GP
, PCI_SUBSYSTEM_VENDOR_ID
, CFG_PCI_SUBSYS_VENDORID
);
255 #ifdef CONFIG_CPCI405
256 if (mfdcr(strap
) & PSR_PCI_ARBIT_EN
)
257 pci_write_config_word(PCIDEVID_405GP
, PCI_SUBSYSTEM_ID
, CFG_PCI_SUBSYS_DEVICEID
);
259 pci_write_config_word(PCIDEVID_405GP
, PCI_SUBSYSTEM_ID
, CFG_PCI_SUBSYS_DEVICEID2
);
261 pci_write_config_word(PCIDEVID_405GP
, PCI_SUBSYSTEM_ID
, CFG_PCI_SUBSYS_DEVICEID
);
267 #ifdef CFG_PCI_CLASSCODE
268 pci_write_config_word(PCIDEVID_405GP
, PCI_CLASS_SUB_CODE
, CFG_PCI_CLASSCODE
);
269 #endif /* CFG_PCI_CLASSCODE */
271 /*--------------------------------------------------------------------------+
272 * If PCI speed = 66Mhz, set 66Mhz capable bit.
273 *--------------------------------------------------------------------------*/
274 if (bd
->bi_pci_busfreq
>= 66000000) {
275 pci_read_config_word(PCIDEVID_405GP
, PCI_STATUS
, &temp_short
);
276 pci_write_config_word(PCIDEVID_405GP
,PCI_STATUS
,(temp_short
|PCI_STATUS_66MHZ
));
279 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
280 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
281 if ((mfdcr(strap
) & PSR_PCI_ARBIT_EN
) ||
282 (((s
= getenv("pciscan")) != NULL
) && (strcmp(s
, "yes") == 0)))
285 /*--------------------------------------------------------------------------+
286 * Write the 405GP PCI Configuration regs.
287 * Enable 405GP to be a master on the PCI bus (PMM).
288 * Enable 405GP to act as a PCI memory target (PTM).
289 *--------------------------------------------------------------------------*/
290 pci_read_config_word(PCIDEVID_405GP
, PCI_COMMAND
, &temp_short
);
291 pci_write_config_word(PCIDEVID_405GP
, PCI_COMMAND
, temp_short
|
292 PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
);
296 #if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */
297 pci_write_config_word(PCIDEVID_405GP
, PCI_VENDOR_ID
, 0x1014); /* IBM */
301 * Set HCE bit (Host Configuration Enabled)
303 pci_read_config_word(PCIDEVID_405GP
, PCIBRDGOPT2
, &temp_short
);
304 pci_write_config_word(PCIDEVID_405GP
, PCIBRDGOPT2
, (temp_short
| 0x0001));
306 #ifdef CONFIG_PCI_PNP
307 /*--------------------------------------------------------------------------+
308 * Scan the PCI bus and configure devices found.
309 *--------------------------------------------------------------------------*/
310 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
311 if ((mfdcr(strap
) & PSR_PCI_ARBIT_EN
) ||
312 (((s
= getenv("pciscan")) != NULL
) && (strcmp(s
, "yes") == 0)))
315 #ifdef CONFIG_PCI_SCAN_SHOW
316 printf("PCI: Bus Dev VenId DevId Class Int\n");
319 hose
->last_busno
= pci_hose_scan(hose
);
321 #endif /* CONFIG_PCI_PNP */
326 * drivers/pci.c skips every host bridge but the 405GP since it could
327 * be set as an Adapter.
329 * I (Andrew May) don't know what we should do here, but I don't want
330 * the auto setup of a PCI device disabling what is done pci_405gp_init
331 * as has happened before.
333 void pci_405gp_setup_bridge(struct pci_controller
*hose
, pci_dev_t dev
,
334 struct pci_config_table
*entry
)
337 printf("405gp_setup_bridge\n");
345 void pci_405gp_fixup_irq(struct pci_controller
*hose
, pci_dev_t dev
)
347 unsigned char int_line
= 0xff;
350 * Write pci interrupt line register (cpci405 specific)
352 switch (PCI_DEV(dev
) & 0x03)
368 pci_hose_write_config_byte(hose
, dev
, PCI_INTERRUPT_LINE
, int_line
);
371 void pci_405gp_setup_vga(struct pci_controller
*hose
, pci_dev_t dev
,
372 struct pci_config_table
*entry
)
374 unsigned int cmdstat
= 0;
376 pciauto_setup_device(hose
, dev
, 6, hose
->pci_mem
, hose
->pci_prefetch
, hose
->pci_io
);
378 /* always enable io space on vga boards */
379 pci_hose_read_config_dword(hose
, dev
, PCI_COMMAND
, &cmdstat
);
380 cmdstat
|= PCI_COMMAND_IO
;
381 pci_hose_write_config_dword(hose
, dev
, PCI_COMMAND
, cmdstat
);
384 #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))
387 *As is these functs get called out of flash Not a horrible
388 *thing, but something to keep in mind. (no statics?)
390 static struct pci_config_table pci_405gp_config_table
[] = {
391 /*if VendID is 0 it terminates the table search (ie Walnut)*/
392 #ifdef CFG_PCI_SUBSYS_VENDORID
393 {CFG_PCI_SUBSYS_VENDORID
, PCI_ANY_ID
, PCI_CLASS_BRIDGE_HOST
,
394 PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, pci_405gp_setup_bridge
},
396 {PCI_ANY_ID
, PCI_ANY_ID
, PCI_CLASS_DISPLAY_VGA
,
397 PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, pci_405gp_setup_vga
},
399 {PCI_ANY_ID
, PCI_ANY_ID
, PCI_CLASS_NOT_DEFINED_VGA
,
400 PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, pci_405gp_setup_vga
},
405 static struct pci_controller hose
= {
406 fixup_irq
: pci_405gp_fixup_irq
,
407 config_table
: pci_405gp_config_table
,
410 void pci_init_board(void)
412 /*we want the ptrs to RAM not flash (ie don't use init list)*/
413 hose
.fixup_irq
= pci_405gp_fixup_irq
;
414 hose
.config_table
= pci_405gp_config_table
;
415 pci_405gp_init(&hose
);
420 #endif /* CONFIG_PCI */
422 #endif /* CONFIG_405GP */
424 /*-----------------------------------------------------------------------------+
426 *-----------------------------------------------------------------------------*/
427 #if defined(CONFIG_440) && defined(CONFIG_PCI)
429 static struct pci_controller ppc440_hose
= {0};
432 void pci_440_init (struct pci_controller
*hose
)
436 #ifndef CONFIG_DISABLE_PISE_TEST
437 /*--------------------------------------------------------------------------+
438 * The PCI initialization sequence enable bit must be set ... if not abort
439 * pci setup since updating the bit requires chip reset.
440 *--------------------------------------------------------------------------*/
441 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
444 mfsdr(sdr_sdstp1
,strap
);
445 if ((strap
& SDR0_SDSTP1_PISE_MASK
) == 0) {
446 printf("PCI: SDR0_STRP1[PISE] not set.\n");
447 printf("PCI: Configuration aborted.\n");
450 #elif defined(CONFIG_440GP)
453 strap
= mfdcr(cpc0_strp1
);
454 if ((strap
& CPC0_STRP1_PISE_MASK
) == 0) {
455 printf("PCI: CPC0_STRP1[PISE] not set.\n");
456 printf("PCI: Configuration aborted.\n");
460 #endif /* CONFIG_DISABLE_PISE_TEST */
462 /*--------------------------------------------------------------------------+
463 * PCI controller init
464 *--------------------------------------------------------------------------*/
465 hose
->first_busno
= 0;
466 hose
->last_busno
= 0xff;
468 pci_set_region(hose
->regions
+ reg_num
++,
474 pci_set_region(hose
->regions
+ reg_num
++,
479 hose
->region_count
= reg_num
;
481 pci_setup_indirect(hose
, PCIX0_CFGADR
, PCIX0_CFGDATA
);
483 #if defined(CFG_PCI_PRE_INIT)
484 /* Let board change/modify hose & do initial checks */
485 if (pci_pre_init (hose
) == 0) {
486 printf("PCI: Board-specific initialization failed.\n");
487 printf("PCI: Configuration aborted.\n");
492 pci_register_hose( hose
);
494 /*--------------------------------------------------------------------------+
496 *--------------------------------------------------------------------------*/
497 #if defined(CFG_PCI_TARGET_INIT)
498 pci_target_init(hose
); /* Let board setup pci target */
500 out16r( PCIX0_SBSYSVID
, CFG_PCI_SUBSYS_VENDORID
);
501 out16r( PCIX0_SBSYSID
, CFG_PCI_SUBSYS_ID
);
502 out16r( PCIX0_CLS
, 0x00060000 ); /* Bridge, host bridge */
505 #if defined(CONFIG_440GX)
506 out32r( PCIX0_BRDGOPT1
, 0x04000060 ); /* PLB Rq pri highest */
507 out32r( PCIX0_BRDGOPT2
, in32(PCIX0_BRDGOPT2
) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
508 #elif defined(PCIX0_BRDGOPT1)
509 out32r( PCIX0_BRDGOPT1
, 0x10000060 ); /* PLB Rq pri highest */
510 out32r( PCIX0_BRDGOPT2
, in32(PCIX0_BRDGOPT2
) | 1 ); /* Enable host config */
513 /*--------------------------------------------------------------------------+
514 * PCI master init: default is one 256MB region for PCI memory:
515 * 0x3_00000000 - 0x3_0FFFFFFF ==> CFG_PCI_MEMBASE
516 *--------------------------------------------------------------------------*/
517 #if defined(CFG_PCI_MASTER_INIT)
518 pci_master_init(hose
); /* Let board setup pci master */
520 out32r( PCIX0_POM0SA
, 0 ); /* disable */
521 out32r( PCIX0_POM1SA
, 0 ); /* disable */
522 out32r( PCIX0_POM2SA
, 0 ); /* disable */
523 out32r( PCIX0_POM0LAL
, 0x00000000 );
524 out32r( PCIX0_POM0LAH
, 0x00000003 );
525 out32r( PCIX0_POM0PCIAL
, CFG_PCI_MEMBASE
);
526 out32r( PCIX0_POM0PCIAH
, 0x00000000 );
527 out32r( PCIX0_POM0SA
, 0xf0000001 ); /* 256MB, enabled */
528 out32r( PCIX0_STS
, in32r( PCIX0_STS
) & ~0x0000fff8 );
531 /*--------------------------------------------------------------------------+
532 * PCI host configuration -- we don't make any assumptions here ... the
533 * _board_must_indicate_ what to do -- there's just too many runtime
534 * scenarios in environments like cPCI, PPMC, etc. to make a determination
535 * based on hard-coded values or state of arbiter enable.
536 *--------------------------------------------------------------------------*/
537 if (is_pci_host(hose
)) {
538 #ifdef CONFIG_PCI_SCAN_SHOW
539 printf("PCI: Bus Dev VenId DevId Class Int\n");
541 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
542 out16r( PCIX0_CMD
, in16r( PCIX0_CMD
) | PCI_COMMAND_MASTER
);
544 hose
->last_busno
= pci_hose_scan(hose
);
549 void pci_init_board(void)
551 pci_440_init (&ppc440_hose
);
554 #endif /* CONFIG_440 & CONFIG_PCI */