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Patch by Travis Sawyer, 30 Dec 2003:
[people/ms/u-boot.git] / cpu / ppc4xx / 440gx_enet.c
1 /*-----------------------------------------------------------------------------+
2 *
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
9 *
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
13 *
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
17 *
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
22 *
23 * File Name: enetemac.c
24 *
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
26 *
27 * Author: Mark Wisner
28 *
29 * Change Activity-
30 *
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
48 * include/net.h
49 * - Receive buffer descriptor ring is used to send buffers
50 * to the user
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
66 * used anymore)
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
74 * (2 EMACs) also
75 *-----------------------------------------------------------------------------*/
76
77 #include <config.h>
78 #if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
79
80 #include <common.h>
81 #include <net.h>
82 #include <asm/processor.h>
83 #include <ppc440.h>
84 #include <commproc.h>
85 #include <440gx_enet.h>
86 #include <405_mal.h>
87 #include <miiphy.h>
88 #include <malloc.h>
89 #include "vecnum.h"
90
91
92 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
93 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
94
95
96 /* Ethernet Transmit and Receive Buffers */
97 /* AS.HARNOIS
98 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
99 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
100 */
101 #define ENET_MAX_MTU PKTSIZE
102 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
103
104
105 /* define the number of channels implemented */
106 #define EMAC_RXCHL EMAC_NUM_DEV
107 #define EMAC_TXCHL EMAC_NUM_DEV
108
109 /*-----------------------------------------------------------------------------+
110 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
111 * Interrupt Controller).
112 *-----------------------------------------------------------------------------*/
113 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
114 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
115 #define EMAC_UIC_DEF UIC_ENET
116
117 #undef INFO_440_ENET
118
119 /*-----------------------------------------------------------------------------+
120 * Global variables. TX and RX descriptors and buffers.
121 *-----------------------------------------------------------------------------*/
122 /* IER globals */
123 static uint32_t mal_ier;
124
125 /*-----------------------------------------------------------------------------+
126 * Prototypes and externals.
127 *-----------------------------------------------------------------------------*/
128 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
129
130 int enetInt (struct eth_device *dev);
131 static void mal_err (struct eth_device *dev, unsigned long isr,
132 unsigned long uic, unsigned long maldef,
133 unsigned long mal_errr);
134 static void emac_err (struct eth_device *dev, unsigned long isr);
135
136 /*-----------------------------------------------------------------------------+
137 | ppc_440x_eth_halt
138 | Disable MAL channel, and EMACn
139 |
140 |
141 +-----------------------------------------------------------------------------*/
142 static void ppc_440x_eth_halt (struct eth_device *dev)
143 {
144 EMAC_440GX_HW_PST hw_p = dev->priv;
145 uint32_t failsafe = 10000;
146
147 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
148
149 /* 1st reset MAL channel */
150 /* Note: writing a 0 to a channel has no effect */
151 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
152 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
153
154 /* wait for reset */
155 while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
156 udelay (1000); /* Delay 1 MS so as not to hammer the register */
157 failsafe--;
158 if (failsafe == 0)
159 break;
160
161 }
162
163 /* EMAC RESET */
164 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
165
166 hw_p->print_speed = 1; /* print speed message again next time */
167
168 return;
169 }
170
171 extern int phy_setup_aneg (unsigned char addr);
172 extern int miiphy_reset (unsigned char addr);
173
174 static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
175 {
176 int i;
177 unsigned long reg;
178 unsigned long msr;
179 unsigned long speed;
180 unsigned long duplex;
181 unsigned long failsafe;
182 unsigned mode_reg;
183 unsigned short devnum;
184 unsigned short reg_short;
185 sys_info_t sysinfo;
186
187 EMAC_440GX_HW_PST hw_p = dev->priv;
188
189 /* before doing anything, figure out if we have a MAC address */
190 /* if not, bail */
191 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
192 return -1;
193
194 /* Need to get the OPB frequency so we can access the PHY */
195 get_sys_info (&sysinfo);
196
197
198 msr = mfmsr ();
199 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
200
201 devnum = hw_p->devnum;
202
203 #ifdef INFO_440_ENET
204 /* AS.HARNOIS
205 * We should have :
206 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
207 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
208 * is possible that new packets (without relationship with
209 * current transfer) have got the time to arrived before
210 * netloop calls eth_halt
211 */
212 printf ("About preceeding transfer (eth%d):\n"
213 "- Sent packet number %d\n"
214 "- Received packet number %d\n"
215 "- Handled packet number %d\n",
216 hw_p->devnum,
217 hw_p->stats.pkts_tx,
218 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
219
220 hw_p->stats.pkts_tx = 0;
221 hw_p->stats.pkts_rx = 0;
222 hw_p->stats.pkts_handled = 0;
223 #endif
224
225 /* MAL Channel RESET */
226 /* 1st reset MAL channel */
227 /* Note: writing a 0 to a channel has no effect */
228 mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
229 mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
230
231 /* wait for reset */
232 /* TBS: should have udelay and failsafe here */
233 failsafe = 10000;
234 /* wait for reset */
235 while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
236 udelay (1000); /* Delay 1 MS so as not to hammer the register */
237 failsafe--;
238 if (failsafe == 0)
239 break;
240
241 }
242
243 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
244 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
245
246 hw_p->rx_slot = 0; /* MAL Receive Slot */
247 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
248 hw_p->rx_u_index = 0; /* Receive User Queue Index */
249
250 hw_p->tx_slot = 0; /* MAL Transmit Slot */
251 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
252 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
253
254 /* set RMII mode */
255 /* NOTE: 440GX spec states that mode is mutually exclusive */
256 /* NOTE: Therefore, disable all other EMACS, since we handle */
257 /* NOTE: only one emac at a time */
258 reg = 0;
259 out32 (ZMII_FER, 0);
260 udelay (100);
261 out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
262 out32 (ZMII_SSR, 0x11110000);
263 /* reset emac so we have access to the phy */
264 __asm__ volatile ("eieio");
265
266 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
267 __asm__ volatile ("eieio");
268
269 if ((devnum == 2) || (devnum == 3))
270 out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
271 (RGMII_FER_RGMII << RGMII_FER_V (3))));
272 __asm__ volatile ("eieio");
273
274 failsafe = 1000;
275 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
276 udelay (1000);
277 failsafe--;
278 }
279
280 /* Whack the M1 register */
281 mode_reg = 0x0;
282 mode_reg &= ~0x00000038;
283 if (sysinfo.freqOPB <= 50000000);
284 else if (sysinfo.freqOPB <= 66666667)
285 mode_reg |= EMAC_M1_OBCI_66;
286 else if (sysinfo.freqOPB <= 83333333)
287 mode_reg |= EMAC_M1_OBCI_83;
288 else if (sysinfo.freqOPB <= 100000000)
289 mode_reg |= EMAC_M1_OBCI_100;
290 else
291 mode_reg |= EMAC_M1_OBCI_GT100;
292
293 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
294
295
296 /* wait for PHY to complete auto negotiation */
297 reg_short = 0;
298 #ifndef CONFIG_CS8952_PHY
299 switch (devnum) {
300 case 0:
301 reg = CONFIG_PHY_ADDR;
302 break;
303 case 1:
304 reg = CONFIG_PHY1_ADDR;
305 break;
306 #if defined (CONFIG_440_GX)
307 case 2:
308 reg = CONFIG_PHY2_ADDR;
309 break;
310 case 3:
311 reg = CONFIG_PHY3_ADDR;
312 break;
313 #endif
314 default:
315 reg = CONFIG_PHY_ADDR;
316 break;
317 }
318
319 /* Reset the phy */
320 miiphy_reset (reg);
321
322 /* Start/Restart autonegotiation */
323 /* miiphy_write(reg, PHY_BMCR, 0x9340); */
324 phy_setup_aneg (reg);
325 udelay (1000);
326
327 miiphy_read (reg, PHY_BMSR, &reg_short);
328
329 /*
330 * Wait if PHY is able of autonegotiation and autonegotiation is not complete
331 */
332 if ((reg_short & PHY_BMSR_AUTN_ABLE)
333 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
334 puts ("Waiting for PHY auto negotiation to complete");
335 i = 0;
336 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
337 /*
338 * Timeout reached ?
339 */
340 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
341 puts (" TIMEOUT !\n");
342 break;
343 }
344
345 if ((i++ % 1000) == 0) {
346 putc ('.');
347 }
348 udelay (1000); /* 1 ms */
349 miiphy_read (reg, PHY_BMSR, &reg_short);
350
351 }
352 puts (" done\n");
353 udelay (500000); /* another 500 ms (results in faster booting) */
354 }
355 #endif
356 speed = miiphy_speed (reg);
357 duplex = miiphy_duplex (reg);
358
359 if (hw_p->print_speed) {
360 hw_p->print_speed = 0;
361 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
362 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
363 }
364
365 /* Set ZMII/RGMII speed according to the phy link speed */
366 reg = in32 (ZMII_SSR);
367 if (speed == 100)
368 out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
369 else
370 out32 (ZMII_SSR,
371 reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
372
373 if ((devnum == 2) || (devnum == 3)) {
374 if (speed == 1000)
375 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
376 else if (speed == 100)
377 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
378 else
379 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
380
381 out32 (RGMII_SSR, reg);
382 }
383
384 /* set the Mal configuration reg */
385 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
386 if (get_pvr () == PVR_440GP_RB)
387 mtdcr (malmcr,
388 MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
389 else
390 mtdcr (malmcr,
391 MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
392 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
393
394 /* Free "old" buffers */
395 if (hw_p->alloc_tx_buf)
396 free (hw_p->alloc_tx_buf);
397 if (hw_p->alloc_rx_buf)
398 free (hw_p->alloc_rx_buf);
399
400 /*
401 * Malloc MAL buffer desciptors, make sure they are
402 * aligned on cache line boundary size
403 * (401/403/IOP480 = 16, 405 = 32)
404 * and doesn't cross cache block boundaries.
405 */
406 hw_p->alloc_tx_buf =
407 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
408 ((2 * CFG_CACHELINE_SIZE) - 2));
409 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
410 hw_p->tx =
411 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
412 CFG_CACHELINE_SIZE -
413 ((int) hw_p->
414 alloc_tx_buf & CACHELINE_MASK));
415 } else {
416 hw_p->tx = hw_p->alloc_tx_buf;
417 }
418
419 hw_p->alloc_rx_buf =
420 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
421 ((2 * CFG_CACHELINE_SIZE) - 2));
422 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
423 hw_p->rx =
424 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
425 CFG_CACHELINE_SIZE -
426 ((int) hw_p->
427 alloc_rx_buf & CACHELINE_MASK));
428 } else {
429 hw_p->rx = hw_p->alloc_rx_buf;
430 }
431
432 for (i = 0; i < NUM_TX_BUFF; i++) {
433 hw_p->tx[i].ctrl = 0;
434 hw_p->tx[i].data_len = 0;
435 if (hw_p->first_init == 0)
436 hw_p->txbuf_ptr =
437 (char *) malloc (ENET_MAX_MTU_ALIGNED);
438 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
439 if ((NUM_TX_BUFF - 1) == i)
440 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
441 hw_p->tx_run[i] = -1;
442 #if 0
443 printf ("TX_BUFF %d @ 0x%08lx\n", i,
444 (ulong) hw_p->tx[i].data_ptr);
445 #endif
446 }
447
448 for (i = 0; i < NUM_RX_BUFF; i++) {
449 hw_p->rx[i].ctrl = 0;
450 hw_p->rx[i].data_len = 0;
451 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
452 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
453 if ((NUM_RX_BUFF - 1) == i)
454 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
455 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
456 hw_p->rx_ready[i] = -1;
457 #if 0
458 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
459 #endif
460 }
461
462 reg = 0x00000000;
463
464 reg |= dev->enetaddr[0]; /* set high address */
465 reg = reg << 8;
466 reg |= dev->enetaddr[1];
467
468 out32 (EMAC_IAH + hw_p->hw_addr, reg);
469
470 reg = 0x00000000;
471 reg |= dev->enetaddr[2]; /* set low address */
472 reg = reg << 8;
473 reg |= dev->enetaddr[3];
474 reg = reg << 8;
475 reg |= dev->enetaddr[4];
476 reg = reg << 8;
477 reg |= dev->enetaddr[5];
478
479 out32 (EMAC_IAL + hw_p->hw_addr, reg);
480
481 switch (devnum) {
482 case 1:
483 /* setup MAL tx & rx channel pointers */
484 mtdcr (maltxbattr, 0x0);
485 mtdcr (maltxctp1r, hw_p->tx);
486 mtdcr (malrxbattr, 0x0);
487 mtdcr (malrxctp1r, hw_p->rx);
488 /* set RX buffer size */
489 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
490 break;
491 #if defined (CONFIG_440_GX)
492 case 2:
493 /* setup MAL tx & rx channel pointers */
494 mtdcr (maltxbattr, 0x0);
495 mtdcr (maltxctp2r, hw_p->tx);
496 mtdcr (malrxbattr, 0x0);
497 mtdcr (malrxctp2r, hw_p->rx);
498 /* set RX buffer size */
499 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
500 break;
501 case 3:
502 /* setup MAL tx & rx channel pointers */
503 mtdcr (maltxbattr, 0x0);
504 mtdcr (maltxctp3r, hw_p->tx);
505 mtdcr (malrxbattr, 0x0);
506 mtdcr (malrxctp3r, hw_p->rx);
507 /* set RX buffer size */
508 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
509 break;
510 #endif /*CONFIG_440_GX */
511 case 0:
512 default:
513 /* setup MAL tx & rx channel pointers */
514 mtdcr (maltxbattr, 0x0);
515 mtdcr (maltxctp0r, hw_p->tx);
516 mtdcr (malrxbattr, 0x0);
517 mtdcr (malrxctp0r, hw_p->rx);
518 /* set RX buffer size */
519 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
520 break;
521 }
522
523 /* Enable MAL transmit and receive channels */
524 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
525 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
526
527 /* set transmit enable & receive enable */
528 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
529
530 /* set receive fifo to 4k and tx fifo to 2k */
531 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
532 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
533
534 /* set speed */
535 /* TBS: do 1GbE */
536 if (speed == _100BASET)
537 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
538 else
539 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
540 if (duplex == FULL)
541 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
542
543 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
544
545 /* Enable broadcast and indvidual address */
546 /* TBS: enabling runts as some misbehaved nics will send runts */
547 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
548
549 /* we probably need to set the tx mode1 reg? maybe at tx time */
550
551 /* set transmit request threshold register */
552 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
553
554 /* set receive low/high water mark register */
555 /* 440GP has a 64 byte burst length */
556 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
557 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
558
559 /* Set fifo limit entry in tx mode 0 */
560 out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
561 /* Frame gap set */
562 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
563
564 /* Set EMAC IER */
565 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
566 EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
567 if (speed == _100BASET)
568 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
569
570 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
571 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
572
573 if (hw_p->first_init == 0) {
574 /*
575 * Connect interrupt service routines
576 */
577 irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
578 (interrupt_handler_t *) enetInt, dev);
579 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
580 (interrupt_handler_t *) enetInt, dev);
581 }
582 #if 0 /* done by irq_install_handler */
583 /* set up interrupt handler */
584 /* setup interrupt controller to take interrupts from the MAL &
585 EMAC */
586 mtdcr (uicsr, 0xffffffff); /* clear pending interrupts */
587 mtdcr (uicer, mfdcr (uicer) | MAL_UIC_DEF | EMAC_UIC_DEF);
588 #endif
589
590 mtmsr (msr); /* enable interrupts again */
591
592 hw_p->bis = bis;
593 hw_p->first_init = 1;
594
595 return (1);
596 }
597
598
599 static int ppc_440x_eth_send (struct eth_device *dev, volatile void *ptr,
600 int len)
601 {
602 struct enet_frame *ef_ptr;
603 ulong time_start, time_now;
604 unsigned long temp_txm0;
605 EMAC_440GX_HW_PST hw_p = dev->priv;
606
607 ef_ptr = (struct enet_frame *) ptr;
608
609 /*-----------------------------------------------------------------------+
610 * Copy in our address into the frame.
611 *-----------------------------------------------------------------------*/
612 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
613
614 /*-----------------------------------------------------------------------+
615 * If frame is too long or too short, modify length.
616 *-----------------------------------------------------------------------*/
617 /* TBS: where does the fragment go???? */
618 if (len > ENET_MAX_MTU)
619 len = ENET_MAX_MTU;
620
621 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
622 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
623
624 /*-----------------------------------------------------------------------+
625 * set TX Buffer busy, and send it
626 *-----------------------------------------------------------------------*/
627 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
628 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
629 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
630 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
631 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
632
633 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
634 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
635
636 __asm__ volatile ("eieio");
637
638 out32 (EMAC_TXM0 + hw_p->hw_addr,
639 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
640 #ifdef INFO_440_ENET
641 hw_p->stats.pkts_tx++;
642 #endif
643
644 /*-----------------------------------------------------------------------+
645 * poll unitl the packet is sent and then make sure it is OK
646 *-----------------------------------------------------------------------*/
647 time_start = get_timer (0);
648 while (1) {
649 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
650 /* loop until either TINT turns on or 3 seconds elapse */
651 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
652 /* transmit is done, so now check for errors
653 * If there is an error, an interrupt should
654 * happen when we return
655 */
656 time_now = get_timer (0);
657 if ((time_now - time_start) > 3000) {
658 return (-1);
659 }
660 } else {
661 return (len);
662 }
663 }
664 }
665
666
667 int enetInt (struct eth_device *dev)
668 {
669 int serviced;
670 int rc = -1; /* default to not us */
671 unsigned long mal_isr;
672 unsigned long emac_isr = 0;
673 unsigned long mal_rx_eob;
674 unsigned long my_uic0msr, my_uic1msr;
675
676 #if defined(CONFIG_440_GX)
677 unsigned long my_uic2msr;
678 #endif
679 EMAC_440GX_HW_PST hw_p;
680
681 /*
682 * Because the mal is generic, we need to get the current
683 * eth device
684 */
685 dev = eth_get_dev ();
686
687 hw_p = dev->priv;
688
689
690 /* enter loop that stays in interrupt code until nothing to service */
691 do {
692 serviced = 0;
693
694 my_uic0msr = mfdcr (uic0msr);
695 my_uic1msr = mfdcr (uic1msr);
696 #if defined(CONFIG_440_GX)
697 my_uic2msr = mfdcr (uic2msr);
698 #endif
699 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
700 && !(my_uic1msr &
701 (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
702 UIC_MRDE))) {
703 /* not for us */
704 return (rc);
705 }
706 #if defined (CONFIG_440_GX)
707 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
708 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
709 /* not for us */
710 return (rc);
711 }
712 #endif
713 /* get and clear controller status interrupts */
714 /* look at Mal and EMAC interrupts */
715 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
716 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
717 /* we have a MAL interrupt */
718 mal_isr = mfdcr (malesr);
719 /* look for mal error */
720 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
721 mal_err (dev, mal_isr, my_uic0msr,
722 MAL_UIC_DEF, MAL_UIC_ERR);
723 serviced = 1;
724 rc = 0;
725 }
726 }
727
728 /* port by port dispatch of emac interrupts */
729 if (hw_p->devnum == 0) {
730 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
731 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
732 if ((hw_p->emac_ier & emac_isr) != 0) {
733 emac_err (dev, emac_isr);
734 serviced = 1;
735 rc = 0;
736 }
737 }
738 if ((hw_p->emac_ier & emac_isr)
739 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
740 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
741 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
742 return (rc); /* we had errors so get out */
743 }
744 }
745
746 if (hw_p->devnum == 1) {
747 if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
748 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
749 if ((hw_p->emac_ier & emac_isr) != 0) {
750 emac_err (dev, emac_isr);
751 serviced = 1;
752 rc = 0;
753 }
754 }
755 if ((hw_p->emac_ier & emac_isr)
756 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
757 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
758 mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
759 return (rc); /* we had errors so get out */
760 }
761 }
762 #if defined (CONFIG_440_GX)
763 if (hw_p->devnum == 2) {
764 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
765 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
766 if ((hw_p->emac_ier & emac_isr) != 0) {
767 emac_err (dev, emac_isr);
768 serviced = 1;
769 rc = 0;
770 }
771 }
772 if ((hw_p->emac_ier & emac_isr)
773 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
774 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
775 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
776 mtdcr (uic2sr, UIC_ETH2);
777 return (rc); /* we had errors so get out */
778 }
779 }
780
781 if (hw_p->devnum == 3) {
782 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
783 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
784 if ((hw_p->emac_ier & emac_isr) != 0) {
785 emac_err (dev, emac_isr);
786 serviced = 1;
787 rc = 0;
788 }
789 }
790 if ((hw_p->emac_ier & emac_isr)
791 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
792 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
793 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
794 mtdcr (uic2sr, UIC_ETH3);
795 return (rc); /* we had errors so get out */
796 }
797 }
798 #endif /* CONFIG_440_GX */
799 /* handle MAX TX EOB interrupt from a tx */
800 if (my_uic0msr & UIC_MTE) {
801 mal_rx_eob = mfdcr (maltxeobisr);
802 mtdcr (maltxeobisr, mal_rx_eob);
803 mtdcr (uic0sr, UIC_MTE);
804 }
805 /* handle MAL RX EOB interupt from a receive */
806 /* check for EOB on valid channels */
807 if (my_uic0msr & UIC_MRE) {
808 mal_rx_eob = mfdcr (malrxeobisr);
809 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
810 /* clear EOB
811 mtdcr(malrxeobisr, mal_rx_eob); */
812 enet_rcv (dev, emac_isr);
813 /* indicate that we serviced an interrupt */
814 serviced = 1;
815 rc = 0;
816 }
817 }
818 mtdcr (uic0sr, UIC_MRE); /* Clear */
819 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
820 switch (hw_p->devnum) {
821 case 0:
822 mtdcr (uic1sr, UIC_ETH0);
823 break;
824 case 1:
825 mtdcr (uic1sr, UIC_ETH1);
826 break;
827 #if defined (CONFIG_440_GX)
828 case 2:
829 mtdcr (uic2sr, UIC_ETH2);
830 break;
831 case 3:
832 mtdcr (uic2sr, UIC_ETH3);
833 break;
834 #endif /* CONFIG_440_GX */
835 default:
836 break;
837 }
838 } while (serviced);
839
840 return (rc);
841 }
842
843 /*-----------------------------------------------------------------------------+
844 * MAL Error Routine
845 *-----------------------------------------------------------------------------*/
846 static void mal_err (struct eth_device *dev, unsigned long isr,
847 unsigned long uic, unsigned long maldef,
848 unsigned long mal_errr)
849 {
850 EMAC_440GX_HW_PST hw_p = dev->priv;
851
852 mtdcr (malesr, isr); /* clear interrupt */
853
854 /* clear DE interrupt */
855 mtdcr (maltxdeir, 0xC0000000);
856 mtdcr (malrxdeir, 0x80000000);
857
858 #ifdef INFO_440_ENET
859 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
860 #endif
861
862 eth_init (hw_p->bis); /* start again... */
863 }
864
865 /*-----------------------------------------------------------------------------+
866 * EMAC Error Routine
867 *-----------------------------------------------------------------------------*/
868 static void emac_err (struct eth_device *dev, unsigned long isr)
869 {
870 EMAC_440GX_HW_PST hw_p = dev->priv;
871
872 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
873 out32 (EMAC_ISR + hw_p->hw_addr, isr);
874 }
875
876 /*-----------------------------------------------------------------------------+
877 * enet_rcv() handles the ethernet receive data
878 *-----------------------------------------------------------------------------*/
879 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
880 {
881 struct enet_frame *ef_ptr;
882 unsigned long data_len;
883 unsigned long rx_eob_isr;
884 EMAC_440GX_HW_PST hw_p = dev->priv;
885
886 int handled = 0;
887 int i;
888 int loop_count = 0;
889
890 rx_eob_isr = mfdcr (malrxeobisr);
891 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
892 /* clear EOB */
893 mtdcr (malrxeobisr, rx_eob_isr);
894
895 /* EMAC RX done */
896 while (1) { /* do all */
897 i = hw_p->rx_slot;
898
899 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
900 || (loop_count >= NUM_RX_BUFF))
901 break;
902 loop_count++;
903 hw_p->rx_slot++;
904 if (NUM_RX_BUFF == hw_p->rx_slot)
905 hw_p->rx_slot = 0;
906 handled++;
907 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
908 if (data_len) {
909 if (data_len > ENET_MAX_MTU) /* Check len */
910 data_len = 0;
911 else {
912 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
913 data_len = 0;
914 hw_p->stats.rx_err_log[hw_p->
915 rx_err_index]
916 = hw_p->rx[i].ctrl;
917 hw_p->rx_err_index++;
918 if (hw_p->rx_err_index ==
919 MAX_ERR_LOG)
920 hw_p->rx_err_index =
921 0;
922 } /* emac_erros */
923 } /* data_len < max mtu */
924 } /* if data_len */
925 if (!data_len) { /* no data */
926 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
927
928 hw_p->stats.data_len_err++; /* Error at Rx */
929 }
930
931 /* !data_len */
932 /* AS.HARNOIS */
933 /* Check if user has already eaten buffer */
934 /* if not => ERROR */
935 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
936 if (hw_p->is_receiving)
937 printf ("ERROR : Receive buffers are full!\n");
938 break;
939 } else {
940 hw_p->stats.rx_frames++;
941 hw_p->stats.rx += data_len;
942 ef_ptr = (struct enet_frame *) hw_p->rx[i].
943 data_ptr;
944 #ifdef INFO_440_ENET
945 hw_p->stats.pkts_rx++;
946 #endif
947 /* AS.HARNOIS
948 * use ring buffer
949 */
950 hw_p->rx_ready[hw_p->rx_i_index] = i;
951 hw_p->rx_i_index++;
952 if (NUM_RX_BUFF == hw_p->rx_i_index)
953 hw_p->rx_i_index = 0;
954
955 /* printf("X"); /|* test-only *|/ */
956
957 /* AS.HARNOIS
958 * free receive buffer only when
959 * buffer has been handled (eth_rx)
960 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
961 */
962 } /* if data_len */
963 } /* while */
964 } /* if EMACK_RXCHL */
965 }
966
967
968 static int ppc_440x_eth_rx (struct eth_device *dev)
969 {
970 int length;
971 int user_index;
972 unsigned long msr;
973 EMAC_440GX_HW_PST hw_p = dev->priv;
974
975 hw_p->is_receiving = 1; /* tell driver */
976
977 for (;;) {
978 /* AS.HARNOIS
979 * use ring buffer and
980 * get index from rx buffer desciptor queue
981 */
982 user_index = hw_p->rx_ready[hw_p->rx_u_index];
983 if (user_index == -1) {
984 length = -1;
985 break; /* nothing received - leave for() loop */
986 }
987
988 msr = mfmsr ();
989 mtmsr (msr & ~(MSR_EE));
990
991 length = hw_p->rx[user_index].data_len;
992
993 /* Pass the packet up to the protocol layers. */
994 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
995 /* NetReceive(NetRxPackets[i], length); */
996 NetReceive (NetRxPackets[user_index], length - 4);
997 /* Free Recv Buffer */
998 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
999 /* Free rx buffer descriptor queue */
1000 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1001 hw_p->rx_u_index++;
1002 if (NUM_RX_BUFF == hw_p->rx_u_index)
1003 hw_p->rx_u_index = 0;
1004
1005 #ifdef INFO_440_ENET
1006 hw_p->stats.pkts_handled++;
1007 #endif
1008
1009 mtmsr (msr); /* Enable IRQ's */
1010 }
1011
1012 hw_p->is_receiving = 0; /* tell driver */
1013
1014 return length;
1015 }
1016
1017 int ppc_440x_eth_initialize (bd_t * bis)
1018 {
1019 static int virgin = 0;
1020 unsigned long pfc1;
1021 struct eth_device *dev;
1022 int eth_num = 0;
1023
1024 EMAC_440GX_HW_PST hw = NULL;
1025
1026 mfsdr (sdr_pfc1, pfc1);
1027 pfc1 &= ~(0x01e00000);
1028 pfc1 |= 0x01200000;
1029 mtsdr (sdr_pfc1, pfc1);
1030
1031 for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
1032
1033 /* See if we can actually bring up the interface, otherwise, skip it */
1034 switch (eth_num) {
1035 case 0:
1036 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0)
1037 continue;
1038 break;
1039 case 1:
1040 if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) ==
1041 0)
1042 continue;
1043 break;
1044 case 2:
1045 if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) ==
1046 0)
1047 continue;
1048 break;
1049 case 3:
1050 if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) ==
1051 0)
1052 continue;
1053 break;
1054 default:
1055 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0)
1056 continue;
1057 break;
1058 }
1059
1060 /* Allocate device structure */
1061 dev = (struct eth_device *) malloc (sizeof (*dev));
1062 if (dev == NULL) {
1063 printf (__FUNCTION__
1064 ": Cannot allocate eth_device %d\n", eth_num);
1065 return (-1);
1066 }
1067
1068 /* Allocate our private use data */
1069 hw = (EMAC_440GX_HW_PST) malloc (sizeof (*hw));
1070 if (hw == NULL) {
1071 printf (__FUNCTION__
1072 ": Cannot allocate private hw data for eth_device %d",
1073 eth_num);
1074 free (dev);
1075 return (-1);
1076 }
1077
1078 switch (eth_num) {
1079 case 0:
1080 hw->hw_addr = 0;
1081 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1082 break;
1083 case 1:
1084 hw->hw_addr = 0x100;
1085 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
1086 break;
1087 case 2:
1088 hw->hw_addr = 0x400;
1089 memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
1090 break;
1091 case 3:
1092 hw->hw_addr = 0x600;
1093 memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
1094 break;
1095 default:
1096 hw->hw_addr = 0;
1097 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1098 break;
1099 }
1100
1101 hw->devnum = eth_num;
1102
1103 sprintf (dev->name, "ppc_440x_eth%d", eth_num);
1104 dev->priv = (void *) hw;
1105 dev->init = ppc_440x_eth_init;
1106 dev->halt = ppc_440x_eth_halt;
1107 dev->send = ppc_440x_eth_send;
1108 dev->recv = ppc_440x_eth_rx;
1109
1110 if (0 == virgin) {
1111 /* set the MAL IER ??? names may change with new spec ??? */
1112 mal_ier =
1113 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1114 MAL_IER_OPBE | MAL_IER_PLBE;
1115 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1116 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1117 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1118 mtdcr (malier, mal_ier);
1119
1120 /* install MAL interrupt handler */
1121 irq_install_handler (VECNUM_MS,
1122 (interrupt_handler_t *) enetInt,
1123 dev);
1124 irq_install_handler (VECNUM_MTE,
1125 (interrupt_handler_t *) enetInt,
1126 dev);
1127 irq_install_handler (VECNUM_MRE,
1128 (interrupt_handler_t *) enetInt,
1129 dev);
1130 irq_install_handler (VECNUM_TXDE,
1131 (interrupt_handler_t *) enetInt,
1132 dev);
1133 irq_install_handler (VECNUM_RXDE,
1134 (interrupt_handler_t *) enetInt,
1135 dev);
1136 virgin = 1;
1137 }
1138
1139 eth_register (dev);
1140
1141 } /* end for each supported device */
1142 return (1);
1143 }
1144 #endif /* CONFIG_440 && CONFIG_NET_MULTI */
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