]> git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/ppc4xx/44x_spd_ddr.c
projects / people / ms / u-boot.git / blob
? search:


8621aa00cf4e561f96733f444778cb9a97d3d99c
[people/ms/u-boot.git] / cpu / ppc4xx / 44x_spd_ddr.c
1 /*
2 * cpu/ppc4xx/44x_spd_ddr.c
3 * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
4 * DDR controller. Those are 440GP/GX/EP/GR.
5 *
6 * (C) Copyright 2001
7 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
8 *
9 * Based on code by:
10 *
11 * Kenneth Johansson ,Ericsson AB.
12 * kenneth.johansson@etx.ericsson.se
13 *
14 * hacked up by bill hunter. fixed so we could run before
15 * serial_init and console_init. previous version avoided this by
16 * running out of cache memory during serial/console init, then running
17 * this code later.
18 *
19 * (C) Copyright 2002
20 * Jun Gu, Artesyn Technology, jung@artesyncp.com
21 * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
22 *
23 * (C) Copyright 2005-2007
24 * Stefan Roese, DENX Software Engineering, sr@denx.de.
25 *
26 * See file CREDITS for list of people who contributed to this
27 * project.
28 *
29 * This program is free software; you can redistribute it and/or
30 * modify it under the terms of the GNU General Public License as
31 * published by the Free Software Foundation; either version 2 of
32 * the License, or (at your option) any later version.
33 *
34 * This program is distributed in the hope that it will be useful,
35 * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 * GNU General Public License for more details.
38 *
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42 * MA 02111-1307 USA
43 */
44
45 /* define DEBUG for debugging output (obviously ;-)) */
46 #if 0
47 #define DEBUG
48 #endif
49
50 #include <common.h>
51 #include <asm/processor.h>
52 #include <i2c.h>
53 #include <ppc4xx.h>
54 #include <asm/mmu.h>
55
56 #if defined(CONFIG_SPD_EEPROM) && \
57 (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
58 defined(CONFIG_440EP) || defined(CONFIG_440GR))
59
60 /*
61 * Set default values
62 */
63 #ifndef CFG_I2C_SPEED
64 #define CFG_I2C_SPEED 50000
65 #endif
66
67 #ifndef CFG_I2C_SLAVE
68 #define CFG_I2C_SLAVE 0xFE
69 #endif
70
71 #define ONE_BILLION 1000000000
72
73 #if defined(CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG)
74 extern void spd_ddr_init_hang (void);
75 #define HANG() spd_ddr_init_hang()
76 #else
77 #define HANG() hang()
78 #endif
79
80 /*-----------------------------------------------------------------------------
81 | Memory Controller Options 0
82 +-----------------------------------------------------------------------------*/
83 #define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
84 #define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
85 #define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
86 #define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
87 #define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
88 #define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
89 #define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
90 #define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
91 #define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
92 #define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
93 #define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
94 #define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
95
96 /*-----------------------------------------------------------------------------
97 | Memory Controller Options 1
98 +-----------------------------------------------------------------------------*/
99 #define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
100 #define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
101
102 /*-----------------------------------------------------------------------------+
103 | SDRAM DEVPOT Options
104 +-----------------------------------------------------------------------------*/
105 #define SDRAM_DEVOPT_DLL 0x80000000
106 #define SDRAM_DEVOPT_DS 0x40000000
107
108 /*-----------------------------------------------------------------------------+
109 | SDRAM MCSTS Options
110 +-----------------------------------------------------------------------------*/
111 #define SDRAM_MCSTS_MRSC 0x80000000
112 #define SDRAM_MCSTS_SRMS 0x40000000
113 #define SDRAM_MCSTS_CIS 0x20000000
114
115 /*-----------------------------------------------------------------------------
116 | SDRAM Refresh Timer Register
117 +-----------------------------------------------------------------------------*/
118 #define SDRAM_RTR_RINT_MASK 0xFFFF0000
119 #define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
120 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
121
122 /*-----------------------------------------------------------------------------+
123 | SDRAM UABus Base Address Reg
124 +-----------------------------------------------------------------------------*/
125 #define SDRAM_UABBA_UBBA_MASK 0x0000000F
126
127 /*-----------------------------------------------------------------------------+
128 | Memory Bank 0-7 configuration
129 +-----------------------------------------------------------------------------*/
130 #define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
131 #define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
132 #define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
133 #define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
134 #define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
135 #define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
136 #define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
137 #define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
138 #define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
139 #define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
140 #define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
141 #define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
142 #define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
143 #define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
144 #define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
145
146 /*-----------------------------------------------------------------------------+
147 | SDRAM TR0 Options
148 +-----------------------------------------------------------------------------*/
149 #define SDRAM_TR0_SDWR_MASK 0x80000000
150 #define SDRAM_TR0_SDWR_2_CLK 0x00000000
151 #define SDRAM_TR0_SDWR_3_CLK 0x80000000
152 #define SDRAM_TR0_SDWD_MASK 0x40000000
153 #define SDRAM_TR0_SDWD_0_CLK 0x00000000
154 #define SDRAM_TR0_SDWD_1_CLK 0x40000000
155 #define SDRAM_TR0_SDCL_MASK 0x01800000
156 #define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
157 #define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
158 #define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
159 #define SDRAM_TR0_SDPA_MASK 0x000C0000
160 #define SDRAM_TR0_SDPA_2_CLK 0x00040000
161 #define SDRAM_TR0_SDPA_3_CLK 0x00080000
162 #define SDRAM_TR0_SDPA_4_CLK 0x000C0000
163 #define SDRAM_TR0_SDCP_MASK 0x00030000
164 #define SDRAM_TR0_SDCP_2_CLK 0x00000000
165 #define SDRAM_TR0_SDCP_3_CLK 0x00010000
166 #define SDRAM_TR0_SDCP_4_CLK 0x00020000
167 #define SDRAM_TR0_SDCP_5_CLK 0x00030000
168 #define SDRAM_TR0_SDLD_MASK 0x0000C000
169 #define SDRAM_TR0_SDLD_1_CLK 0x00000000
170 #define SDRAM_TR0_SDLD_2_CLK 0x00004000
171 #define SDRAM_TR0_SDRA_MASK 0x0000001C
172 #define SDRAM_TR0_SDRA_6_CLK 0x00000000
173 #define SDRAM_TR0_SDRA_7_CLK 0x00000004
174 #define SDRAM_TR0_SDRA_8_CLK 0x00000008
175 #define SDRAM_TR0_SDRA_9_CLK 0x0000000C
176 #define SDRAM_TR0_SDRA_10_CLK 0x00000010
177 #define SDRAM_TR0_SDRA_11_CLK 0x00000014
178 #define SDRAM_TR0_SDRA_12_CLK 0x00000018
179 #define SDRAM_TR0_SDRA_13_CLK 0x0000001C
180 #define SDRAM_TR0_SDRD_MASK 0x00000003
181 #define SDRAM_TR0_SDRD_2_CLK 0x00000001
182 #define SDRAM_TR0_SDRD_3_CLK 0x00000002
183 #define SDRAM_TR0_SDRD_4_CLK 0x00000003
184
185 /*-----------------------------------------------------------------------------+
186 | SDRAM TR1 Options
187 +-----------------------------------------------------------------------------*/
188 #define SDRAM_TR1_RDSS_MASK 0xC0000000
189 #define SDRAM_TR1_RDSS_TR0 0x00000000
190 #define SDRAM_TR1_RDSS_TR1 0x40000000
191 #define SDRAM_TR1_RDSS_TR2 0x80000000
192 #define SDRAM_TR1_RDSS_TR3 0xC0000000
193 #define SDRAM_TR1_RDSL_MASK 0x00C00000
194 #define SDRAM_TR1_RDSL_STAGE1 0x00000000
195 #define SDRAM_TR1_RDSL_STAGE2 0x00400000
196 #define SDRAM_TR1_RDSL_STAGE3 0x00800000
197 #define SDRAM_TR1_RDCD_MASK 0x00000800
198 #define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
199 #define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
200 #define SDRAM_TR1_RDCT_MASK 0x000001FF
201 #define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
202 #define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
203 #define SDRAM_TR1_RDCT_MIN 0x00000000
204 #define SDRAM_TR1_RDCT_MAX 0x000001FF
205
206 /*-----------------------------------------------------------------------------+
207 | SDRAM WDDCTR Options
208 +-----------------------------------------------------------------------------*/
209 #define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
210 #define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
211 #define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
212 #define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
213 #define SDRAM_WDDCTR_DCD_MASK 0x000001FF
214
215 /*-----------------------------------------------------------------------------+
216 | SDRAM CLKTR Options
217 +-----------------------------------------------------------------------------*/
218 #define SDRAM_CLKTR_CLKP_MASK 0xC0000000
219 #define SDRAM_CLKTR_CLKP_0DEG 0x00000000
220 #define SDRAM_CLKTR_CLKP_90DEG 0x40000000
221 #define SDRAM_CLKTR_CLKP_180DEG 0x80000000
222 #define SDRAM_CLKTR_DCDT_MASK 0x000001FF
223
224 /*-----------------------------------------------------------------------------+
225 | SDRAM DLYCAL Options
226 +-----------------------------------------------------------------------------*/
227 #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
228 #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
229 #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
230
231 /*-----------------------------------------------------------------------------+
232 | General Definition
233 +-----------------------------------------------------------------------------*/
234 #define DEFAULT_SPD_ADDR1 0x53
235 #define DEFAULT_SPD_ADDR2 0x52
236 #define MAXBANKS 4 /* at most 4 dimm banks */
237 #define MAX_SPD_BYTES 256
238 #define NUMHALFCYCLES 4
239 #define NUMMEMTESTS 8
240 #define NUMMEMWORDS 8
241 #define MAXBXCR 4
242 #define TRUE 1
243 #define FALSE 0
244
245 /*
246 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
247 * region. Right now the cache should still be disabled in U-Boot because of the
248 * EMAC driver, that need it's buffer descriptor to be located in non cached
249 * memory.
250 *
251 * If at some time this restriction doesn't apply anymore, just define
252 * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
253 * everything correctly.
254 */
255 #ifdef CFG_ENABLE_SDRAM_CACHE
256 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
257 #else
258 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
259 #endif
260
261 /* bank_parms is used to sort the bank sizes by descending order */
262 struct bank_param {
263 unsigned long cr;
264 unsigned long bank_size_bytes;
265 };
266
267 typedef struct bank_param BANKPARMS;
268
269 #ifdef CFG_SIMULATE_SPD_EEPROM
270 extern unsigned char cfg_simulate_spd_eeprom[128];
271 #endif
272 void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
273
274 static unsigned char spd_read(uchar chip, uint addr);
275 static void get_spd_info(unsigned long *dimm_populated,
276 unsigned char *iic0_dimm_addr,
277 unsigned long num_dimm_banks);
278 static void check_mem_type(unsigned long *dimm_populated,
279 unsigned char *iic0_dimm_addr,
280 unsigned long num_dimm_banks);
281 static void check_volt_type(unsigned long *dimm_populated,
282 unsigned char *iic0_dimm_addr,
283 unsigned long num_dimm_banks);
284 static void program_cfg0(unsigned long *dimm_populated,
285 unsigned char *iic0_dimm_addr,
286 unsigned long num_dimm_banks);
287 static void program_cfg1(unsigned long *dimm_populated,
288 unsigned char *iic0_dimm_addr,
289 unsigned long num_dimm_banks);
290 static void program_rtr(unsigned long *dimm_populated,
291 unsigned char *iic0_dimm_addr,
292 unsigned long num_dimm_banks);
293 static void program_tr0(unsigned long *dimm_populated,
294 unsigned char *iic0_dimm_addr,
295 unsigned long num_dimm_banks);
296 static void program_tr1(void);
297
298 #ifdef CONFIG_DDR_ECC
299 static void program_ecc(unsigned long num_bytes);
300 #endif
301
302 static unsigned long program_bxcr(unsigned long *dimm_populated,
303 unsigned char *iic0_dimm_addr,
304 unsigned long num_dimm_banks);
305
306 /*
307 * This function is reading data from the DIMM module EEPROM over the SPD bus
308 * and uses that to program the sdram controller.
309 *
310 * This works on boards that has the same schematics that the AMCC walnut has.
311 *
312 * BUG: Don't handle ECC memory
313 * BUG: A few values in the TR register is currently hardcoded
314 */
315 long int spd_sdram(void) {
316 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
317 unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
318 unsigned long total_size;
319 unsigned long cfg0;
320 unsigned long mcsts;
321 unsigned long num_dimm_banks; /* on board dimm banks */
322
323 num_dimm_banks = sizeof(iic0_dimm_addr);
324
325 /*
326 * Make sure I2C controller is initialized
327 * before continuing.
328 */
329 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
330
331 /*
332 * Read the SPD information using I2C interface. Check to see if the
333 * DIMM slots are populated.
334 */
335 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
336
337 /*
338 * Check the memory type for the dimms plugged.
339 */
340 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
341
342 /*
343 * Check the voltage type for the dimms plugged.
344 */
345 check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
346
347 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
348 /*
349 * Soft-reset SDRAM controller.
350 */
351 mtsdr(sdr_srst, SDR0_SRST_DMC);
352 mtsdr(sdr_srst, 0x00000000);
353 #endif
354
355 /*
356 * program 440GP SDRAM controller options (SDRAM0_CFG0)
357 */
358 program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
359
360 /*
361 * program 440GP SDRAM controller options (SDRAM0_CFG1)
362 */
363 program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
364
365 /*
366 * program SDRAM refresh register (SDRAM0_RTR)
367 */
368 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
369
370 /*
371 * program SDRAM Timing Register 0 (SDRAM0_TR0)
372 */
373 program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
374
375 /*
376 * program the BxCR registers to find out total sdram installed
377 */
378 total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
379 num_dimm_banks);
380
381 #ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
382 /* and program tlb entries for this size (dynamic) */
383 program_tlb(0, total_size, MY_TLB_WORD2_I_ENABLE);
384 #endif
385
386 /*
387 * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
388 */
389 mtsdram(mem_clktr, 0x40000000);
390
391 /*
392 * delay to ensure 200 usec has elapsed
393 */
394 udelay(400);
395
396 /*
397 * enable the memory controller
398 */
399 mfsdram(mem_cfg0, cfg0);
400 mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
401
402 /*
403 * wait for SDRAM_CFG0_DC_EN to complete
404 */
405 while (1) {
406 mfsdram(mem_mcsts, mcsts);
407 if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
408 break;
409 }
410
411 /*
412 * program SDRAM Timing Register 1, adding some delays
413 */
414 program_tr1();
415
416 #ifdef CONFIG_DDR_ECC
417 /*
418 * If ecc is enabled, initialize the parity bits.
419 */
420 program_ecc(total_size);
421 #endif
422
423 return total_size;
424 }
425
426 static unsigned char spd_read(uchar chip, uint addr)
427 {
428 unsigned char data[2];
429
430 #ifdef CFG_SIMULATE_SPD_EEPROM
431 if (chip == CFG_SIMULATE_SPD_EEPROM) {
432 /*
433 * Onboard spd eeprom requested -> simulate values
434 */
435 return cfg_simulate_spd_eeprom[addr];
436 }
437 #endif /* CFG_SIMULATE_SPD_EEPROM */
438
439 if (i2c_probe(chip) == 0) {
440 if (i2c_read(chip, addr, 1, data, 1) == 0) {
441 return data[0];
442 }
443 }
444
445 return 0;
446 }
447
448 static void get_spd_info(unsigned long *dimm_populated,
449 unsigned char *iic0_dimm_addr,
450 unsigned long num_dimm_banks)
451 {
452 unsigned long dimm_num;
453 unsigned long dimm_found;
454 unsigned char num_of_bytes;
455 unsigned char total_size;
456
457 dimm_found = FALSE;
458 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
459 num_of_bytes = 0;
460 total_size = 0;
461
462 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
463 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
464
465 if ((num_of_bytes != 0) && (total_size != 0)) {
466 dimm_populated[dimm_num] = TRUE;
467 dimm_found = TRUE;
468 debug("DIMM slot %lu: populated\n", dimm_num);
469 } else {
470 dimm_populated[dimm_num] = FALSE;
471 debug("DIMM slot %lu: Not populated\n", dimm_num);
472 }
473 }
474
475 if (dimm_found == FALSE) {
476 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
477 HANG();
478 }
479 }
480
481 static void check_mem_type(unsigned long *dimm_populated,
482 unsigned char *iic0_dimm_addr,
483 unsigned long num_dimm_banks)
484 {
485 unsigned long dimm_num;
486 unsigned char dimm_type;
487
488 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
489 if (dimm_populated[dimm_num] == TRUE) {
490 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
491 switch (dimm_type) {
492 case 7:
493 debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
494 break;
495 default:
496 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
497 dimm_num);
498 printf("Only DDR SDRAM DIMMs are supported.\n");
499 printf("Replace the DIMM module with a supported DIMM.\n\n");
500 HANG();
501 break;
502 }
503 }
504 }
505 }
506
507 static void check_volt_type(unsigned long *dimm_populated,
508 unsigned char *iic0_dimm_addr,
509 unsigned long num_dimm_banks)
510 {
511 unsigned long dimm_num;
512 unsigned long voltage_type;
513
514 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
515 if (dimm_populated[dimm_num] == TRUE) {
516 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
517 if (voltage_type != 0x04) {
518 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
519 dimm_num);
520 HANG();
521 } else {
522 debug("DIMM %lu voltage level supported.\n", dimm_num);
523 }
524 break;
525 }
526 }
527 }
528
529 static void program_cfg0(unsigned long *dimm_populated,
530 unsigned char *iic0_dimm_addr,
531 unsigned long num_dimm_banks)
532 {
533 unsigned long dimm_num;
534 unsigned long cfg0;
535 unsigned long ecc_enabled;
536 unsigned char ecc;
537 unsigned char attributes;
538 unsigned long data_width;
539 unsigned long dimm_32bit;
540 unsigned long dimm_64bit;
541
542 /*
543 * get Memory Controller Options 0 data
544 */
545 mfsdram(mem_cfg0, cfg0);
546
547 /*
548 * clear bits
549 */
550 cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
551 SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
552 SDRAM_CFG0_DMWD_MASK |
553 SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
554
555
556 /*
557 * FIXME: assume the DDR SDRAMs in both banks are the same
558 */
559 ecc_enabled = TRUE;
560 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
561 if (dimm_populated[dimm_num] == TRUE) {
562 ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
563 if (ecc != 0x02) {
564 ecc_enabled = FALSE;
565 }
566
567 /*
568 * program Registered DIMM Enable
569 */
570 attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
571 if ((attributes & 0x02) != 0x00) {
572 cfg0 |= SDRAM_CFG0_RDEN;
573 }
574
575 /*
576 * program DDR SDRAM Data Width
577 */
578 data_width =
579 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
580 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
581 if (data_width == 64 || data_width == 72) {
582 dimm_64bit = TRUE;
583 cfg0 |= SDRAM_CFG0_DMWD_64;
584 } else if (data_width == 32 || data_width == 40) {
585 dimm_32bit = TRUE;
586 cfg0 |= SDRAM_CFG0_DMWD_32;
587 } else {
588 printf("WARNING: DIMM with datawidth of %lu bits.\n",
589 data_width);
590 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
591 HANG();
592 }
593 break;
594 }
595 }
596
597 /*
598 * program Memory Data Error Checking
599 */
600 if (ecc_enabled == TRUE) {
601 cfg0 |= SDRAM_CFG0_MCHK_GEN;
602 } else {
603 cfg0 |= SDRAM_CFG0_MCHK_NON;
604 }
605
606 /*
607 * program Page Management Unit (0 == enabled)
608 */
609 cfg0 &= ~SDRAM_CFG0_PMUD;
610
611 /*
612 * program Memory Controller Options 0
613 * Note: DCEN must be enabled after all DDR SDRAM controller
614 * configuration registers get initialized.
615 */
616 mtsdram(mem_cfg0, cfg0);
617 }
618
619 static void program_cfg1(unsigned long *dimm_populated,
620 unsigned char *iic0_dimm_addr,
621 unsigned long num_dimm_banks)
622 {
623 unsigned long cfg1;
624 mfsdram(mem_cfg1, cfg1);
625
626 /*
627 * Self-refresh exit, disable PM
628 */
629 cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
630
631 /*
632 * program Memory Controller Options 1
633 */
634 mtsdram(mem_cfg1, cfg1);
635 }
636
637 static void program_rtr(unsigned long *dimm_populated,
638 unsigned char *iic0_dimm_addr,
639 unsigned long num_dimm_banks)
640 {
641 unsigned long dimm_num;
642 unsigned long bus_period_x_10;
643 unsigned long refresh_rate = 0;
644 unsigned char refresh_rate_type;
645 unsigned long refresh_interval;
646 unsigned long sdram_rtr;
647 PPC440_SYS_INFO sys_info;
648
649 /*
650 * get the board info
651 */
652 get_sys_info(&sys_info);
653 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
654
655 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
656 if (dimm_populated[dimm_num] == TRUE) {
657 refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
658 switch (refresh_rate_type) {
659 case 0x00:
660 refresh_rate = 15625;
661 break;
662 case 0x01:
663 refresh_rate = 15625/4;
664 break;
665 case 0x02:
666 refresh_rate = 15625/2;
667 break;
668 case 0x03:
669 refresh_rate = 15626*2;
670 break;
671 case 0x04:
672 refresh_rate = 15625*4;
673 break;
674 case 0x05:
675 refresh_rate = 15625*8;
676 break;
677 default:
678 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
679 dimm_num);
680 printf("Replace the DIMM module with a supported DIMM.\n");
681 break;
682 }
683
684 break;
685 }
686 }
687
688 refresh_interval = refresh_rate * 10 / bus_period_x_10;
689 sdram_rtr = (refresh_interval & 0x3ff8) << 16;
690
691 /*
692 * program Refresh Timer Register (SDRAM0_RTR)
693 */
694 mtsdram(mem_rtr, sdram_rtr);
695 }
696
697 static void program_tr0(unsigned long *dimm_populated,
698 unsigned char *iic0_dimm_addr,
699 unsigned long num_dimm_banks)
700 {
701 unsigned long dimm_num;
702 unsigned long tr0;
703 unsigned char wcsbc;
704 unsigned char t_rp_ns;
705 unsigned char t_rcd_ns;
706 unsigned char t_ras_ns;
707 unsigned long t_rp_clk;
708 unsigned long t_ras_rcd_clk;
709 unsigned long t_rcd_clk;
710 unsigned long t_rfc_clk;
711 unsigned long plb_check;
712 unsigned char cas_bit;
713 unsigned long cas_index;
714 unsigned char cas_2_0_available;
715 unsigned char cas_2_5_available;
716 unsigned char cas_3_0_available;
717 unsigned long cycle_time_ns_x_10[3];
718 unsigned long tcyc_3_0_ns_x_10;
719 unsigned long tcyc_2_5_ns_x_10;
720 unsigned long tcyc_2_0_ns_x_10;
721 unsigned long tcyc_reg;
722 unsigned long bus_period_x_10;
723 PPC440_SYS_INFO sys_info;
724 unsigned long residue;
725
726 /*
727 * get the board info
728 */
729 get_sys_info(&sys_info);
730 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
731
732 /*
733 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
734 */
735 mfsdram(mem_tr0, tr0);
736 tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
737 SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
738 SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
739 SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
740
741 /*
742 * initialization
743 */
744 wcsbc = 0;
745 t_rp_ns = 0;
746 t_rcd_ns = 0;
747 t_ras_ns = 0;
748 cas_2_0_available = TRUE;
749 cas_2_5_available = TRUE;
750 cas_3_0_available = TRUE;
751 tcyc_2_0_ns_x_10 = 0;
752 tcyc_2_5_ns_x_10 = 0;
753 tcyc_3_0_ns_x_10 = 0;
754
755 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
756 if (dimm_populated[dimm_num] == TRUE) {
757 wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
758 t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
759 t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
760 t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
761 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
762
763 for (cas_index = 0; cas_index < 3; cas_index++) {
764 switch (cas_index) {
765 case 0:
766 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
767 break;
768 case 1:
769 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
770 break;
771 default:
772 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
773 break;
774 }
775
776 if ((tcyc_reg & 0x0F) >= 10) {
777 printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
778 dimm_num);
779 HANG();
780 }
781
782 cycle_time_ns_x_10[cas_index] =
783 (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
784 }
785
786 cas_index = 0;
787
788 if ((cas_bit & 0x80) != 0) {
789 cas_index += 3;
790 } else if ((cas_bit & 0x40) != 0) {
791 cas_index += 2;
792 } else if ((cas_bit & 0x20) != 0) {
793 cas_index += 1;
794 }
795
796 if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
797 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
798 cas_index++;
799 } else {
800 if (cas_index != 0) {
801 cas_index++;
802 }
803 cas_3_0_available = FALSE;
804 }
805
806 if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
807 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
808 cas_index++;
809 } else {
810 if (cas_index != 0) {
811 cas_index++;
812 }
813 cas_2_5_available = FALSE;
814 }
815
816 if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
817 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
818 cas_index++;
819 } else {
820 if (cas_index != 0) {
821 cas_index++;
822 }
823 cas_2_0_available = FALSE;
824 }
825
826 break;
827 }
828 }
829
830 /*
831 * Program SD_WR and SD_WCSBC fields
832 */
833 tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
834 switch (wcsbc) {
835 case 0:
836 tr0 |= SDRAM_TR0_SDWD_0_CLK;
837 break;
838 default:
839 tr0 |= SDRAM_TR0_SDWD_1_CLK;
840 break;
841 }
842
843 /*
844 * Program SD_CASL field
845 */
846 if ((cas_2_0_available == TRUE) &&
847 (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
848 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
849 } else if ((cas_2_5_available == TRUE) &&
850 (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
851 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
852 } else if ((cas_3_0_available == TRUE) &&
853 (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
854 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
855 } else {
856 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
857 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
858 printf("Make sure the PLB speed is within the supported range.\n");
859 HANG();
860 }
861
862 /*
863 * Calculate Trp in clock cycles and round up if necessary
864 * Program SD_PTA field
865 */
866 t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
867 plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
868 if (sys_info.freqPLB != plb_check) {
869 t_rp_clk++;
870 }
871 switch ((unsigned long)t_rp_clk) {
872 case 0:
873 case 1:
874 case 2:
875 tr0 |= SDRAM_TR0_SDPA_2_CLK;
876 break;
877 case 3:
878 tr0 |= SDRAM_TR0_SDPA_3_CLK;
879 break;
880 default:
881 tr0 |= SDRAM_TR0_SDPA_4_CLK;
882 break;
883 }
884
885 /*
886 * Program SD_CTP field
887 */
888 t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
889 plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
890 if (sys_info.freqPLB != plb_check) {
891 t_ras_rcd_clk++;
892 }
893 switch (t_ras_rcd_clk) {
894 case 0:
895 case 1:
896 case 2:
897 tr0 |= SDRAM_TR0_SDCP_2_CLK;
898 break;
899 case 3:
900 tr0 |= SDRAM_TR0_SDCP_3_CLK;
901 break;
902 case 4:
903 tr0 |= SDRAM_TR0_SDCP_4_CLK;
904 break;
905 default:
906 tr0 |= SDRAM_TR0_SDCP_5_CLK;
907 break;
908 }
909
910 /*
911 * Program SD_LDF field
912 */
913 tr0 |= SDRAM_TR0_SDLD_2_CLK;
914
915 /*
916 * Program SD_RFTA field
917 * FIXME tRFC hardcoded as 75 nanoseconds
918 */
919 t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
920 residue = sys_info.freqPLB % (ONE_BILLION / 75);
921 if (residue >= (ONE_BILLION / 150)) {
922 t_rfc_clk++;
923 }
924 switch (t_rfc_clk) {
925 case 0:
926 case 1:
927 case 2:
928 case 3:
929 case 4:
930 case 5:
931 case 6:
932 tr0 |= SDRAM_TR0_SDRA_6_CLK;
933 break;
934 case 7:
935 tr0 |= SDRAM_TR0_SDRA_7_CLK;
936 break;
937 case 8:
938 tr0 |= SDRAM_TR0_SDRA_8_CLK;
939 break;
940 case 9:
941 tr0 |= SDRAM_TR0_SDRA_9_CLK;
942 break;
943 case 10:
944 tr0 |= SDRAM_TR0_SDRA_10_CLK;
945 break;
946 case 11:
947 tr0 |= SDRAM_TR0_SDRA_11_CLK;
948 break;
949 case 12:
950 tr0 |= SDRAM_TR0_SDRA_12_CLK;
951 break;
952 default:
953 tr0 |= SDRAM_TR0_SDRA_13_CLK;
954 break;
955 }
956
957 /*
958 * Program SD_RCD field
959 */
960 t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
961 plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
962 if (sys_info.freqPLB != plb_check) {
963 t_rcd_clk++;
964 }
965 switch (t_rcd_clk) {
966 case 0:
967 case 1:
968 case 2:
969 tr0 |= SDRAM_TR0_SDRD_2_CLK;
970 break;
971 case 3:
972 tr0 |= SDRAM_TR0_SDRD_3_CLK;
973 break;
974 default:
975 tr0 |= SDRAM_TR0_SDRD_4_CLK;
976 break;
977 }
978
979 debug("tr0: %x\n", tr0);
980 mtsdram(mem_tr0, tr0);
981 }
982
983 static int short_mem_test(void)
984 {
985 unsigned long i, j;
986 unsigned long bxcr_num;
987 unsigned long *membase;
988 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
989 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
990 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
991 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
992 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
993 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
994 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
995 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
996 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
997 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
998 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
999 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
1000 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
1001 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
1002 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
1003 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
1004 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
1005
1006 for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1007 mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
1008 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
1009 /* Bank is enabled */
1010 membase = (unsigned long*)
1011 (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
1012
1013 /*
1014 * Run the short memory test
1015 */
1016 for (i = 0; i < NUMMEMTESTS; i++) {
1017 for (j = 0; j < NUMMEMWORDS; j++) {
1018 //printf("bank enabled base:%x\n", &membase[j]);
1019 membase[j] = test[i][j];
1020 ppcDcbf((unsigned long)&(membase[j]));
1021 }
1022
1023 for (j = 0; j < NUMMEMWORDS; j++) {
1024 if (membase[j] != test[i][j]) {
1025 ppcDcbf((unsigned long)&(membase[j]));
1026 return 0;
1027 }
1028 ppcDcbf((unsigned long)&(membase[j]));
1029 }
1030
1031 if (j < NUMMEMWORDS)
1032 return 0;
1033 }
1034
1035 /*
1036 * see if the rdclt value passed
1037 */
1038 if (i < NUMMEMTESTS)
1039 return 0;
1040 }
1041 }
1042
1043 return 1;
1044 }
1045
1046 static void program_tr1(void)
1047 {
1048 unsigned long tr0;
1049 unsigned long tr1;
1050 unsigned long cfg0;
1051 unsigned long ecc_temp;
1052 unsigned long dlycal;
1053 unsigned long dly_val;
1054 unsigned long k;
1055 unsigned long max_pass_length;
1056 unsigned long current_pass_length;
1057 unsigned long current_fail_length;
1058 unsigned long current_start;
1059 unsigned long rdclt;
1060 unsigned long rdclt_offset;
1061 long max_start;
1062 long max_end;
1063 long rdclt_average;
1064 unsigned char window_found;
1065 unsigned char fail_found;
1066 unsigned char pass_found;
1067 PPC440_SYS_INFO sys_info;
1068
1069 /*
1070 * get the board info
1071 */
1072 get_sys_info(&sys_info);
1073
1074 /*
1075 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1076 */
1077 mfsdram(mem_tr1, tr1);
1078 tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
1079 SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
1080
1081 mfsdram(mem_tr0, tr0);
1082 if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
1083 (sys_info.freqPLB > 100000000)) {
1084 tr1 |= SDRAM_TR1_RDSS_TR2;
1085 tr1 |= SDRAM_TR1_RDSL_STAGE3;
1086 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1087 } else {
1088 tr1 |= SDRAM_TR1_RDSS_TR1;
1089 tr1 |= SDRAM_TR1_RDSL_STAGE2;
1090 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1091 }
1092
1093 /*
1094 * save CFG0 ECC setting to a temporary variable and turn ECC off
1095 */
1096 mfsdram(mem_cfg0, cfg0);
1097 ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
1098 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
1099
1100 /*
1101 * get the delay line calibration register value
1102 */
1103 mfsdram(mem_dlycal, dlycal);
1104 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
1105
1106 max_pass_length = 0;
1107 max_start = 0;
1108 max_end = 0;
1109 current_pass_length = 0;
1110 current_fail_length = 0;
1111 current_start = 0;
1112 rdclt_offset = 0;
1113 window_found = FALSE;
1114 fail_found = FALSE;
1115 pass_found = FALSE;
1116 debug("Starting memory test ");
1117
1118 for (k = 0; k < NUMHALFCYCLES; k++) {
1119 for (rdclt = 0; rdclt < dly_val; rdclt++) {
1120 /*
1121 * Set the timing reg for the test.
1122 */
1123 mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
1124
1125 if (short_mem_test()) {
1126 if (fail_found == TRUE) {
1127 pass_found = TRUE;
1128 if (current_pass_length == 0) {
1129 current_start = rdclt_offset + rdclt;
1130 }
1131
1132 current_fail_length = 0;
1133 current_pass_length++;
1134
1135 if (current_pass_length > max_pass_length) {
1136 max_pass_length = current_pass_length;
1137 max_start = current_start;
1138 max_end = rdclt_offset + rdclt;
1139 }
1140 }
1141 } else {
1142 current_pass_length = 0;
1143 current_fail_length++;
1144
1145 if (current_fail_length >= (dly_val>>2)) {
1146 if (fail_found == FALSE) {
1147 fail_found = TRUE;
1148 } else if (pass_found == TRUE) {
1149 window_found = TRUE;
1150 break;
1151 }
1152 }
1153 }
1154 }
1155 debug(".");
1156
1157 if (window_found == TRUE) {
1158 break;
1159 }
1160
1161 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1162 rdclt_offset += dly_val;
1163 }
1164 debug("\n");
1165
1166 /*
1167 * make sure we find the window
1168 */
1169 if (window_found == FALSE) {
1170 printf("ERROR: Cannot determine a common read delay.\n");
1171 HANG();
1172 }
1173
1174 /*
1175 * restore the orignal ECC setting
1176 */
1177 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1178
1179 /*
1180 * set the SDRAM TR1 RDCD value
1181 */
1182 tr1 &= ~SDRAM_TR1_RDCD_MASK;
1183 if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1184 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1185 } else {
1186 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1187 }
1188
1189 /*
1190 * set the SDRAM TR1 RDCLT value
1191 */
1192 tr1 &= ~SDRAM_TR1_RDCT_MASK;
1193 while (max_end >= (dly_val << 1)) {
1194 max_end -= (dly_val << 1);
1195 max_start -= (dly_val << 1);
1196 }
1197
1198 rdclt_average = ((max_start + max_end) >> 1);
1199 if (rdclt_average >= 0x60)
1200 while (1)
1201 ;
1202
1203 if (rdclt_average < 0) {
1204 rdclt_average = 0;
1205 }
1206
1207 if (rdclt_average >= dly_val) {
1208 rdclt_average -= dly_val;
1209 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1210 }
1211 tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1212
1213 debug("tr1: %x\n", tr1);
1214
1215 /*
1216 * program SDRAM Timing Register 1 TR1
1217 */
1218 mtsdram(mem_tr1, tr1);
1219 }
1220
1221 static unsigned long program_bxcr(unsigned long *dimm_populated,
1222 unsigned char *iic0_dimm_addr,
1223 unsigned long num_dimm_banks)
1224 {
1225 unsigned long dimm_num;
1226 unsigned long bank_base_addr;
1227 unsigned long cr;
1228 unsigned long i;
1229 unsigned long j;
1230 unsigned long temp;
1231 unsigned char num_row_addr;
1232 unsigned char num_col_addr;
1233 unsigned char num_banks;
1234 unsigned char bank_size_id;
1235 unsigned long ctrl_bank_num[MAXBANKS];
1236 unsigned long bx_cr_num;
1237 unsigned long largest_size_index;
1238 unsigned long largest_size;
1239 unsigned long current_size_index;
1240 BANKPARMS bank_parms[MAXBXCR];
1241 unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
1242 unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
1243
1244 /*
1245 * Set the BxCR regs. First, wipe out the bank config registers.
1246 */
1247 for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1248 mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2));
1249 mtdcr(memcfgd, 0x00000000);
1250 bank_parms[bx_cr_num].bank_size_bytes = 0;
1251 }
1252
1253 #ifdef CONFIG_BAMBOO
1254 /*
1255 * This next section is hardware dependent and must be programmed
1256 * to match the hardware. For bamboo, the following holds...
1257 * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard)
1258 * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
1259 * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
1260 * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
1261 * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
1262 */
1263 ctrl_bank_num[0] = 0;
1264 ctrl_bank_num[1] = 1;
1265 ctrl_bank_num[2] = 3;
1266 #else
1267 /*
1268 * Ocotea, Ebony and the other IBM/AMCC eval boards have
1269 * 2 DIMM slots with each max 2 banks
1270 */
1271 ctrl_bank_num[0] = 0;
1272 ctrl_bank_num[1] = 2;
1273 #endif
1274
1275 /*
1276 * reset the bank_base address
1277 */
1278 bank_base_addr = CFG_SDRAM_BASE;
1279
1280 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1281 if (dimm_populated[dimm_num] == TRUE) {
1282 num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1283 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1284 num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
1285 bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1286 debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num,
1287 num_row_addr, num_col_addr, num_banks);
1288
1289 /*
1290 * Set the SDRAM0_BxCR regs
1291 */
1292 cr = 0;
1293 switch (bank_size_id) {
1294 case 0x02:
1295 cr |= SDRAM_BXCR_SDSZ_8;
1296 break;
1297 case 0x04:
1298 cr |= SDRAM_BXCR_SDSZ_16;
1299 break;
1300 case 0x08:
1301 cr |= SDRAM_BXCR_SDSZ_32;
1302 break;
1303 case 0x10:
1304 cr |= SDRAM_BXCR_SDSZ_64;
1305 break;
1306 case 0x20:
1307 cr |= SDRAM_BXCR_SDSZ_128;
1308 break;
1309 case 0x40:
1310 cr |= SDRAM_BXCR_SDSZ_256;
1311 break;
1312 case 0x80:
1313 cr |= SDRAM_BXCR_SDSZ_512;
1314 break;
1315 default:
1316 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1317 dimm_num);
1318 printf("ERROR: Unsupported value for the banksize: %d.\n",
1319 bank_size_id);
1320 printf("Replace the DIMM module with a supported DIMM.\n\n");
1321 HANG();
1322 }
1323
1324 switch (num_col_addr) {
1325 case 0x08:
1326 cr |= SDRAM_BXCR_SDAM_1;
1327 break;
1328 case 0x09:
1329 cr |= SDRAM_BXCR_SDAM_2;
1330 break;
1331 case 0x0A:
1332 cr |= SDRAM_BXCR_SDAM_3;
1333 break;
1334 case 0x0B:
1335 cr |= SDRAM_BXCR_SDAM_4;
1336 break;
1337 default:
1338 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1339 dimm_num);
1340 printf("ERROR: Unsupported value for number of "
1341 "column addresses: %d.\n", num_col_addr);
1342 printf("Replace the DIMM module with a supported DIMM.\n\n");
1343 HANG();
1344 }
1345
1346 /*
1347 * enable the bank
1348 */
1349 cr |= SDRAM_BXCR_SDBE;
1350
1351 for (i = 0; i < num_banks; i++) {
1352 bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
1353 (4 << 20) * bank_size_id;
1354 bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
1355 debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
1356 dimm_num, i, ctrl_bank_num[dimm_num]+i,
1357 bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
1358 }
1359 }
1360 }
1361
1362 /* Initialize sort tables */
1363 for (i = 0; i < MAXBXCR; i++) {
1364 sorted_bank_num[i] = i;
1365 sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
1366 }
1367
1368 for (i = 0; i < MAXBXCR-1; i++) {
1369 largest_size = sorted_bank_size[i];
1370 largest_size_index = 255;
1371
1372 /* Find the largest remaining value */
1373 for (j = i + 1; j < MAXBXCR; j++) {
1374 if (sorted_bank_size[j] > largest_size) {
1375 /* Save largest remaining value and its index */
1376 largest_size = sorted_bank_size[j];
1377 largest_size_index = j;
1378 }
1379 }
1380
1381 if (largest_size_index != 255) {
1382 /* Swap the current and largest values */
1383 current_size_index = sorted_bank_num[largest_size_index];
1384 sorted_bank_size[largest_size_index] = sorted_bank_size[i];
1385 sorted_bank_size[i] = largest_size;
1386 sorted_bank_num[largest_size_index] = sorted_bank_num[i];
1387 sorted_bank_num[i] = current_size_index;
1388 }
1389 }
1390
1391 /* Set the SDRAM0_BxCR regs thanks to sort tables */
1392 for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1393 if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
1394 mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2));
1395 temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
1396 SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
1397 temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
1398 bank_parms[sorted_bank_num[bx_cr_num]].cr;
1399 mtdcr(memcfgd, temp);
1400 bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
1401 debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp);
1402 }
1403 }
1404
1405 return(bank_base_addr);
1406 }
1407
1408 #ifdef CONFIG_DDR_ECC
1409 static void program_ecc(unsigned long num_bytes)
1410 {
1411 unsigned long bank_base_addr;
1412 unsigned long current_address;
1413 unsigned long end_address;
1414 unsigned long address_increment;
1415 unsigned long cfg0;
1416
1417 /*
1418 * get Memory Controller Options 0 data
1419 */
1420 mfsdram(mem_cfg0, cfg0);
1421
1422 /*
1423 * reset the bank_base address
1424 */
1425 bank_base_addr = CFG_SDRAM_BASE;
1426
1427 if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
1428 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN);
1429
1430 if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32)
1431 address_increment = 4;
1432 else
1433 address_increment = 8;
1434
1435 current_address = (unsigned long)(bank_base_addr);
1436 end_address = (unsigned long)(bank_base_addr) + num_bytes;
1437
1438 while (current_address < end_address) {
1439 *((unsigned long*)current_address) = 0x00000000;
1440 current_address += address_increment;
1441 }
1442
1443 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1444 SDRAM_CFG0_MCHK_CHK);
1445 }
1446 }
1447 #endif /* CONFIG_DDR_ECC */
1448 #endif /* CONFIG_SPD_EEPROM */
"Das U-Boot" Source Tree