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[PCS440EP] get rid of CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG
[people/ms/u-boot.git] / cpu / ppc4xx / 44x_spd_ddr2.c
1 /*
2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those are 440SP/SPe.
5 *
6 * (C) Copyright 2007
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * COPYRIGHT AMCC CORPORATION 2004
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 *
29 */
30
31 /* define DEBUG for debugging output (obviously ;-)) */
32 #if 0
33 #define DEBUG
34 #endif
35
36 #include <common.h>
37 #include <command.h>
38 #include <ppc4xx.h>
39 #include <i2c.h>
40 #include <asm/io.h>
41 #include <asm/processor.h>
42 #include <asm/mmu.h>
43
44 #if defined(CONFIG_SPD_EEPROM) && \
45 (defined(CONFIG_440SP) || defined(CONFIG_440SPE))
46
47 /*-----------------------------------------------------------------------------+
48 * Defines
49 *-----------------------------------------------------------------------------*/
50 #ifndef TRUE
51 #define TRUE 1
52 #endif
53 #ifndef FALSE
54 #define FALSE 0
55 #endif
56
57 #define SDRAM_DDR1 1
58 #define SDRAM_DDR2 2
59 #define SDRAM_NONE 0
60
61 #define MAXDIMMS 2
62 #define MAXRANKS 4
63 #define MAXBXCF 4
64 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
65
66 #define ONE_BILLION 1000000000
67
68 #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
69
70 #define CMD_NOP (7 << 19)
71 #define CMD_PRECHARGE (2 << 19)
72 #define CMD_REFRESH (1 << 19)
73 #define CMD_EMR (0 << 19)
74 #define CMD_READ (5 << 19)
75 #define CMD_WRITE (4 << 19)
76
77 #define SELECT_MR (0 << 16)
78 #define SELECT_EMR (1 << 16)
79 #define SELECT_EMR2 (2 << 16)
80 #define SELECT_EMR3 (3 << 16)
81
82 /* MR */
83 #define DLL_RESET 0x00000100
84
85 #define WRITE_RECOV_2 (1 << 9)
86 #define WRITE_RECOV_3 (2 << 9)
87 #define WRITE_RECOV_4 (3 << 9)
88 #define WRITE_RECOV_5 (4 << 9)
89 #define WRITE_RECOV_6 (5 << 9)
90
91 #define BURST_LEN_4 0x00000002
92
93 /* EMR */
94 #define ODT_0_OHM 0x00000000
95 #define ODT_50_OHM 0x00000044
96 #define ODT_75_OHM 0x00000004
97 #define ODT_150_OHM 0x00000040
98
99 #define ODS_FULL 0x00000000
100 #define ODS_REDUCED 0x00000002
101
102 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
103 #define ODT_EB0R (0x80000000 >> 8)
104 #define ODT_EB0W (0x80000000 >> 7)
105 #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
106 #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
107 #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
108
109 /* Defines for the Read Cycle Delay test */
110 #define NUMMEMTESTS 8
111 #define NUMMEMWORDS 8
112 #define NUMLOOPS 256 /* memory test loops */
113
114 #undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
115
116 /*
117 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
118 * region. Right now the cache should still be disabled in U-Boot because of the
119 * EMAC driver, that need it's buffer descriptor to be located in non cached
120 * memory.
121 *
122 * If at some time this restriction doesn't apply anymore, just define
123 * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
124 * everything correctly.
125 */
126 #ifdef CFG_ENABLE_SDRAM_CACHE
127 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
128 #else
129 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
130 #endif
131
132 /*
133 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
134 */
135 void __spd_ddr_init_hang (void)
136 {
137 hang ();
138 }
139 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
140
141
142 /* Private Structure Definitions */
143
144 /* enum only to ease code for cas latency setting */
145 typedef enum ddr_cas_id {
146 DDR_CAS_2 = 20,
147 DDR_CAS_2_5 = 25,
148 DDR_CAS_3 = 30,
149 DDR_CAS_4 = 40,
150 DDR_CAS_5 = 50
151 } ddr_cas_id_t;
152
153 /*-----------------------------------------------------------------------------+
154 * Prototypes
155 *-----------------------------------------------------------------------------*/
156 static unsigned long sdram_memsize(void);
157 void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
158 static void get_spd_info(unsigned long *dimm_populated,
159 unsigned char *iic0_dimm_addr,
160 unsigned long num_dimm_banks);
161 static void check_mem_type(unsigned long *dimm_populated,
162 unsigned char *iic0_dimm_addr,
163 unsigned long num_dimm_banks);
164 static void check_frequency(unsigned long *dimm_populated,
165 unsigned char *iic0_dimm_addr,
166 unsigned long num_dimm_banks);
167 static void check_rank_number(unsigned long *dimm_populated,
168 unsigned char *iic0_dimm_addr,
169 unsigned long num_dimm_banks);
170 static void check_voltage_type(unsigned long *dimm_populated,
171 unsigned char *iic0_dimm_addr,
172 unsigned long num_dimm_banks);
173 static void program_memory_queue(unsigned long *dimm_populated,
174 unsigned char *iic0_dimm_addr,
175 unsigned long num_dimm_banks);
176 static void program_codt(unsigned long *dimm_populated,
177 unsigned char *iic0_dimm_addr,
178 unsigned long num_dimm_banks);
179 static void program_mode(unsigned long *dimm_populated,
180 unsigned char *iic0_dimm_addr,
181 unsigned long num_dimm_banks,
182 ddr_cas_id_t *selected_cas,
183 int *write_recovery);
184 static void program_tr(unsigned long *dimm_populated,
185 unsigned char *iic0_dimm_addr,
186 unsigned long num_dimm_banks);
187 static void program_rtr(unsigned long *dimm_populated,
188 unsigned char *iic0_dimm_addr,
189 unsigned long num_dimm_banks);
190 static void program_bxcf(unsigned long *dimm_populated,
191 unsigned char *iic0_dimm_addr,
192 unsigned long num_dimm_banks);
193 static void program_copt1(unsigned long *dimm_populated,
194 unsigned char *iic0_dimm_addr,
195 unsigned long num_dimm_banks);
196 static void program_initplr(unsigned long *dimm_populated,
197 unsigned char *iic0_dimm_addr,
198 unsigned long num_dimm_banks,
199 ddr_cas_id_t selected_cas,
200 int write_recovery);
201 static unsigned long is_ecc_enabled(void);
202 #ifdef CONFIG_DDR_ECC
203 static void program_ecc(unsigned long *dimm_populated,
204 unsigned char *iic0_dimm_addr,
205 unsigned long num_dimm_banks,
206 unsigned long tlb_word2_i_value);
207 static void program_ecc_addr(unsigned long start_address,
208 unsigned long num_bytes,
209 unsigned long tlb_word2_i_value);
210 #endif
211 static void program_DQS_calibration(unsigned long *dimm_populated,
212 unsigned char *iic0_dimm_addr,
213 unsigned long num_dimm_banks);
214 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
215 static void test(void);
216 #else
217 static void DQS_calibration_process(void);
218 #endif
219 #if defined(DEBUG)
220 static void ppc440sp_sdram_register_dump(void);
221 #endif
222 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
223 void dcbz_area(u32 start_address, u32 num_bytes);
224 void dflush(void);
225
226 static u32 mfdcr_any(u32 dcr)
227 {
228 u32 val;
229
230 switch (dcr) {
231 case SDRAM_R0BAS + 0:
232 val = mfdcr(SDRAM_R0BAS + 0);
233 break;
234 case SDRAM_R0BAS + 1:
235 val = mfdcr(SDRAM_R0BAS + 1);
236 break;
237 case SDRAM_R0BAS + 2:
238 val = mfdcr(SDRAM_R0BAS + 2);
239 break;
240 case SDRAM_R0BAS + 3:
241 val = mfdcr(SDRAM_R0BAS + 3);
242 break;
243 default:
244 printf("DCR %d not defined in case statement!!!\n", dcr);
245 val = 0; /* just to satisfy the compiler */
246 }
247
248 return val;
249 }
250
251 static void mtdcr_any(u32 dcr, u32 val)
252 {
253 switch (dcr) {
254 case SDRAM_R0BAS + 0:
255 mtdcr(SDRAM_R0BAS + 0, val);
256 break;
257 case SDRAM_R0BAS + 1:
258 mtdcr(SDRAM_R0BAS + 1, val);
259 break;
260 case SDRAM_R0BAS + 2:
261 mtdcr(SDRAM_R0BAS + 2, val);
262 break;
263 case SDRAM_R0BAS + 3:
264 mtdcr(SDRAM_R0BAS + 3, val);
265 break;
266 default:
267 printf("DCR %d not defined in case statement!!!\n", dcr);
268 }
269 }
270
271 static unsigned char spd_read(uchar chip, uint addr)
272 {
273 unsigned char data[2];
274
275 if (i2c_probe(chip) == 0)
276 if (i2c_read(chip, addr, 1, data, 1) == 0)
277 return data[0];
278
279 return 0;
280 }
281
282 /*-----------------------------------------------------------------------------+
283 * sdram_memsize
284 *-----------------------------------------------------------------------------*/
285 static unsigned long sdram_memsize(void)
286 {
287 unsigned long mem_size;
288 unsigned long mcopt2;
289 unsigned long mcstat;
290 unsigned long mb0cf;
291 unsigned long sdsz;
292 unsigned long i;
293
294 mem_size = 0;
295
296 mfsdram(SDRAM_MCOPT2, mcopt2);
297 mfsdram(SDRAM_MCSTAT, mcstat);
298
299 /* DDR controller must be enabled and not in self-refresh. */
300 /* Otherwise memsize is zero. */
301 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
302 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
303 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
304 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
305 for (i = 0; i < MAXBXCF; i++) {
306 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
307 /* Banks enabled */
308 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
309 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
310
311 switch(sdsz) {
312 case SDRAM_RXBAS_SDSZ_8:
313 mem_size+=8;
314 break;
315 case SDRAM_RXBAS_SDSZ_16:
316 mem_size+=16;
317 break;
318 case SDRAM_RXBAS_SDSZ_32:
319 mem_size+=32;
320 break;
321 case SDRAM_RXBAS_SDSZ_64:
322 mem_size+=64;
323 break;
324 case SDRAM_RXBAS_SDSZ_128:
325 mem_size+=128;
326 break;
327 case SDRAM_RXBAS_SDSZ_256:
328 mem_size+=256;
329 break;
330 case SDRAM_RXBAS_SDSZ_512:
331 mem_size+=512;
332 break;
333 case SDRAM_RXBAS_SDSZ_1024:
334 mem_size+=1024;
335 break;
336 case SDRAM_RXBAS_SDSZ_2048:
337 mem_size+=2048;
338 break;
339 case SDRAM_RXBAS_SDSZ_4096:
340 mem_size+=4096;
341 break;
342 default:
343 mem_size=0;
344 break;
345 }
346 }
347 }
348 }
349
350 mem_size *= 1024 * 1024;
351 return(mem_size);
352 }
353
354 /*-----------------------------------------------------------------------------+
355 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
356 * Note: This routine runs from flash with a stack set up in the chip's
357 * sram space. It is important that the routine does not require .sbss, .bss or
358 * .data sections. It also cannot call routines that require these sections.
359 *-----------------------------------------------------------------------------*/
360 /*-----------------------------------------------------------------------------
361 * Function: initdram
362 * Description: Configures SDRAM memory banks for DDR operation.
363 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
364 * via the IIC bus and then configures the DDR SDRAM memory
365 * banks appropriately. If Auto Memory Configuration is
366 * not used, it is assumed that no DIMM is plugged
367 *-----------------------------------------------------------------------------*/
368 long int initdram(int board_type)
369 {
370 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
371 unsigned char spd0[MAX_SPD_BYTES];
372 unsigned char spd1[MAX_SPD_BYTES];
373 unsigned char *dimm_spd[MAXDIMMS];
374 unsigned long dimm_populated[MAXDIMMS];
375 unsigned long num_dimm_banks; /* on board dimm banks */
376 unsigned long val;
377 ddr_cas_id_t selected_cas;
378 int write_recovery;
379 unsigned long dram_size = 0;
380
381 num_dimm_banks = sizeof(iic0_dimm_addr);
382
383 /*------------------------------------------------------------------
384 * Set up an array of SPD matrixes.
385 *-----------------------------------------------------------------*/
386 dimm_spd[0] = spd0;
387 dimm_spd[1] = spd1;
388
389 /*------------------------------------------------------------------
390 * Reset the DDR-SDRAM controller.
391 *-----------------------------------------------------------------*/
392 mtsdr(SDR0_SRST, (0x80000000 >> 10));
393 mtsdr(SDR0_SRST, 0x00000000);
394
395 /*
396 * Make sure I2C controller is initialized
397 * before continuing.
398 */
399
400 /* switch to correct I2C bus */
401 I2C_SET_BUS(CFG_SPD_BUS_NUM);
402 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
403
404 /*------------------------------------------------------------------
405 * Clear out the serial presence detect buffers.
406 * Perform IIC reads from the dimm. Fill in the spds.
407 * Check to see if the dimm slots are populated
408 *-----------------------------------------------------------------*/
409 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
410
411 /*------------------------------------------------------------------
412 * Check the memory type for the dimms plugged.
413 *-----------------------------------------------------------------*/
414 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
415
416 /*------------------------------------------------------------------
417 * Check the frequency supported for the dimms plugged.
418 *-----------------------------------------------------------------*/
419 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
420
421 /*------------------------------------------------------------------
422 * Check the total rank number.
423 *-----------------------------------------------------------------*/
424 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
425
426 /*------------------------------------------------------------------
427 * Check the voltage type for the dimms plugged.
428 *-----------------------------------------------------------------*/
429 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
430
431 /*------------------------------------------------------------------
432 * Program SDRAM controller options 2 register
433 * Except Enabling of the memory controller.
434 *-----------------------------------------------------------------*/
435 mfsdram(SDRAM_MCOPT2, val);
436 mtsdram(SDRAM_MCOPT2,
437 (val &
438 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
439 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
440 SDRAM_MCOPT2_ISIE_MASK))
441 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
442 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
443 SDRAM_MCOPT2_ISIE_ENABLE));
444
445 /*------------------------------------------------------------------
446 * Program SDRAM controller options 1 register
447 * Note: Does not enable the memory controller.
448 *-----------------------------------------------------------------*/
449 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
450
451 /*------------------------------------------------------------------
452 * Set the SDRAM Controller On Die Termination Register
453 *-----------------------------------------------------------------*/
454 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
455
456 /*------------------------------------------------------------------
457 * Program SDRAM refresh register.
458 *-----------------------------------------------------------------*/
459 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
460
461 /*------------------------------------------------------------------
462 * Program SDRAM mode register.
463 *-----------------------------------------------------------------*/
464 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
465 &selected_cas, &write_recovery);
466
467 /*------------------------------------------------------------------
468 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
469 *-----------------------------------------------------------------*/
470 mfsdram(SDRAM_WRDTR, val);
471 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
472 (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
473
474 /*------------------------------------------------------------------
475 * Set the SDRAM Clock Timing Register
476 *-----------------------------------------------------------------*/
477 mfsdram(SDRAM_CLKTR, val);
478 #ifdef CFG_44x_DDR2_CKTR_180
479 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_180_DEG_ADV);
480 #else
481 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
482 #endif
483
484 /*------------------------------------------------------------------
485 * Program the BxCF registers.
486 *-----------------------------------------------------------------*/
487 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
488
489 /*------------------------------------------------------------------
490 * Program SDRAM timing registers.
491 *-----------------------------------------------------------------*/
492 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
493
494 /*------------------------------------------------------------------
495 * Set the Extended Mode register
496 *-----------------------------------------------------------------*/
497 mfsdram(SDRAM_MEMODE, val);
498 mtsdram(SDRAM_MEMODE,
499 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
500 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
501 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
502 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
503
504 /*------------------------------------------------------------------
505 * Program Initialization preload registers.
506 *-----------------------------------------------------------------*/
507 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
508 selected_cas, write_recovery);
509
510 /*------------------------------------------------------------------
511 * Delay to ensure 200usec have elapsed since reset.
512 *-----------------------------------------------------------------*/
513 udelay(400);
514
515 /*------------------------------------------------------------------
516 * Set the memory queue core base addr.
517 *-----------------------------------------------------------------*/
518 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
519
520 /*------------------------------------------------------------------
521 * Program SDRAM controller options 2 register
522 * Enable the memory controller.
523 *-----------------------------------------------------------------*/
524 mfsdram(SDRAM_MCOPT2, val);
525 mtsdram(SDRAM_MCOPT2,
526 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
527 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
528 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
529
530 /*------------------------------------------------------------------
531 * Wait for SDRAM_CFG0_DC_EN to complete.
532 *-----------------------------------------------------------------*/
533 do {
534 mfsdram(SDRAM_MCSTAT, val);
535 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
536
537 /* get installed memory size */
538 dram_size = sdram_memsize();
539
540 /* and program tlb entries for this size (dynamic) */
541 program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE);
542
543 /*------------------------------------------------------------------
544 * DQS calibration.
545 *-----------------------------------------------------------------*/
546 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
547
548 #ifdef CONFIG_DDR_ECC
549 /*------------------------------------------------------------------
550 * If ecc is enabled, initialize the parity bits.
551 *-----------------------------------------------------------------*/
552 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE);
553 #endif
554
555 #ifdef DEBUG
556 ppc440sp_sdram_register_dump();
557 #endif
558
559 return dram_size;
560 }
561
562 static void get_spd_info(unsigned long *dimm_populated,
563 unsigned char *iic0_dimm_addr,
564 unsigned long num_dimm_banks)
565 {
566 unsigned long dimm_num;
567 unsigned long dimm_found;
568 unsigned char num_of_bytes;
569 unsigned char total_size;
570
571 dimm_found = FALSE;
572 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
573 num_of_bytes = 0;
574 total_size = 0;
575
576 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
577 debug("\nspd_read(0x%x) returned %d\n",
578 iic0_dimm_addr[dimm_num], num_of_bytes);
579 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
580 debug("spd_read(0x%x) returned %d\n",
581 iic0_dimm_addr[dimm_num], total_size);
582
583 if ((num_of_bytes != 0) && (total_size != 0)) {
584 dimm_populated[dimm_num] = TRUE;
585 dimm_found = TRUE;
586 debug("DIMM slot %lu: populated\n", dimm_num);
587 } else {
588 dimm_populated[dimm_num] = FALSE;
589 debug("DIMM slot %lu: Not populated\n", dimm_num);
590 }
591 }
592
593 if (dimm_found == FALSE) {
594 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
595 spd_ddr_init_hang ();
596 }
597 }
598
599 #ifdef CONFIG_ADD_RAM_INFO
600 void board_add_ram_info(int use_default)
601 {
602 PPC440_SYS_INFO board_cfg;
603 u32 val;
604
605 if (is_ecc_enabled())
606 puts(" (ECC");
607 else
608 puts(" (ECC not");
609
610 get_sys_info(&board_cfg);
611
612 mfsdr(SDR0_DDR0, val);
613 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
614 printf(" enabled, %d MHz", (val * 2) / 1000000);
615
616 mfsdram(SDRAM_MMODE, val);
617 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
618 printf(", CL%d)", val);
619 }
620 #endif
621
622 /*------------------------------------------------------------------
623 * For the memory DIMMs installed, this routine verifies that they
624 * really are DDR specific DIMMs.
625 *-----------------------------------------------------------------*/
626 static void check_mem_type(unsigned long *dimm_populated,
627 unsigned char *iic0_dimm_addr,
628 unsigned long num_dimm_banks)
629 {
630 unsigned long dimm_num;
631 unsigned long dimm_type;
632
633 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
634 if (dimm_populated[dimm_num] == TRUE) {
635 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
636 switch (dimm_type) {
637 case 1:
638 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
639 "slot %d.\n", (unsigned int)dimm_num);
640 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
641 printf("Replace the DIMM module with a supported DIMM.\n\n");
642 spd_ddr_init_hang ();
643 break;
644 case 2:
645 printf("ERROR: EDO DIMM detected in slot %d.\n",
646 (unsigned int)dimm_num);
647 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
648 printf("Replace the DIMM module with a supported DIMM.\n\n");
649 spd_ddr_init_hang ();
650 break;
651 case 3:
652 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
653 (unsigned int)dimm_num);
654 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
655 printf("Replace the DIMM module with a supported DIMM.\n\n");
656 spd_ddr_init_hang ();
657 break;
658 case 4:
659 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
660 (unsigned int)dimm_num);
661 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
662 printf("Replace the DIMM module with a supported DIMM.\n\n");
663 spd_ddr_init_hang ();
664 break;
665 case 5:
666 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
667 (unsigned int)dimm_num);
668 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
669 printf("Replace the DIMM module with a supported DIMM.\n\n");
670 spd_ddr_init_hang ();
671 break;
672 case 6:
673 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
674 (unsigned int)dimm_num);
675 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
676 printf("Replace the DIMM module with a supported DIMM.\n\n");
677 spd_ddr_init_hang ();
678 break;
679 case 7:
680 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
681 dimm_populated[dimm_num] = SDRAM_DDR1;
682 break;
683 case 8:
684 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
685 dimm_populated[dimm_num] = SDRAM_DDR2;
686 break;
687 default:
688 printf("ERROR: Unknown DIMM detected in slot %d.\n",
689 (unsigned int)dimm_num);
690 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
691 printf("Replace the DIMM module with a supported DIMM.\n\n");
692 spd_ddr_init_hang ();
693 break;
694 }
695 }
696 }
697 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
698 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
699 && (dimm_populated[dimm_num] != SDRAM_NONE)
700 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
701 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
702 spd_ddr_init_hang ();
703 }
704 }
705 }
706
707 /*------------------------------------------------------------------
708 * For the memory DIMMs installed, this routine verifies that
709 * frequency previously calculated is supported.
710 *-----------------------------------------------------------------*/
711 static void check_frequency(unsigned long *dimm_populated,
712 unsigned char *iic0_dimm_addr,
713 unsigned long num_dimm_banks)
714 {
715 unsigned long dimm_num;
716 unsigned long tcyc_reg;
717 unsigned long cycle_time;
718 unsigned long calc_cycle_time;
719 unsigned long sdram_freq;
720 unsigned long sdr_ddrpll;
721 PPC440_SYS_INFO board_cfg;
722
723 /*------------------------------------------------------------------
724 * Get the board configuration info.
725 *-----------------------------------------------------------------*/
726 get_sys_info(&board_cfg);
727
728 mfsdr(SDR0_DDR0, sdr_ddrpll);
729 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
730
731 /*
732 * calc_cycle_time is calculated from DDR frequency set by board/chip
733 * and is expressed in multiple of 10 picoseconds
734 * to match the way DIMM cycle time is calculated below.
735 */
736 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
737
738 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
739 if (dimm_populated[dimm_num] != SDRAM_NONE) {
740 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
741 /*
742 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
743 * the higher order nibble (bits 4-7) designates the cycle time
744 * to a granularity of 1ns;
745 * the value presented by the lower order nibble (bits 0-3)
746 * has a granularity of .1ns and is added to the value designated
747 * by the higher nibble. In addition, four lines of the lower order
748 * nibble are assigned to support +.25,+.33, +.66 and +.75.
749 */
750 /* Convert from hex to decimal */
751 if ((tcyc_reg & 0x0F) == 0x0D)
752 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
753 else if ((tcyc_reg & 0x0F) == 0x0C)
754 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
755 else if ((tcyc_reg & 0x0F) == 0x0B)
756 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
757 else if ((tcyc_reg & 0x0F) == 0x0A)
758 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
759 else
760 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
761 ((tcyc_reg & 0x0F)*10);
762 debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
763
764 if (cycle_time > (calc_cycle_time + 10)) {
765 /*
766 * the provided sdram cycle_time is too small
767 * for the available DIMM cycle_time.
768 * The additionnal 100ps is here to accept a small incertainty.
769 */
770 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
771 "slot %d \n while calculated cycle time is %d ps.\n",
772 (unsigned int)(cycle_time*10),
773 (unsigned int)dimm_num,
774 (unsigned int)(calc_cycle_time*10));
775 printf("Replace the DIMM, or change DDR frequency via "
776 "strapping bits.\n\n");
777 spd_ddr_init_hang ();
778 }
779 }
780 }
781 }
782
783 /*------------------------------------------------------------------
784 * For the memory DIMMs installed, this routine verifies two
785 * ranks/banks maximum are availables.
786 *-----------------------------------------------------------------*/
787 static void check_rank_number(unsigned long *dimm_populated,
788 unsigned char *iic0_dimm_addr,
789 unsigned long num_dimm_banks)
790 {
791 unsigned long dimm_num;
792 unsigned long dimm_rank;
793 unsigned long total_rank = 0;
794
795 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
796 if (dimm_populated[dimm_num] != SDRAM_NONE) {
797 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
798 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
799 dimm_rank = (dimm_rank & 0x0F) +1;
800 else
801 dimm_rank = dimm_rank & 0x0F;
802
803
804 if (dimm_rank > MAXRANKS) {
805 printf("ERROR: DRAM DIMM detected with %d ranks in "
806 "slot %d is not supported.\n", dimm_rank, dimm_num);
807 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
808 printf("Replace the DIMM module with a supported DIMM.\n\n");
809 spd_ddr_init_hang ();
810 } else
811 total_rank += dimm_rank;
812 }
813 if (total_rank > MAXRANKS) {
814 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
815 "for all slots.\n", (unsigned int)total_rank);
816 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
817 printf("Remove one of the DIMM modules.\n\n");
818 spd_ddr_init_hang ();
819 }
820 }
821 }
822
823 /*------------------------------------------------------------------
824 * only support 2.5V modules.
825 * This routine verifies this.
826 *-----------------------------------------------------------------*/
827 static void check_voltage_type(unsigned long *dimm_populated,
828 unsigned char *iic0_dimm_addr,
829 unsigned long num_dimm_banks)
830 {
831 unsigned long dimm_num;
832 unsigned long voltage_type;
833
834 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
835 if (dimm_populated[dimm_num] != SDRAM_NONE) {
836 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
837 switch (voltage_type) {
838 case 0x00:
839 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
840 printf("This DIMM is 5.0 Volt/TTL.\n");
841 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
842 (unsigned int)dimm_num);
843 spd_ddr_init_hang ();
844 break;
845 case 0x01:
846 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
847 printf("This DIMM is LVTTL.\n");
848 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
849 (unsigned int)dimm_num);
850 spd_ddr_init_hang ();
851 break;
852 case 0x02:
853 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
854 printf("This DIMM is 1.5 Volt.\n");
855 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
856 (unsigned int)dimm_num);
857 spd_ddr_init_hang ();
858 break;
859 case 0x03:
860 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
861 printf("This DIMM is 3.3 Volt/TTL.\n");
862 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
863 (unsigned int)dimm_num);
864 spd_ddr_init_hang ();
865 break;
866 case 0x04:
867 /* 2.5 Voltage only for DDR1 */
868 break;
869 case 0x05:
870 /* 1.8 Voltage only for DDR2 */
871 break;
872 default:
873 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
874 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
875 (unsigned int)dimm_num);
876 spd_ddr_init_hang ();
877 break;
878 }
879 }
880 }
881 }
882
883 /*-----------------------------------------------------------------------------+
884 * program_copt1.
885 *-----------------------------------------------------------------------------*/
886 static void program_copt1(unsigned long *dimm_populated,
887 unsigned char *iic0_dimm_addr,
888 unsigned long num_dimm_banks)
889 {
890 unsigned long dimm_num;
891 unsigned long mcopt1;
892 unsigned long ecc_enabled;
893 unsigned long ecc = 0;
894 unsigned long data_width = 0;
895 unsigned long dimm_32bit;
896 unsigned long dimm_64bit;
897 unsigned long registered = 0;
898 unsigned long attribute = 0;
899 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
900 unsigned long bankcount;
901 unsigned long ddrtype;
902 unsigned long val;
903
904 #ifdef CONFIG_DDR_ECC
905 ecc_enabled = TRUE;
906 #else
907 ecc_enabled = FALSE;
908 #endif
909 dimm_32bit = FALSE;
910 dimm_64bit = FALSE;
911 buf0 = FALSE;
912 buf1 = FALSE;
913
914 /*------------------------------------------------------------------
915 * Set memory controller options reg 1, SDRAM_MCOPT1.
916 *-----------------------------------------------------------------*/
917 mfsdram(SDRAM_MCOPT1, val);
918 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
919 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
920 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
921 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
922 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
923 SDRAM_MCOPT1_DREF_MASK);
924
925 mcopt1 |= SDRAM_MCOPT1_QDEP;
926 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
927 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
928 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
929 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
930 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
931
932 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
933 if (dimm_populated[dimm_num] != SDRAM_NONE) {
934 /* test ecc support */
935 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
936 if (ecc != 0x02) /* ecc not supported */
937 ecc_enabled = FALSE;
938
939 /* test bank count */
940 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
941 if (bankcount == 0x04) /* bank count = 4 */
942 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
943 else /* bank count = 8 */
944 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
945
946 /* test DDR type */
947 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
948 /* test for buffered/unbuffered, registered, differential clocks */
949 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
950 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
951
952 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
953 if (dimm_num == 0) {
954 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
955 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
956 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
957 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
958 if (registered == 1) { /* DDR2 always buffered */
959 /* TODO: what about above comments ? */
960 mcopt1 |= SDRAM_MCOPT1_RDEN;
961 buf0 = TRUE;
962 } else {
963 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
964 if ((attribute & 0x02) == 0x00) {
965 /* buffered not supported */
966 buf0 = FALSE;
967 } else {
968 mcopt1 |= SDRAM_MCOPT1_RDEN;
969 buf0 = TRUE;
970 }
971 }
972 }
973 else if (dimm_num == 1) {
974 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
975 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
976 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
977 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
978 if (registered == 1) {
979 /* DDR2 always buffered */
980 mcopt1 |= SDRAM_MCOPT1_RDEN;
981 buf1 = TRUE;
982 } else {
983 if ((attribute & 0x02) == 0x00) {
984 /* buffered not supported */
985 buf1 = FALSE;
986 } else {
987 mcopt1 |= SDRAM_MCOPT1_RDEN;
988 buf1 = TRUE;
989 }
990 }
991 }
992
993 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
994 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
995 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
996
997 switch (data_width) {
998 case 72:
999 case 64:
1000 dimm_64bit = TRUE;
1001 break;
1002 case 40:
1003 case 32:
1004 dimm_32bit = TRUE;
1005 break;
1006 default:
1007 printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
1008 data_width);
1009 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1010 break;
1011 }
1012 }
1013 }
1014
1015 /* verify matching properties */
1016 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1017 if (buf0 != buf1) {
1018 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1019 spd_ddr_init_hang ();
1020 }
1021 }
1022
1023 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1024 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1025 spd_ddr_init_hang ();
1026 }
1027 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1028 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1029 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1030 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1031 } else {
1032 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1033 spd_ddr_init_hang ();
1034 }
1035
1036 if (ecc_enabled == TRUE)
1037 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1038 else
1039 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1040
1041 mtsdram(SDRAM_MCOPT1, mcopt1);
1042 }
1043
1044 /*-----------------------------------------------------------------------------+
1045 * program_codt.
1046 *-----------------------------------------------------------------------------*/
1047 static void program_codt(unsigned long *dimm_populated,
1048 unsigned char *iic0_dimm_addr,
1049 unsigned long num_dimm_banks)
1050 {
1051 unsigned long codt;
1052 unsigned long modt0 = 0;
1053 unsigned long modt1 = 0;
1054 unsigned long modt2 = 0;
1055 unsigned long modt3 = 0;
1056 unsigned char dimm_num;
1057 unsigned char dimm_rank;
1058 unsigned char total_rank = 0;
1059 unsigned char total_dimm = 0;
1060 unsigned char dimm_type = 0;
1061 unsigned char firstSlot = 0;
1062
1063 /*------------------------------------------------------------------
1064 * Set the SDRAM Controller On Die Termination Register
1065 *-----------------------------------------------------------------*/
1066 mfsdram(SDRAM_CODT, codt);
1067 codt |= (SDRAM_CODT_IO_NMODE
1068 & (~SDRAM_CODT_DQS_SINGLE_END
1069 & ~SDRAM_CODT_CKSE_SINGLE_END
1070 & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1071 & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1072
1073 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1074 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1075 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1076 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1077 dimm_rank = (dimm_rank & 0x0F) + 1;
1078 dimm_type = SDRAM_DDR2;
1079 } else {
1080 dimm_rank = dimm_rank & 0x0F;
1081 dimm_type = SDRAM_DDR1;
1082 }
1083
1084 total_rank += dimm_rank;
1085 total_dimm++;
1086 if ((dimm_num == 0) && (total_dimm == 1))
1087 firstSlot = TRUE;
1088 else
1089 firstSlot = FALSE;
1090 }
1091 }
1092 if (dimm_type == SDRAM_DDR2) {
1093 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1094 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1095 if (total_rank == 1) {
1096 codt |= CALC_ODT_R(0);
1097 modt0 = CALC_ODT_W(0);
1098 modt1 = 0x00000000;
1099 modt2 = 0x00000000;
1100 modt3 = 0x00000000;
1101 }
1102 if (total_rank == 2) {
1103 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1104 modt0 = CALC_ODT_W(0);
1105 modt1 = CALC_ODT_W(0);
1106 modt2 = 0x00000000;
1107 modt3 = 0x00000000;
1108 }
1109 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1110 if (total_rank == 1) {
1111 codt |= CALC_ODT_R(2);
1112 modt0 = 0x00000000;
1113 modt1 = 0x00000000;
1114 modt2 = CALC_ODT_W(2);
1115 modt3 = 0x00000000;
1116 }
1117 if (total_rank == 2) {
1118 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1119 modt0 = 0x00000000;
1120 modt1 = 0x00000000;
1121 modt2 = CALC_ODT_W(2);
1122 modt3 = CALC_ODT_W(2);
1123 }
1124 }
1125 if (total_dimm == 2) {
1126 if (total_rank == 2) {
1127 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1128 modt0 = CALC_ODT_RW(2);
1129 modt1 = 0x00000000;
1130 modt2 = CALC_ODT_RW(0);
1131 modt3 = 0x00000000;
1132 }
1133 if (total_rank == 4) {
1134 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1135 CALC_ODT_R(2) | CALC_ODT_R(3);
1136 modt0 = CALC_ODT_RW(2);
1137 modt1 = 0x00000000;
1138 modt2 = CALC_ODT_RW(0);
1139 modt3 = 0x00000000;
1140 }
1141 }
1142 } else {
1143 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1144 modt0 = 0x00000000;
1145 modt1 = 0x00000000;
1146 modt2 = 0x00000000;
1147 modt3 = 0x00000000;
1148
1149 if (total_dimm == 1) {
1150 if (total_rank == 1)
1151 codt |= 0x00800000;
1152 if (total_rank == 2)
1153 codt |= 0x02800000;
1154 }
1155 if (total_dimm == 2) {
1156 if (total_rank == 2)
1157 codt |= 0x08800000;
1158 if (total_rank == 4)
1159 codt |= 0x2a800000;
1160 }
1161 }
1162
1163 debug("nb of dimm %d\n", total_dimm);
1164 debug("nb of rank %d\n", total_rank);
1165 if (total_dimm == 1)
1166 debug("dimm in slot %d\n", firstSlot);
1167
1168 mtsdram(SDRAM_CODT, codt);
1169 mtsdram(SDRAM_MODT0, modt0);
1170 mtsdram(SDRAM_MODT1, modt1);
1171 mtsdram(SDRAM_MODT2, modt2);
1172 mtsdram(SDRAM_MODT3, modt3);
1173 }
1174
1175 /*-----------------------------------------------------------------------------+
1176 * program_initplr.
1177 *-----------------------------------------------------------------------------*/
1178 static void program_initplr(unsigned long *dimm_populated,
1179 unsigned char *iic0_dimm_addr,
1180 unsigned long num_dimm_banks,
1181 ddr_cas_id_t selected_cas,
1182 int write_recovery)
1183 {
1184 u32 cas = 0;
1185 u32 odt = 0;
1186 u32 ods = 0;
1187 u32 mr;
1188 u32 wr;
1189 u32 emr;
1190 u32 emr2;
1191 u32 emr3;
1192 int dimm_num;
1193 int total_dimm = 0;
1194
1195 /******************************************************
1196 ** Assumption: if more than one DIMM, all DIMMs are the same
1197 ** as already checked in check_memory_type
1198 ******************************************************/
1199
1200 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1201 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1202 mtsdram(SDRAM_INITPLR1, 0x81900400);
1203 mtsdram(SDRAM_INITPLR2, 0x81810000);
1204 mtsdram(SDRAM_INITPLR3, 0xff800162);
1205 mtsdram(SDRAM_INITPLR4, 0x81900400);
1206 mtsdram(SDRAM_INITPLR5, 0x86080000);
1207 mtsdram(SDRAM_INITPLR6, 0x86080000);
1208 mtsdram(SDRAM_INITPLR7, 0x81000062);
1209 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1210 switch (selected_cas) {
1211 case DDR_CAS_3:
1212 cas = 3 << 4;
1213 break;
1214 case DDR_CAS_4:
1215 cas = 4 << 4;
1216 break;
1217 case DDR_CAS_5:
1218 cas = 5 << 4;
1219 break;
1220 default:
1221 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1222 spd_ddr_init_hang ();
1223 break;
1224 }
1225
1226 #if 0
1227 /*
1228 * ToDo - Still a problem with the write recovery:
1229 * On the Corsair CM2X512-5400C4 module, setting write recovery
1230 * in the INITPLR reg to the value calculated in program_mode()
1231 * results in not correctly working DDR2 memory (crash after
1232 * relocation).
1233 *
1234 * So for now, set the write recovery to 3. This seems to work
1235 * on the Corair module too.
1236 *
1237 * 2007-03-01, sr
1238 */
1239 switch (write_recovery) {
1240 case 3:
1241 wr = WRITE_RECOV_3;
1242 break;
1243 case 4:
1244 wr = WRITE_RECOV_4;
1245 break;
1246 case 5:
1247 wr = WRITE_RECOV_5;
1248 break;
1249 case 6:
1250 wr = WRITE_RECOV_6;
1251 break;
1252 default:
1253 printf("ERROR: write recovery not support (%d)", write_recovery);
1254 spd_ddr_init_hang ();
1255 break;
1256 }
1257 #else
1258 wr = WRITE_RECOV_3; /* test-only, see description above */
1259 #endif
1260
1261 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1262 if (dimm_populated[dimm_num] != SDRAM_NONE)
1263 total_dimm++;
1264 if (total_dimm == 1) {
1265 odt = ODT_150_OHM;
1266 ods = ODS_FULL;
1267 } else if (total_dimm == 2) {
1268 odt = ODT_75_OHM;
1269 ods = ODS_REDUCED;
1270 } else {
1271 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1272 spd_ddr_init_hang ();
1273 }
1274
1275 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1276 emr = CMD_EMR | SELECT_EMR | odt | ods;
1277 emr2 = CMD_EMR | SELECT_EMR2;
1278 emr3 = CMD_EMR | SELECT_EMR3;
1279 mtsdram(SDRAM_INITPLR0, 0xB5000000 | CMD_NOP); /* NOP */
1280 udelay(1000);
1281 mtsdram(SDRAM_INITPLR1, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1282 mtsdram(SDRAM_INITPLR2, 0x80800000 | emr2); /* EMR2 */
1283 mtsdram(SDRAM_INITPLR3, 0x80800000 | emr3); /* EMR3 */
1284 mtsdram(SDRAM_INITPLR4, 0x80800000 | emr); /* EMR DLL ENABLE */
1285 mtsdram(SDRAM_INITPLR5, 0x80800000 | mr | DLL_RESET); /* MR w/ DLL reset */
1286 udelay(1000);
1287 mtsdram(SDRAM_INITPLR6, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1288 mtsdram(SDRAM_INITPLR7, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1289 mtsdram(SDRAM_INITPLR8, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1290 mtsdram(SDRAM_INITPLR9, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1291 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1292 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr); /* MR w/o DLL reset */
1293 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr); /* EMR OCD Default */
1294 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
1295 } else {
1296 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1297 spd_ddr_init_hang ();
1298 }
1299 }
1300
1301 /*------------------------------------------------------------------
1302 * This routine programs the SDRAM_MMODE register.
1303 * the selected_cas is an output parameter, that will be passed
1304 * by caller to call the above program_initplr( )
1305 *-----------------------------------------------------------------*/
1306 static void program_mode(unsigned long *dimm_populated,
1307 unsigned char *iic0_dimm_addr,
1308 unsigned long num_dimm_banks,
1309 ddr_cas_id_t *selected_cas,
1310 int *write_recovery)
1311 {
1312 unsigned long dimm_num;
1313 unsigned long sdram_ddr1;
1314 unsigned long t_wr_ns;
1315 unsigned long t_wr_clk;
1316 unsigned long cas_bit;
1317 unsigned long cas_index;
1318 unsigned long sdram_freq;
1319 unsigned long ddr_check;
1320 unsigned long mmode;
1321 unsigned long tcyc_reg;
1322 unsigned long cycle_2_0_clk;
1323 unsigned long cycle_2_5_clk;
1324 unsigned long cycle_3_0_clk;
1325 unsigned long cycle_4_0_clk;
1326 unsigned long cycle_5_0_clk;
1327 unsigned long max_2_0_tcyc_ns_x_100;
1328 unsigned long max_2_5_tcyc_ns_x_100;
1329 unsigned long max_3_0_tcyc_ns_x_100;
1330 unsigned long max_4_0_tcyc_ns_x_100;
1331 unsigned long max_5_0_tcyc_ns_x_100;
1332 unsigned long cycle_time_ns_x_100[3];
1333 PPC440_SYS_INFO board_cfg;
1334 unsigned char cas_2_0_available;
1335 unsigned char cas_2_5_available;
1336 unsigned char cas_3_0_available;
1337 unsigned char cas_4_0_available;
1338 unsigned char cas_5_0_available;
1339 unsigned long sdr_ddrpll;
1340
1341 /*------------------------------------------------------------------
1342 * Get the board configuration info.
1343 *-----------------------------------------------------------------*/
1344 get_sys_info(&board_cfg);
1345
1346 mfsdr(SDR0_DDR0, sdr_ddrpll);
1347 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1348 debug("sdram_freq=%d\n", sdram_freq);
1349
1350 /*------------------------------------------------------------------
1351 * Handle the timing. We need to find the worst case timing of all
1352 * the dimm modules installed.
1353 *-----------------------------------------------------------------*/
1354 t_wr_ns = 0;
1355 cas_2_0_available = TRUE;
1356 cas_2_5_available = TRUE;
1357 cas_3_0_available = TRUE;
1358 cas_4_0_available = TRUE;
1359 cas_5_0_available = TRUE;
1360 max_2_0_tcyc_ns_x_100 = 10;
1361 max_2_5_tcyc_ns_x_100 = 10;
1362 max_3_0_tcyc_ns_x_100 = 10;
1363 max_4_0_tcyc_ns_x_100 = 10;
1364 max_5_0_tcyc_ns_x_100 = 10;
1365 sdram_ddr1 = TRUE;
1366
1367 /* loop through all the DIMM slots on the board */
1368 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1369 /* If a dimm is installed in a particular slot ... */
1370 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1371 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1372 sdram_ddr1 = TRUE;
1373 else
1374 sdram_ddr1 = FALSE;
1375
1376 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1377 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1378 debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1379
1380 /* For a particular DIMM, grab the three CAS values it supports */
1381 for (cas_index = 0; cas_index < 3; cas_index++) {
1382 switch (cas_index) {
1383 case 0:
1384 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1385 break;
1386 case 1:
1387 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1388 break;
1389 default:
1390 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1391 break;
1392 }
1393
1394 if ((tcyc_reg & 0x0F) >= 10) {
1395 if ((tcyc_reg & 0x0F) == 0x0D) {
1396 /* Convert from hex to decimal */
1397 cycle_time_ns_x_100[cas_index] =
1398 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1399 } else {
1400 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1401 "in slot %d\n", (unsigned int)dimm_num);
1402 spd_ddr_init_hang ();
1403 }
1404 } else {
1405 /* Convert from hex to decimal */
1406 cycle_time_ns_x_100[cas_index] =
1407 (((tcyc_reg & 0xF0) >> 4) * 100) +
1408 ((tcyc_reg & 0x0F)*10);
1409 }
1410 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1411 cycle_time_ns_x_100[cas_index]);
1412 }
1413
1414 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1415 /* supported for a particular DIMM. */
1416 cas_index = 0;
1417
1418 if (sdram_ddr1) {
1419 /*
1420 * DDR devices use the following bitmask for CAS latency:
1421 * Bit 7 6 5 4 3 2 1 0
1422 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1423 */
1424 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1425 (cycle_time_ns_x_100[cas_index] != 0)) {
1426 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1427 cycle_time_ns_x_100[cas_index]);
1428 cas_index++;
1429 } else {
1430 if (cas_index != 0)
1431 cas_index++;
1432 cas_4_0_available = FALSE;
1433 }
1434
1435 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1436 (cycle_time_ns_x_100[cas_index] != 0)) {
1437 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1438 cycle_time_ns_x_100[cas_index]);
1439 cas_index++;
1440 } else {
1441 if (cas_index != 0)
1442 cas_index++;
1443 cas_3_0_available = FALSE;
1444 }
1445
1446 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1447 (cycle_time_ns_x_100[cas_index] != 0)) {
1448 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1449 cycle_time_ns_x_100[cas_index]);
1450 cas_index++;
1451 } else {
1452 if (cas_index != 0)
1453 cas_index++;
1454 cas_2_5_available = FALSE;
1455 }
1456
1457 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1458 (cycle_time_ns_x_100[cas_index] != 0)) {
1459 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1460 cycle_time_ns_x_100[cas_index]);
1461 cas_index++;
1462 } else {
1463 if (cas_index != 0)
1464 cas_index++;
1465 cas_2_0_available = FALSE;
1466 }
1467 } else {
1468 /*
1469 * DDR2 devices use the following bitmask for CAS latency:
1470 * Bit 7 6 5 4 3 2 1 0
1471 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1472 */
1473 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1474 (cycle_time_ns_x_100[cas_index] != 0)) {
1475 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1476 cycle_time_ns_x_100[cas_index]);
1477 cas_index++;
1478 } else {
1479 if (cas_index != 0)
1480 cas_index++;
1481 cas_5_0_available = FALSE;
1482 }
1483
1484 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1485 (cycle_time_ns_x_100[cas_index] != 0)) {
1486 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1487 cycle_time_ns_x_100[cas_index]);
1488 cas_index++;
1489 } else {
1490 if (cas_index != 0)
1491 cas_index++;
1492 cas_4_0_available = FALSE;
1493 }
1494
1495 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1496 (cycle_time_ns_x_100[cas_index] != 0)) {
1497 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1498 cycle_time_ns_x_100[cas_index]);
1499 cas_index++;
1500 } else {
1501 if (cas_index != 0)
1502 cas_index++;
1503 cas_3_0_available = FALSE;
1504 }
1505 }
1506 }
1507 }
1508
1509 /*------------------------------------------------------------------
1510 * Set the SDRAM mode, SDRAM_MMODE
1511 *-----------------------------------------------------------------*/
1512 mfsdram(SDRAM_MMODE, mmode);
1513 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1514
1515 /* add 10 here because of rounding problems */
1516 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1517 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1518 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1519 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1520 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1521 debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1522 debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1523 debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1524
1525 if (sdram_ddr1 == TRUE) { /* DDR1 */
1526 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1527 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1528 *selected_cas = DDR_CAS_2;
1529 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1530 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1531 *selected_cas = DDR_CAS_2_5;
1532 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1533 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1534 *selected_cas = DDR_CAS_3;
1535 } else {
1536 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1537 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1538 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1539 spd_ddr_init_hang ();
1540 }
1541 } else { /* DDR2 */
1542 debug("cas_3_0_available=%d\n", cas_3_0_available);
1543 debug("cas_4_0_available=%d\n", cas_4_0_available);
1544 debug("cas_5_0_available=%d\n", cas_5_0_available);
1545 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1546 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1547 *selected_cas = DDR_CAS_3;
1548 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1549 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1550 *selected_cas = DDR_CAS_4;
1551 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1552 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1553 *selected_cas = DDR_CAS_5;
1554 } else {
1555 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1556 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1557 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1558 printf("cas3=%d cas4=%d cas5=%d\n",
1559 cas_3_0_available, cas_4_0_available, cas_5_0_available);
1560 printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
1561 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1562 spd_ddr_init_hang ();
1563 }
1564 }
1565
1566 if (sdram_ddr1 == TRUE)
1567 mmode |= SDRAM_MMODE_WR_DDR1;
1568 else {
1569
1570 /* loop through all the DIMM slots on the board */
1571 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1572 /* If a dimm is installed in a particular slot ... */
1573 if (dimm_populated[dimm_num] != SDRAM_NONE)
1574 t_wr_ns = max(t_wr_ns,
1575 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1576 }
1577
1578 /*
1579 * convert from nanoseconds to ddr clocks
1580 * round up if necessary
1581 */
1582 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1583 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1584 if (sdram_freq != ddr_check)
1585 t_wr_clk++;
1586
1587 switch (t_wr_clk) {
1588 case 0:
1589 case 1:
1590 case 2:
1591 case 3:
1592 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1593 break;
1594 case 4:
1595 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1596 break;
1597 case 5:
1598 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1599 break;
1600 default:
1601 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1602 break;
1603 }
1604 *write_recovery = t_wr_clk;
1605 }
1606
1607 debug("CAS latency = %d\n", *selected_cas);
1608 debug("Write recovery = %d\n", *write_recovery);
1609
1610 mtsdram(SDRAM_MMODE, mmode);
1611 }
1612
1613 /*-----------------------------------------------------------------------------+
1614 * program_rtr.
1615 *-----------------------------------------------------------------------------*/
1616 static void program_rtr(unsigned long *dimm_populated,
1617 unsigned char *iic0_dimm_addr,
1618 unsigned long num_dimm_banks)
1619 {
1620 PPC440_SYS_INFO board_cfg;
1621 unsigned long max_refresh_rate;
1622 unsigned long dimm_num;
1623 unsigned long refresh_rate_type;
1624 unsigned long refresh_rate;
1625 unsigned long rint;
1626 unsigned long sdram_freq;
1627 unsigned long sdr_ddrpll;
1628 unsigned long val;
1629
1630 /*------------------------------------------------------------------
1631 * Get the board configuration info.
1632 *-----------------------------------------------------------------*/
1633 get_sys_info(&board_cfg);
1634
1635 /*------------------------------------------------------------------
1636 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1637 *-----------------------------------------------------------------*/
1638 mfsdr(SDR0_DDR0, sdr_ddrpll);
1639 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1640
1641 max_refresh_rate = 0;
1642 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1643 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1644
1645 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1646 refresh_rate_type &= 0x7F;
1647 switch (refresh_rate_type) {
1648 case 0:
1649 refresh_rate = 15625;
1650 break;
1651 case 1:
1652 refresh_rate = 3906;
1653 break;
1654 case 2:
1655 refresh_rate = 7812;
1656 break;
1657 case 3:
1658 refresh_rate = 31250;
1659 break;
1660 case 4:
1661 refresh_rate = 62500;
1662 break;
1663 case 5:
1664 refresh_rate = 125000;
1665 break;
1666 default:
1667 refresh_rate = 0;
1668 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1669 (unsigned int)dimm_num);
1670 printf("Replace the DIMM module with a supported DIMM.\n\n");
1671 spd_ddr_init_hang ();
1672 break;
1673 }
1674
1675 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1676 }
1677 }
1678
1679 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1680 mfsdram(SDRAM_RTR, val);
1681 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1682 (SDRAM_RTR_RINT_ENCODE(rint)));
1683 }
1684
1685 /*------------------------------------------------------------------
1686 * This routine programs the SDRAM_TRx registers.
1687 *-----------------------------------------------------------------*/
1688 static void program_tr(unsigned long *dimm_populated,
1689 unsigned char *iic0_dimm_addr,
1690 unsigned long num_dimm_banks)
1691 {
1692 unsigned long dimm_num;
1693 unsigned long sdram_ddr1;
1694 unsigned long t_rp_ns;
1695 unsigned long t_rcd_ns;
1696 unsigned long t_rrd_ns;
1697 unsigned long t_ras_ns;
1698 unsigned long t_rc_ns;
1699 unsigned long t_rfc_ns;
1700 unsigned long t_wpc_ns;
1701 unsigned long t_wtr_ns;
1702 unsigned long t_rpc_ns;
1703 unsigned long t_rp_clk;
1704 unsigned long t_rcd_clk;
1705 unsigned long t_rrd_clk;
1706 unsigned long t_ras_clk;
1707 unsigned long t_rc_clk;
1708 unsigned long t_rfc_clk;
1709 unsigned long t_wpc_clk;
1710 unsigned long t_wtr_clk;
1711 unsigned long t_rpc_clk;
1712 unsigned long sdtr1, sdtr2, sdtr3;
1713 unsigned long ddr_check;
1714 unsigned long sdram_freq;
1715 unsigned long sdr_ddrpll;
1716
1717 PPC440_SYS_INFO board_cfg;
1718
1719 /*------------------------------------------------------------------
1720 * Get the board configuration info.
1721 *-----------------------------------------------------------------*/
1722 get_sys_info(&board_cfg);
1723
1724 mfsdr(SDR0_DDR0, sdr_ddrpll);
1725 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1726
1727 /*------------------------------------------------------------------
1728 * Handle the timing. We need to find the worst case timing of all
1729 * the dimm modules installed.
1730 *-----------------------------------------------------------------*/
1731 t_rp_ns = 0;
1732 t_rrd_ns = 0;
1733 t_rcd_ns = 0;
1734 t_ras_ns = 0;
1735 t_rc_ns = 0;
1736 t_rfc_ns = 0;
1737 t_wpc_ns = 0;
1738 t_wtr_ns = 0;
1739 t_rpc_ns = 0;
1740 sdram_ddr1 = TRUE;
1741
1742 /* loop through all the DIMM slots on the board */
1743 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1744 /* If a dimm is installed in a particular slot ... */
1745 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1746 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1747 sdram_ddr1 = TRUE;
1748 else
1749 sdram_ddr1 = FALSE;
1750
1751 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1752 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1753 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1754 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1755 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1756 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1757 }
1758 }
1759
1760 /*------------------------------------------------------------------
1761 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1762 *-----------------------------------------------------------------*/
1763 mfsdram(SDRAM_SDTR1, sdtr1);
1764 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1765 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1766
1767 /* default values */
1768 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1769 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1770
1771 /* normal operations */
1772 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1773 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1774
1775 mtsdram(SDRAM_SDTR1, sdtr1);
1776
1777 /*------------------------------------------------------------------
1778 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1779 *-----------------------------------------------------------------*/
1780 mfsdram(SDRAM_SDTR2, sdtr2);
1781 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1782 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1783 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1784 SDRAM_SDTR2_RRD_MASK);
1785
1786 /*
1787 * convert t_rcd from nanoseconds to ddr clocks
1788 * round up if necessary
1789 */
1790 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1791 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1792 if (sdram_freq != ddr_check)
1793 t_rcd_clk++;
1794
1795 switch (t_rcd_clk) {
1796 case 0:
1797 case 1:
1798 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1799 break;
1800 case 2:
1801 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1802 break;
1803 case 3:
1804 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1805 break;
1806 case 4:
1807 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1808 break;
1809 default:
1810 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1811 break;
1812 }
1813
1814 if (sdram_ddr1 == TRUE) { /* DDR1 */
1815 if (sdram_freq < 200000000) {
1816 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1817 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1818 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1819 } else {
1820 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1821 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1822 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1823 }
1824 } else { /* DDR2 */
1825 /* loop through all the DIMM slots on the board */
1826 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1827 /* If a dimm is installed in a particular slot ... */
1828 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1829 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1830 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1831 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1832 }
1833 }
1834
1835 /*
1836 * convert from nanoseconds to ddr clocks
1837 * round up if necessary
1838 */
1839 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1840 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1841 if (sdram_freq != ddr_check)
1842 t_wpc_clk++;
1843
1844 switch (t_wpc_clk) {
1845 case 0:
1846 case 1:
1847 case 2:
1848 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1849 break;
1850 case 3:
1851 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1852 break;
1853 case 4:
1854 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1855 break;
1856 case 5:
1857 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1858 break;
1859 default:
1860 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1861 break;
1862 }
1863
1864 /*
1865 * convert from nanoseconds to ddr clocks
1866 * round up if necessary
1867 */
1868 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1869 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1870 if (sdram_freq != ddr_check)
1871 t_wtr_clk++;
1872
1873 switch (t_wtr_clk) {
1874 case 0:
1875 case 1:
1876 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1877 break;
1878 case 2:
1879 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1880 break;
1881 case 3:
1882 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1883 break;
1884 default:
1885 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1886 break;
1887 }
1888
1889 /*
1890 * convert from nanoseconds to ddr clocks
1891 * round up if necessary
1892 */
1893 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1894 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1895 if (sdram_freq != ddr_check)
1896 t_rpc_clk++;
1897
1898 switch (t_rpc_clk) {
1899 case 0:
1900 case 1:
1901 case 2:
1902 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1903 break;
1904 case 3:
1905 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1906 break;
1907 default:
1908 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1909 break;
1910 }
1911 }
1912
1913 /* default value */
1914 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1915
1916 /*
1917 * convert t_rrd from nanoseconds to ddr clocks
1918 * round up if necessary
1919 */
1920 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1921 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1922 if (sdram_freq != ddr_check)
1923 t_rrd_clk++;
1924
1925 if (t_rrd_clk == 3)
1926 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1927 else
1928 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1929
1930 /*
1931 * convert t_rp from nanoseconds to ddr clocks
1932 * round up if necessary
1933 */
1934 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1935 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1936 if (sdram_freq != ddr_check)
1937 t_rp_clk++;
1938
1939 switch (t_rp_clk) {
1940 case 0:
1941 case 1:
1942 case 2:
1943 case 3:
1944 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
1945 break;
1946 case 4:
1947 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
1948 break;
1949 case 5:
1950 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
1951 break;
1952 case 6:
1953 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
1954 break;
1955 default:
1956 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
1957 break;
1958 }
1959
1960 mtsdram(SDRAM_SDTR2, sdtr2);
1961
1962 /*------------------------------------------------------------------
1963 * Set the SDRAM Timing Reg 3, SDRAM_TR3
1964 *-----------------------------------------------------------------*/
1965 mfsdram(SDRAM_SDTR3, sdtr3);
1966 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
1967 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
1968
1969 /*
1970 * convert t_ras from nanoseconds to ddr clocks
1971 * round up if necessary
1972 */
1973 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
1974 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
1975 if (sdram_freq != ddr_check)
1976 t_ras_clk++;
1977
1978 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
1979
1980 /*
1981 * convert t_rc from nanoseconds to ddr clocks
1982 * round up if necessary
1983 */
1984 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
1985 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
1986 if (sdram_freq != ddr_check)
1987 t_rc_clk++;
1988
1989 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
1990
1991 /* default xcs value */
1992 sdtr3 |= SDRAM_SDTR3_XCS;
1993
1994 /*
1995 * convert t_rfc from nanoseconds to ddr clocks
1996 * round up if necessary
1997 */
1998 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
1999 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2000 if (sdram_freq != ddr_check)
2001 t_rfc_clk++;
2002
2003 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2004
2005 mtsdram(SDRAM_SDTR3, sdtr3);
2006 }
2007
2008 /*-----------------------------------------------------------------------------+
2009 * program_bxcf.
2010 *-----------------------------------------------------------------------------*/
2011 static void program_bxcf(unsigned long *dimm_populated,
2012 unsigned char *iic0_dimm_addr,
2013 unsigned long num_dimm_banks)
2014 {
2015 unsigned long dimm_num;
2016 unsigned long num_col_addr;
2017 unsigned long num_ranks;
2018 unsigned long num_banks;
2019 unsigned long mode;
2020 unsigned long ind_rank;
2021 unsigned long ind;
2022 unsigned long ind_bank;
2023 unsigned long bank_0_populated;
2024
2025 /*------------------------------------------------------------------
2026 * Set the BxCF regs. First, wipe out the bank config registers.
2027 *-----------------------------------------------------------------*/
2028 mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF);
2029 mtdcr(SDRAMC_CFGDATA, 0x00000000);
2030 mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF);
2031 mtdcr(SDRAMC_CFGDATA, 0x00000000);
2032 mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF);
2033 mtdcr(SDRAMC_CFGDATA, 0x00000000);
2034 mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF);
2035 mtdcr(SDRAMC_CFGDATA, 0x00000000);
2036
2037 mode = SDRAM_BXCF_M_BE_ENABLE;
2038
2039 bank_0_populated = 0;
2040
2041 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2042 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2043 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2044 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2045 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2046 num_ranks = (num_ranks & 0x0F) +1;
2047 else
2048 num_ranks = num_ranks & 0x0F;
2049
2050 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2051
2052 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2053 if (num_banks == 4)
2054 ind = 0;
2055 else
2056 ind = 5;
2057 switch (num_col_addr) {
2058 case 0x08:
2059 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2060 break;
2061 case 0x09:
2062 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2063 break;
2064 case 0x0A:
2065 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2066 break;
2067 case 0x0B:
2068 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2069 break;
2070 case 0x0C:
2071 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2072 break;
2073 default:
2074 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2075 (unsigned int)dimm_num);
2076 printf("ERROR: Unsupported value for number of "
2077 "column addresses: %d.\n", (unsigned int)num_col_addr);
2078 printf("Replace the DIMM module with a supported DIMM.\n\n");
2079 spd_ddr_init_hang ();
2080 }
2081 }
2082
2083 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2084 bank_0_populated = 1;
2085
2086 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2087 mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2));
2088 mtdcr(SDRAMC_CFGDATA, mode);
2089 }
2090 }
2091 }
2092 }
2093
2094 /*------------------------------------------------------------------
2095 * program memory queue.
2096 *-----------------------------------------------------------------*/
2097 static void program_memory_queue(unsigned long *dimm_populated,
2098 unsigned char *iic0_dimm_addr,
2099 unsigned long num_dimm_banks)
2100 {
2101 unsigned long dimm_num;
2102 unsigned long rank_base_addr;
2103 unsigned long rank_reg;
2104 unsigned long rank_size_bytes;
2105 unsigned long rank_size_id;
2106 unsigned long num_ranks;
2107 unsigned long baseadd_size;
2108 unsigned long i;
2109 unsigned long bank_0_populated = 0;
2110
2111 /*------------------------------------------------------------------
2112 * Reset the rank_base_address.
2113 *-----------------------------------------------------------------*/
2114 rank_reg = SDRAM_R0BAS;
2115
2116 rank_base_addr = 0x00000000;
2117
2118 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2119 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2120 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2121 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2122 num_ranks = (num_ranks & 0x0F) + 1;
2123 else
2124 num_ranks = num_ranks & 0x0F;
2125
2126 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2127
2128 /*------------------------------------------------------------------
2129 * Set the sizes
2130 *-----------------------------------------------------------------*/
2131 baseadd_size = 0;
2132 rank_size_bytes = 4 * 1024 * 1024 * rank_size_id;
2133 switch (rank_size_id) {
2134 case 0x02:
2135 baseadd_size |= SDRAM_RXBAS_SDSZ_8;
2136 break;
2137 case 0x04:
2138 baseadd_size |= SDRAM_RXBAS_SDSZ_16;
2139 break;
2140 case 0x08:
2141 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2142 break;
2143 case 0x10:
2144 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2145 break;
2146 case 0x20:
2147 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2148 break;
2149 case 0x40:
2150 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2151 break;
2152 case 0x80:
2153 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2154 break;
2155 default:
2156 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2157 (unsigned int)dimm_num);
2158 printf("ERROR: Unsupported value for the banksize: %d.\n",
2159 (unsigned int)rank_size_id);
2160 printf("Replace the DIMM module with a supported DIMM.\n\n");
2161 spd_ddr_init_hang ();
2162 }
2163
2164 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2165 bank_0_populated = 1;
2166
2167 for (i = 0; i < num_ranks; i++) {
2168 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2169 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2170 baseadd_size));
2171 rank_base_addr += rank_size_bytes;
2172 }
2173 }
2174 }
2175 }
2176
2177 /*-----------------------------------------------------------------------------+
2178 * is_ecc_enabled.
2179 *-----------------------------------------------------------------------------*/
2180 static unsigned long is_ecc_enabled(void)
2181 {
2182 unsigned long dimm_num;
2183 unsigned long ecc;
2184 unsigned long val;
2185
2186 ecc = 0;
2187 /* loop through all the DIMM slots on the board */
2188 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2189 mfsdram(SDRAM_MCOPT1, val);
2190 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2191 }
2192
2193 return ecc;
2194 }
2195
2196 static void blank_string(int size)
2197 {
2198 int i;
2199
2200 for (i=0; i<size; i++)
2201 putc('\b');
2202 for (i=0; i<size; i++)
2203 putc(' ');
2204 for (i=0; i<size; i++)
2205 putc('\b');
2206 }
2207
2208 #ifdef CONFIG_DDR_ECC
2209 /*-----------------------------------------------------------------------------+
2210 * program_ecc.
2211 *-----------------------------------------------------------------------------*/
2212 static void program_ecc(unsigned long *dimm_populated,
2213 unsigned char *iic0_dimm_addr,
2214 unsigned long num_dimm_banks,
2215 unsigned long tlb_word2_i_value)
2216 {
2217 unsigned long mcopt1;
2218 unsigned long mcopt2;
2219 unsigned long mcstat;
2220 unsigned long dimm_num;
2221 unsigned long ecc;
2222
2223 ecc = 0;
2224 /* loop through all the DIMM slots on the board */
2225 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2226 /* If a dimm is installed in a particular slot ... */
2227 if (dimm_populated[dimm_num] != SDRAM_NONE)
2228 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2229 }
2230 if (ecc == 0)
2231 return;
2232
2233 mfsdram(SDRAM_MCOPT1, mcopt1);
2234 mfsdram(SDRAM_MCOPT2, mcopt2);
2235
2236 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2237 /* DDR controller must be enabled and not in self-refresh. */
2238 mfsdram(SDRAM_MCSTAT, mcstat);
2239 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2240 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2241 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2242 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2243
2244 program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2245 }
2246 }
2247
2248 return;
2249 }
2250
2251 #ifdef CONFIG_ECC_ERROR_RESET
2252 /*
2253 * Check for ECC errors and reset board upon any error here
2254 *
2255 * On the Katmai 440SPe eval board, from time to time, the first
2256 * lword write access after DDR2 initializazion with ECC checking
2257 * enabled, leads to an ECC error. I couldn't find a configuration
2258 * without this happening. On my board with the current setup it
2259 * happens about 1 from 10 times.
2260 *
2261 * The ECC modules used for testing are:
2262 * - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's)
2263 *
2264 * This has to get fixed for the Katmai and tested for the other
2265 * board (440SP/440SPe) that will eventually use this code in the
2266 * future.
2267 *
2268 * 2007-03-01, sr
2269 */
2270 static void check_ecc(void)
2271 {
2272 u32 val;
2273
2274 mfsdram(SDRAM_ECCCR, val);
2275 if (val != 0) {
2276 printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n",
2277 val, mfdcr(0x4c), mfdcr(0x4e));
2278 printf("ECC error occured, resetting board...\n");
2279 do_reset(NULL, 0, 0, NULL);
2280 }
2281 }
2282 #endif
2283
2284 static void wait_ddr_idle(void)
2285 {
2286 u32 val;
2287
2288 do {
2289 mfsdram(SDRAM_MCSTAT, val);
2290 } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2291 }
2292
2293 /*-----------------------------------------------------------------------------+
2294 * program_ecc_addr.
2295 *-----------------------------------------------------------------------------*/
2296 static void program_ecc_addr(unsigned long start_address,
2297 unsigned long num_bytes,
2298 unsigned long tlb_word2_i_value)
2299 {
2300 unsigned long current_address;
2301 unsigned long end_address;
2302 unsigned long address_increment;
2303 unsigned long mcopt1;
2304 char str[] = "ECC generation -";
2305 char slash[] = "\\|/-\\|/-";
2306 int loop = 0;
2307 int loopi = 0;
2308
2309 current_address = start_address;
2310 mfsdram(SDRAM_MCOPT1, mcopt1);
2311 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2312 mtsdram(SDRAM_MCOPT1,
2313 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2314 sync();
2315 eieio();
2316 wait_ddr_idle();
2317
2318 puts(str);
2319 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2320 /* ECC bit set method for non-cached memory */
2321 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2322 address_increment = 4;
2323 else
2324 address_increment = 8;
2325 end_address = current_address + num_bytes;
2326
2327 while (current_address < end_address) {
2328 *((unsigned long *)current_address) = 0x00000000;
2329 current_address += address_increment;
2330
2331 if ((loop++ % (2 << 20)) == 0) {
2332 putc('\b');
2333 putc(slash[loopi++ % 8]);
2334 }
2335 }
2336
2337 } else {
2338 /* ECC bit set method for cached memory */
2339 dcbz_area(start_address, num_bytes);
2340 dflush();
2341 }
2342
2343 blank_string(strlen(str));
2344
2345 sync();
2346 eieio();
2347 wait_ddr_idle();
2348
2349 /* clear ECC error repoting registers */
2350 mtsdram(SDRAM_ECCCR, 0xffffffff);
2351 mtdcr(0x4c, 0xffffffff);
2352
2353 mtsdram(SDRAM_MCOPT1,
2354 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2355 sync();
2356 eieio();
2357 wait_ddr_idle();
2358
2359 #ifdef CONFIG_ECC_ERROR_RESET
2360 /*
2361 * One write to 0 is enough to trigger this ECC error
2362 * (see description above)
2363 */
2364 out_be32(0, 0x12345678);
2365 check_ecc();
2366 #endif
2367 }
2368 }
2369 #endif
2370
2371 /*-----------------------------------------------------------------------------+
2372 * program_DQS_calibration.
2373 *-----------------------------------------------------------------------------*/
2374 static void program_DQS_calibration(unsigned long *dimm_populated,
2375 unsigned char *iic0_dimm_addr,
2376 unsigned long num_dimm_banks)
2377 {
2378 unsigned long val;
2379
2380 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2381 mtsdram(SDRAM_RQDC, 0x80000037);
2382 mtsdram(SDRAM_RDCC, 0x40000000);
2383 mtsdram(SDRAM_RFDC, 0x000001DF);
2384
2385 test();
2386 #else
2387 /*------------------------------------------------------------------
2388 * Program RDCC register
2389 * Read sample cycle auto-update enable
2390 *-----------------------------------------------------------------*/
2391
2392 /*
2393 * Modified for the Katmai platform: with some DIMMs, the DDR2
2394 * controller automatically selects the T2 read cycle, but this
2395 * proves unreliable. Go ahead and force the DDR2 controller
2396 * to use the T4 sample and disable the automatic update of the
2397 * RDSS field.
2398 */
2399 mfsdram(SDRAM_RDCC, val);
2400 mtsdram(SDRAM_RDCC,
2401 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2402 | (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
2403
2404 /*------------------------------------------------------------------
2405 * Program RQDC register
2406 * Internal DQS delay mechanism enable
2407 *-----------------------------------------------------------------*/
2408 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2409
2410 /*------------------------------------------------------------------
2411 * Program RFDC register
2412 * Set Feedback Fractional Oversample
2413 * Auto-detect read sample cycle enable
2414 *-----------------------------------------------------------------*/
2415 mfsdram(SDRAM_RFDC, val);
2416 mtsdram(SDRAM_RFDC,
2417 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2418 SDRAM_RFDC_RFFD_MASK))
2419 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2420 SDRAM_RFDC_RFFD_ENCODE(0)));
2421
2422 DQS_calibration_process();
2423 #endif
2424 }
2425
2426 static int short_mem_test(void)
2427 {
2428 u32 *membase;
2429 u32 bxcr_num;
2430 u32 bxcf;
2431 int i;
2432 int j;
2433 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2434 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2435 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2436 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2437 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2438 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2439 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2440 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2441 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2442 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2443 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2444 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2445 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2446 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2447 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2448 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2449 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2450 int l;
2451
2452 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2453 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2454
2455 /* Banks enabled */
2456 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2457 /* Bank is enabled */
2458
2459 /*------------------------------------------------------------------
2460 * Run the short memory test.
2461 *-----------------------------------------------------------------*/
2462 membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
2463
2464 for (i = 0; i < NUMMEMTESTS; i++) {
2465 for (j = 0; j < NUMMEMWORDS; j++) {
2466 membase[j] = test[i][j];
2467 ppcDcbf((u32)&(membase[j]));
2468 }
2469 sync();
2470 for (l=0; l<NUMLOOPS; l++) {
2471 for (j = 0; j < NUMMEMWORDS; j++) {
2472 if (membase[j] != test[i][j]) {
2473 ppcDcbf((u32)&(membase[j]));
2474 return 0;
2475 }
2476 ppcDcbf((u32)&(membase[j]));
2477 }
2478 sync();
2479 }
2480 }
2481 } /* if bank enabled */
2482 } /* for bxcf_num */
2483
2484 return 1;
2485 }
2486
2487 #ifndef HARD_CODED_DQS
2488 /*-----------------------------------------------------------------------------+
2489 * DQS_calibration_process.
2490 *-----------------------------------------------------------------------------*/
2491 static void DQS_calibration_process(void)
2492 {
2493 unsigned long rfdc_reg;
2494 unsigned long rffd;
2495 unsigned long rqdc_reg;
2496 unsigned long rqfd;
2497 unsigned long val;
2498 long rqfd_average;
2499 long rffd_average;
2500 long max_start;
2501 long min_end;
2502 unsigned long begin_rqfd[MAXRANKS];
2503 unsigned long begin_rffd[MAXRANKS];
2504 unsigned long end_rqfd[MAXRANKS];
2505 unsigned long end_rffd[MAXRANKS];
2506 char window_found;
2507 unsigned long dlycal;
2508 unsigned long dly_val;
2509 unsigned long max_pass_length;
2510 unsigned long current_pass_length;
2511 unsigned long current_fail_length;
2512 unsigned long current_start;
2513 long max_end;
2514 unsigned char fail_found;
2515 unsigned char pass_found;
2516 u32 rqfd_start;
2517 char str[] = "Auto calibration -";
2518 char slash[] = "\\|/-\\|/-";
2519 int loopi = 0;
2520
2521 /*------------------------------------------------------------------
2522 * Test to determine the best read clock delay tuning bits.
2523 *
2524 * Before the DDR controller can be used, the read clock delay needs to be
2525 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2526 * This value cannot be hardcoded into the program because it changes
2527 * depending on the board's setup and environment.
2528 * To do this, all delay values are tested to see if they
2529 * work or not. By doing this, you get groups of fails with groups of
2530 * passing values. The idea is to find the start and end of a passing
2531 * window and take the center of it to use as the read clock delay.
2532 *
2533 * A failure has to be seen first so that when we hit a pass, we know
2534 * that it is truely the start of the window. If we get passing values
2535 * to start off with, we don't know if we are at the start of the window.
2536 *
2537 * The code assumes that a failure will always be found.
2538 * If a failure is not found, there is no easy way to get the middle
2539 * of the passing window. I guess we can pretty much pick any value
2540 * but some values will be better than others. Since the lowest speed
2541 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2542 * from experimentation it is safe to say you will always have a failure.
2543 *-----------------------------------------------------------------*/
2544
2545 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2546 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2547
2548 puts(str);
2549
2550 calibration_loop:
2551 mfsdram(SDRAM_RQDC, rqdc_reg);
2552 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2553 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2554
2555 max_start = 0;
2556 min_end = 0;
2557 begin_rqfd[0] = 0;
2558 begin_rffd[0] = 0;
2559 begin_rqfd[1] = 0;
2560 begin_rffd[1] = 0;
2561 end_rqfd[0] = 0;
2562 end_rffd[0] = 0;
2563 end_rqfd[1] = 0;
2564 end_rffd[1] = 0;
2565 window_found = FALSE;
2566
2567 max_pass_length = 0;
2568 max_start = 0;
2569 max_end = 0;
2570 current_pass_length = 0;
2571 current_fail_length = 0;
2572 current_start = 0;
2573 window_found = FALSE;
2574 fail_found = FALSE;
2575 pass_found = FALSE;
2576
2577 /*
2578 * get the delay line calibration register value
2579 */
2580 mfsdram(SDRAM_DLCR, dlycal);
2581 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2582
2583 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2584 mfsdram(SDRAM_RFDC, rfdc_reg);
2585 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2586
2587 /*------------------------------------------------------------------
2588 * Set the timing reg for the test.
2589 *-----------------------------------------------------------------*/
2590 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2591
2592 /*------------------------------------------------------------------
2593 * See if the rffd value passed.
2594 *-----------------------------------------------------------------*/
2595 if (short_mem_test()) {
2596 if (fail_found == TRUE) {
2597 pass_found = TRUE;
2598 if (current_pass_length == 0)
2599 current_start = rffd;
2600
2601 current_fail_length = 0;
2602 current_pass_length++;
2603
2604 if (current_pass_length > max_pass_length) {
2605 max_pass_length = current_pass_length;
2606 max_start = current_start;
2607 max_end = rffd;
2608 }
2609 }
2610 } else {
2611 current_pass_length = 0;
2612 current_fail_length++;
2613
2614 if (current_fail_length >= (dly_val >> 2)) {
2615 if (fail_found == FALSE) {
2616 fail_found = TRUE;
2617 } else if (pass_found == TRUE) {
2618 window_found = TRUE;
2619 break;
2620 }
2621 }
2622 }
2623 } /* for rffd */
2624
2625 /*------------------------------------------------------------------
2626 * Set the average RFFD value
2627 *-----------------------------------------------------------------*/
2628 rffd_average = ((max_start + max_end) >> 1);
2629
2630 if (rffd_average < 0)
2631 rffd_average = 0;
2632
2633 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2634 rffd_average = SDRAM_RFDC_RFFD_MAX;
2635 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2636 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2637
2638 max_pass_length = 0;
2639 max_start = 0;
2640 max_end = 0;
2641 current_pass_length = 0;
2642 current_fail_length = 0;
2643 current_start = 0;
2644 window_found = FALSE;
2645 fail_found = FALSE;
2646 pass_found = FALSE;
2647
2648 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2649 mfsdram(SDRAM_RQDC, rqdc_reg);
2650 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2651
2652 /*------------------------------------------------------------------
2653 * Set the timing reg for the test.
2654 *-----------------------------------------------------------------*/
2655 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2656
2657 /*------------------------------------------------------------------
2658 * See if the rffd value passed.
2659 *-----------------------------------------------------------------*/
2660 if (short_mem_test()) {
2661 if (fail_found == TRUE) {
2662 pass_found = TRUE;
2663 if (current_pass_length == 0)
2664 current_start = rqfd;
2665
2666 current_fail_length = 0;
2667 current_pass_length++;
2668
2669 if (current_pass_length > max_pass_length) {
2670 max_pass_length = current_pass_length;
2671 max_start = current_start;
2672 max_end = rqfd;
2673 }
2674 }
2675 } else {
2676 current_pass_length = 0;
2677 current_fail_length++;
2678
2679 if (fail_found == FALSE) {
2680 fail_found = TRUE;
2681 } else if (pass_found == TRUE) {
2682 window_found = TRUE;
2683 break;
2684 }
2685 }
2686 }
2687
2688 rqfd_average = ((max_start + max_end) >> 1);
2689
2690 /*------------------------------------------------------------------
2691 * Make sure we found the valid read passing window. Halt if not
2692 *-----------------------------------------------------------------*/
2693 if (window_found == FALSE) {
2694 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2695 putc('\b');
2696 putc(slash[loopi++ % 8]);
2697
2698 /* try again from with a different RQFD start value */
2699 rqfd_start++;
2700 goto calibration_loop;
2701 }
2702
2703 printf("\nERROR: Cannot determine a common read delay for the "
2704 "DIMM(s) installed.\n");
2705 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2706 spd_ddr_init_hang ();
2707 }
2708
2709 blank_string(strlen(str));
2710
2711 if (rqfd_average < 0)
2712 rqfd_average = 0;
2713
2714 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2715 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2716
2717 mtsdram(SDRAM_RQDC,
2718 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2719 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2720
2721 mfsdram(SDRAM_DLCR, val);
2722 debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2723 mfsdram(SDRAM_RQDC, val);
2724 debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2725 mfsdram(SDRAM_RFDC, val);
2726 debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2727 }
2728 #else /* calibration test with hardvalues */
2729 /*-----------------------------------------------------------------------------+
2730 * DQS_calibration_process.
2731 *-----------------------------------------------------------------------------*/
2732 static void test(void)
2733 {
2734 unsigned long dimm_num;
2735 unsigned long ecc_temp;
2736 unsigned long i, j;
2737 unsigned long *membase;
2738 unsigned long bxcf[MAXRANKS];
2739 unsigned long val;
2740 char window_found;
2741 char begin_found[MAXDIMMS];
2742 char end_found[MAXDIMMS];
2743 char search_end[MAXDIMMS];
2744 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2745 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2746 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2747 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2748 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2749 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2750 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2751 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2752 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2753 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2754 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2755 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2756 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2757 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2758 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2759 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2760 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2761
2762 /*------------------------------------------------------------------
2763 * Test to determine the best read clock delay tuning bits.
2764 *
2765 * Before the DDR controller can be used, the read clock delay needs to be
2766 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2767 * This value cannot be hardcoded into the program because it changes
2768 * depending on the board's setup and environment.
2769 * To do this, all delay values are tested to see if they
2770 * work or not. By doing this, you get groups of fails with groups of
2771 * passing values. The idea is to find the start and end of a passing
2772 * window and take the center of it to use as the read clock delay.
2773 *
2774 * A failure has to be seen first so that when we hit a pass, we know
2775 * that it is truely the start of the window. If we get passing values
2776 * to start off with, we don't know if we are at the start of the window.
2777 *
2778 * The code assumes that a failure will always be found.
2779 * If a failure is not found, there is no easy way to get the middle
2780 * of the passing window. I guess we can pretty much pick any value
2781 * but some values will be better than others. Since the lowest speed
2782 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2783 * from experimentation it is safe to say you will always have a failure.
2784 *-----------------------------------------------------------------*/
2785 mfsdram(SDRAM_MCOPT1, ecc_temp);
2786 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2787 mfsdram(SDRAM_MCOPT1, val);
2788 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2789 SDRAM_MCOPT1_MCHK_NON);
2790
2791 window_found = FALSE;
2792 begin_found[0] = FALSE;
2793 end_found[0] = FALSE;
2794 search_end[0] = FALSE;
2795 begin_found[1] = FALSE;
2796 end_found[1] = FALSE;
2797 search_end[1] = FALSE;
2798
2799 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2800 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2801
2802 /* Banks enabled */
2803 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2804
2805 /* Bank is enabled */
2806 membase =
2807 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2808
2809 /*------------------------------------------------------------------
2810 * Run the short memory test.
2811 *-----------------------------------------------------------------*/
2812 for (i = 0; i < NUMMEMTESTS; i++) {
2813 for (j = 0; j < NUMMEMWORDS; j++) {
2814 membase[j] = test[i][j];
2815 ppcDcbf((u32)&(membase[j]));
2816 }
2817 sync();
2818 for (j = 0; j < NUMMEMWORDS; j++) {
2819 if (membase[j] != test[i][j]) {
2820 ppcDcbf((u32)&(membase[j]));
2821 break;
2822 }
2823 ppcDcbf((u32)&(membase[j]));
2824 }
2825 sync();
2826 if (j < NUMMEMWORDS)
2827 break;
2828 }
2829
2830 /*------------------------------------------------------------------
2831 * See if the rffd value passed.
2832 *-----------------------------------------------------------------*/
2833 if (i < NUMMEMTESTS) {
2834 if ((end_found[dimm_num] == FALSE) &&
2835 (search_end[dimm_num] == TRUE)) {
2836 end_found[dimm_num] = TRUE;
2837 }
2838 if ((end_found[0] == TRUE) &&
2839 (end_found[1] == TRUE))
2840 break;
2841 } else {
2842 if (begin_found[dimm_num] == FALSE) {
2843 begin_found[dimm_num] = TRUE;
2844 search_end[dimm_num] = TRUE;
2845 }
2846 }
2847 } else {
2848 begin_found[dimm_num] = TRUE;
2849 end_found[dimm_num] = TRUE;
2850 }
2851 }
2852
2853 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2854 window_found = TRUE;
2855
2856 /*------------------------------------------------------------------
2857 * Make sure we found the valid read passing window. Halt if not
2858 *-----------------------------------------------------------------*/
2859 if (window_found == FALSE) {
2860 printf("ERROR: Cannot determine a common read delay for the "
2861 "DIMM(s) installed.\n");
2862 spd_ddr_init_hang ();
2863 }
2864
2865 /*------------------------------------------------------------------
2866 * Restore the ECC variable to what it originally was
2867 *-----------------------------------------------------------------*/
2868 mtsdram(SDRAM_MCOPT1,
2869 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2870 | ecc_temp);
2871 }
2872 #endif
2873
2874 #if defined(DEBUG)
2875 static void ppc440sp_sdram_register_dump(void)
2876 {
2877 unsigned int sdram_reg;
2878 unsigned int sdram_data;
2879 unsigned int dcr_data;
2880
2881 printf("\n Register Dump:\n");
2882 sdram_reg = SDRAM_MCSTAT;
2883 mfsdram(sdram_reg, sdram_data);
2884 printf(" SDRAM_MCSTAT = 0x%08X", sdram_data);
2885 sdram_reg = SDRAM_MCOPT1;
2886 mfsdram(sdram_reg, sdram_data);
2887 printf(" SDRAM_MCOPT1 = 0x%08X\n", sdram_data);
2888 sdram_reg = SDRAM_MCOPT2;
2889 mfsdram(sdram_reg, sdram_data);
2890 printf(" SDRAM_MCOPT2 = 0x%08X", sdram_data);
2891 sdram_reg = SDRAM_MODT0;
2892 mfsdram(sdram_reg, sdram_data);
2893 printf(" SDRAM_MODT0 = 0x%08X\n", sdram_data);
2894 sdram_reg = SDRAM_MODT1;
2895 mfsdram(sdram_reg, sdram_data);
2896 printf(" SDRAM_MODT1 = 0x%08X", sdram_data);
2897 sdram_reg = SDRAM_MODT2;
2898 mfsdram(sdram_reg, sdram_data);
2899 printf(" SDRAM_MODT2 = 0x%08X\n", sdram_data);
2900 sdram_reg = SDRAM_MODT3;
2901 mfsdram(sdram_reg, sdram_data);
2902 printf(" SDRAM_MODT3 = 0x%08X", sdram_data);
2903 sdram_reg = SDRAM_CODT;
2904 mfsdram(sdram_reg, sdram_data);
2905 printf(" SDRAM_CODT = 0x%08X\n", sdram_data);
2906 sdram_reg = SDRAM_VVPR;
2907 mfsdram(sdram_reg, sdram_data);
2908 printf(" SDRAM_VVPR = 0x%08X", sdram_data);
2909 sdram_reg = SDRAM_OPARS;
2910 mfsdram(sdram_reg, sdram_data);
2911 printf(" SDRAM_OPARS = 0x%08X\n", sdram_data);
2912 /*
2913 * OPAR2 is only used as a trigger register.
2914 * No data is contained in this register, and reading or writing
2915 * to is can cause bad things to happen (hangs). Just skip it
2916 * and report NA
2917 * sdram_reg = SDRAM_OPAR2;
2918 * mfsdram(sdram_reg, sdram_data);
2919 * printf(" SDRAM_OPAR2 = 0x%08X\n", sdram_data);
2920 */
2921 printf(" SDRAM_OPART = N/A ");
2922 sdram_reg = SDRAM_RTR;
2923 mfsdram(sdram_reg, sdram_data);
2924 printf(" SDRAM_RTR = 0x%08X\n", sdram_data);
2925 sdram_reg = SDRAM_MB0CF;
2926 mfsdram(sdram_reg, sdram_data);
2927 printf(" SDRAM_MB0CF = 0x%08X", sdram_data);
2928 sdram_reg = SDRAM_MB1CF;
2929 mfsdram(sdram_reg, sdram_data);
2930 printf(" SDRAM_MB1CF = 0x%08X\n", sdram_data);
2931 sdram_reg = SDRAM_MB2CF;
2932 mfsdram(sdram_reg, sdram_data);
2933 printf(" SDRAM_MB2CF = 0x%08X", sdram_data);
2934 sdram_reg = SDRAM_MB3CF;
2935 mfsdram(sdram_reg, sdram_data);
2936 printf(" SDRAM_MB3CF = 0x%08X\n", sdram_data);
2937 sdram_reg = SDRAM_INITPLR0;
2938 mfsdram(sdram_reg, sdram_data);
2939 printf(" SDRAM_INITPLR0 = 0x%08X", sdram_data);
2940 sdram_reg = SDRAM_INITPLR1;
2941 mfsdram(sdram_reg, sdram_data);
2942 printf(" SDRAM_INITPLR1 = 0x%08X\n", sdram_data);
2943 sdram_reg = SDRAM_INITPLR2;
2944 mfsdram(sdram_reg, sdram_data);
2945 printf(" SDRAM_INITPLR2 = 0x%08X", sdram_data);
2946 sdram_reg = SDRAM_INITPLR3;
2947 mfsdram(sdram_reg, sdram_data);
2948 printf(" SDRAM_INITPLR3 = 0x%08X\n", sdram_data);
2949 sdram_reg = SDRAM_INITPLR4;
2950 mfsdram(sdram_reg, sdram_data);
2951 printf(" SDRAM_INITPLR4 = 0x%08X", sdram_data);
2952 sdram_reg = SDRAM_INITPLR5;
2953 mfsdram(sdram_reg, sdram_data);
2954 printf(" SDRAM_INITPLR5 = 0x%08X\n", sdram_data);
2955 sdram_reg = SDRAM_INITPLR6;
2956 mfsdram(sdram_reg, sdram_data);
2957 printf(" SDRAM_INITPLR6 = 0x%08X", sdram_data);
2958 sdram_reg = SDRAM_INITPLR7;
2959 mfsdram(sdram_reg, sdram_data);
2960 printf(" SDRAM_INITPLR7 = 0x%08X\n", sdram_data);
2961 sdram_reg = SDRAM_INITPLR8;
2962 mfsdram(sdram_reg, sdram_data);
2963 printf(" SDRAM_INITPLR8 = 0x%08X", sdram_data);
2964 sdram_reg = SDRAM_INITPLR9;
2965 mfsdram(sdram_reg, sdram_data);
2966 printf(" SDRAM_INITPLR9 = 0x%08X\n", sdram_data);
2967 sdram_reg = SDRAM_INITPLR10;
2968 mfsdram(sdram_reg, sdram_data);
2969 printf(" SDRAM_INITPLR10 = 0x%08X", sdram_data);
2970 sdram_reg = SDRAM_INITPLR11;
2971 mfsdram(sdram_reg, sdram_data);
2972 printf(" SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
2973 sdram_reg = SDRAM_INITPLR12;
2974 mfsdram(sdram_reg, sdram_data);
2975 printf(" SDRAM_INITPLR12 = 0x%08X", sdram_data);
2976 sdram_reg = SDRAM_INITPLR13;
2977 mfsdram(sdram_reg, sdram_data);
2978 printf(" SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
2979 sdram_reg = SDRAM_INITPLR14;
2980 mfsdram(sdram_reg, sdram_data);
2981 printf(" SDRAM_INITPLR14 = 0x%08X", sdram_data);
2982 sdram_reg = SDRAM_INITPLR15;
2983 mfsdram(sdram_reg, sdram_data);
2984 printf(" SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
2985 sdram_reg = SDRAM_RQDC;
2986 mfsdram(sdram_reg, sdram_data);
2987 printf(" SDRAM_RQDC = 0x%08X", sdram_data);
2988 sdram_reg = SDRAM_RFDC;
2989 mfsdram(sdram_reg, sdram_data);
2990 printf(" SDRAM_RFDC = 0x%08X\n", sdram_data);
2991 sdram_reg = SDRAM_RDCC;
2992 mfsdram(sdram_reg, sdram_data);
2993 printf(" SDRAM_RDCC = 0x%08X", sdram_data);
2994 sdram_reg = SDRAM_DLCR;
2995 mfsdram(sdram_reg, sdram_data);
2996 printf(" SDRAM_DLCR = 0x%08X\n", sdram_data);
2997 sdram_reg = SDRAM_CLKTR;
2998 mfsdram(sdram_reg, sdram_data);
2999 printf(" SDRAM_CLKTR = 0x%08X", sdram_data);
3000 sdram_reg = SDRAM_WRDTR;
3001 mfsdram(sdram_reg, sdram_data);
3002 printf(" SDRAM_WRDTR = 0x%08X\n", sdram_data);
3003 sdram_reg = SDRAM_SDTR1;
3004 mfsdram(sdram_reg, sdram_data);
3005 printf(" SDRAM_SDTR1 = 0x%08X", sdram_data);
3006 sdram_reg = SDRAM_SDTR2;
3007 mfsdram(sdram_reg, sdram_data);
3008 printf(" SDRAM_SDTR2 = 0x%08X\n", sdram_data);
3009 sdram_reg = SDRAM_SDTR3;
3010 mfsdram(sdram_reg, sdram_data);
3011 printf(" SDRAM_SDTR3 = 0x%08X", sdram_data);
3012 sdram_reg = SDRAM_MMODE;
3013 mfsdram(sdram_reg, sdram_data);
3014 printf(" SDRAM_MMODE = 0x%08X\n", sdram_data);
3015 sdram_reg = SDRAM_MEMODE;
3016 mfsdram(sdram_reg, sdram_data);
3017 printf(" SDRAM_MEMODE = 0x%08X", sdram_data);
3018 sdram_reg = SDRAM_ECCCR;
3019 mfsdram(sdram_reg, sdram_data);
3020 printf(" SDRAM_ECCCR = 0x%08X\n\n", sdram_data);
3021
3022 dcr_data = mfdcr(SDRAM_R0BAS);
3023 printf(" MQ0_B0BAS = 0x%08X", dcr_data);
3024 dcr_data = mfdcr(SDRAM_R1BAS);
3025 printf(" MQ1_B0BAS = 0x%08X\n", dcr_data);
3026 dcr_data = mfdcr(SDRAM_R2BAS);
3027 printf(" MQ2_B0BAS = 0x%08X", dcr_data);
3028 dcr_data = mfdcr(SDRAM_R3BAS);
3029 printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
3030 }
3031 #endif
3032 #endif /* CONFIG_SPD_EEPROM */
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