cpu/ppc4xx/cpu_init.c

   1 /*
   2  * (C) Copyright 2000-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <watchdog.h>
  26 #include <ppc4xx_enet.h>
  27 #include <asm/processor.h>
  28 #include <asm/gpio.h>
  29 #include <ppc4xx.h>
  30
  31 #if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
  32 DECLARE_GLOBAL_DATA_PTR;
  33 #endif
  34
  35 #ifdef CFG_INIT_DCACHE_CS
  36 # if (CFG_INIT_DCACHE_CS == 0)
  37 #  define PBxAP pb0ap
  38 #  define PBxCR pb0cr
  39 #  if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
  40 #   define PBxAP_VAL CFG_EBC_PB0AP
  41 #   define PBxCR_VAL CFG_EBC_PB0CR
  42 #  endif
  43 # endif
  44 # if (CFG_INIT_DCACHE_CS == 1)
  45 #  define PBxAP pb1ap
  46 #  define PBxCR pb1cr
  47 #  if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR))
  48 #   define PBxAP_VAL CFG_EBC_PB1AP
  49 #   define PBxCR_VAL CFG_EBC_PB1CR
  50 #  endif
  51 # endif
  52 # if (CFG_INIT_DCACHE_CS == 2)
  53 #  define PBxAP pb2ap
  54 #  define PBxCR pb2cr
  55 #  if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR))
  56 #   define PBxAP_VAL CFG_EBC_PB2AP
  57 #   define PBxCR_VAL CFG_EBC_PB2CR
  58 #  endif
  59 # endif
  60 # if (CFG_INIT_DCACHE_CS == 3)
  61 #  define PBxAP pb3ap
  62 #  define PBxCR pb3cr
  63 #  if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR))
  64 #   define PBxAP_VAL CFG_EBC_PB3AP
  65 #   define PBxCR_VAL CFG_EBC_PB3CR
  66 #  endif
  67 # endif
  68 # if (CFG_INIT_DCACHE_CS == 4)
  69 #  define PBxAP pb4ap
  70 #  define PBxCR pb4cr
  71 #  if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR))
  72 #   define PBxAP_VAL CFG_EBC_PB4AP
  73 #   define PBxCR_VAL CFG_EBC_PB4CR
  74 #  endif
  75 # endif
  76 # if (CFG_INIT_DCACHE_CS == 5)
  77 #  define PBxAP pb5ap
  78 #  define PBxCR pb5cr
  79 #  if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR))
  80 #   define PBxAP_VAL CFG_EBC_PB5AP
  81 #   define PBxCR_VAL CFG_EBC_PB5CR
  82 #  endif
  83 # endif
  84 # if (CFG_INIT_DCACHE_CS == 6)
  85 #  define PBxAP pb6ap
  86 #  define PBxCR pb6cr
  87 #  if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR))
  88 #   define PBxAP_VAL CFG_EBC_PB6AP
  89 #   define PBxCR_VAL CFG_EBC_PB6CR
  90 #  endif
  91 # endif
  92 # if (CFG_INIT_DCACHE_CS == 7)
  93 #  define PBxAP pb7ap
  94 #  define PBxCR pb7cr
  95 #  if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR))
  96 #   define PBxAP_VAL CFG_EBC_PB7AP
  97 #   define PBxCR_VAL CFG_EBC_PB7CR
  98 #  endif
  99 # endif
 100 #endif /* CFG_INIT_DCACHE_CS */
 101
 102 /*
 103  * Breath some life into the CPU...
 104  *
 105  * Set up the memory map,
 106  * initialize a bunch of registers
 107  */
 108 void
 109 cpu_init_f (void)
 110 {
 111 #if defined(CONFIG_WATCHDOG)
 112         unsigned long val;
 113 #endif
 114
 115 #if defined(CONFIG_405EP)
 116         /*
 117          * GPIO0 setup (select GPIO or alternate function)
 118          */
 119 #if defined(CFG_GPIO0_OR)
 120         out32(GPIO0_OR, CFG_GPIO0_OR);          /* set initial state of output pins     */
 121 #endif
 122 #if defined(CFG_GPIO0_ODR)
 123         out32(GPIO0_ODR, CFG_GPIO0_ODR);        /* open-drain select                    */
 124 #endif
 125         out32(GPIO0_OSRH, CFG_GPIO0_OSRH);      /* output select                        */
 126         out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
 127         out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);    /* input select                         */
 128         out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
 129         out32(GPIO0_TSRH, CFG_GPIO0_TSRH);      /* three-state select                   */
 130         out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
 131         out32(GPIO0_TCR, CFG_GPIO0_TCR);        /* enable output driver for outputs     */
 132
 133         /*
 134          * Set EMAC noise filter bits
 135          */
 136         mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE);
 137 #endif /* CONFIG_405EP */
 138
 139 #if defined(CFG_440_GPIO_TABLE)
 140         gpio_set_chip_configuration();
 141 #endif /* CFG_440_GPIO_TABLE */
 142
 143         /*
 144          * External Bus Controller (EBC) Setup
 145          */
 146 #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
 147 #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
 148      defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
 149      defined(CONFIG_405))
 150         /*
 151          * Move the next instructions into icache, since these modify the flash
 152          * we are running from!
 153          */
 154         asm volatile("  bl      0f"             ::: "lr");
 155         asm volatile("0:        mflr    3"              ::: "r3");
 156         asm volatile("  addi    4, 0, 14"       ::: "r4");
 157         asm volatile("  mtctr   4"              ::: "ctr");
 158         asm volatile("1:        icbt    0, 3");
 159         asm volatile("  addi    3, 3, 32"       ::: "r3");
 160         asm volatile("  bdnz    1b"             ::: "ctr", "cr0");
 161         asm volatile("  addis   3, 0, 0x0"      ::: "r3");
 162         asm volatile("  ori     3, 3, 0xA000"   ::: "r3");
 163         asm volatile("  mtctr   3"              ::: "ctr");
 164         asm volatile("2:        bdnz    2b"             ::: "ctr", "cr0");
 165 #endif
 166
 167         mtebc(pb0ap, CFG_EBC_PB0AP);
 168         mtebc(pb0cr, CFG_EBC_PB0CR);
 169 #endif
 170
 171 #if (defined(CFG_EBC_PB1AP) && defined(CFG_EBC_PB1CR) && !(CFG_INIT_DCACHE_CS == 1))
 172         mtebc(pb1ap, CFG_EBC_PB1AP);
 173         mtebc(pb1cr, CFG_EBC_PB1CR);
 174 #endif
 175
 176 #if (defined(CFG_EBC_PB2AP) && defined(CFG_EBC_PB2CR) && !(CFG_INIT_DCACHE_CS == 2))
 177         mtebc(pb2ap, CFG_EBC_PB2AP);
 178         mtebc(pb2cr, CFG_EBC_PB2CR);
 179 #endif
 180
 181 #if (defined(CFG_EBC_PB3AP) && defined(CFG_EBC_PB3CR) && !(CFG_INIT_DCACHE_CS == 3))
 182         mtebc(pb3ap, CFG_EBC_PB3AP);
 183         mtebc(pb3cr, CFG_EBC_PB3CR);
 184 #endif
 185
 186 #if (defined(CFG_EBC_PB4AP) && defined(CFG_EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
 187         mtebc(pb4ap, CFG_EBC_PB4AP);
 188         mtebc(pb4cr, CFG_EBC_PB4CR);
 189 #endif
 190
 191 #if (defined(CFG_EBC_PB5AP) && defined(CFG_EBC_PB5CR) && !(CFG_INIT_DCACHE_CS == 5))
 192         mtebc(pb5ap, CFG_EBC_PB5AP);
 193         mtebc(pb5cr, CFG_EBC_PB5CR);
 194 #endif
 195
 196 #if (defined(CFG_EBC_PB6AP) && defined(CFG_EBC_PB6CR) && !(CFG_INIT_DCACHE_CS == 6))
 197         mtebc(pb6ap, CFG_EBC_PB6AP);
 198         mtebc(pb6cr, CFG_EBC_PB6CR);
 199 #endif
 200
 201 #if (defined(CFG_EBC_PB7AP) && defined(CFG_EBC_PB7CR) && !(CFG_INIT_DCACHE_CS == 7))
 202         mtebc(pb7ap, CFG_EBC_PB7AP);
 203         mtebc(pb7cr, CFG_EBC_PB7CR);
 204 #endif
 205
 206 #if defined (CFG_EBC_CFG)
 207         mtebc(EBC0_CFG, CFG_EBC_CFG);
 208 #endif
 209
 210 #if defined(CONFIG_WATCHDOG)
 211         val = mfspr(tcr);
 212 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 213         val |= 0xb8000000;      /* generate system reset after 1.34 seconds */
 214 #elif defined(CONFIG_440EPX)
 215         val |= 0xb0000000;      /* generate system reset after 1.34 seconds */
 216 #else
 217         val |= 0xf0000000;      /* generate system reset after 2.684 seconds */
 218 #endif
 219 #if defined(CFG_4xx_RESET_TYPE)
 220         val &= ~0x30000000;                     /* clear WRC bits */
 221         val |= CFG_4xx_RESET_TYPE << 28;        /* set board specific WRC type */
 222 #endif
 223         mtspr(tcr, val);
 224
 225         val = mfspr(tsr);
 226         val |= 0x80000000;      /* enable watchdog timer */
 227         mtspr(tsr, val);
 228
 229         reset_4xx_watchdog();
 230 #endif /* CONFIG_WATCHDOG */
 231 }
 232
 233 /*
 234  * initialize higher level parts of CPU like time base and timers
 235  */
 236 int cpu_init_r (void)
 237 {
 238 #if defined(CONFIG_405GP)  || defined(CONFIG_405EP)
 239         bd_t *bd = gd->bd;
 240         unsigned long reg;
 241 #if defined(CONFIG_405GP)
 242         uint pvr = get_pvr();
 243 #endif
 244
 245 #ifdef CFG_INIT_DCACHE_CS
 246         /*
 247          * Flush and invalidate dcache, then disable CS for temporary stack.
 248          * Afterwards, this CS can be used for other purposes
 249          */
 250         dcache_disable();   /* flush and invalidate dcache */
 251         mtebc(PBxAP, 0);
 252         mtebc(PBxCR, 0);    /* disable CS for temporary stack */
 253
 254 #if (defined(PBxAP_VAL) && defined(PBxCR_VAL))
 255         /*
 256          * Write new value into CS register
 257          */
 258         mtebc(PBxAP, PBxAP_VAL);
 259         mtebc(PBxCR, PBxCR_VAL);
 260 #endif
 261 #endif /* CFG_INIT_DCACHE_CS */
 262
 263         /*
 264          * Write Ethernetaddress into on-chip register
 265          */
 266         reg = 0x00000000;
 267         reg |= bd->bi_enetaddr[0];           /* set high address */
 268         reg = reg << 8;
 269         reg |= bd->bi_enetaddr[1];
 270         out32 (EMAC_IAH, reg);
 271
 272         reg = 0x00000000;
 273         reg |= bd->bi_enetaddr[2];           /* set low address  */
 274         reg = reg << 8;
 275         reg |= bd->bi_enetaddr[3];
 276         reg = reg << 8;
 277         reg |= bd->bi_enetaddr[4];
 278         reg = reg << 8;
 279         reg |= bd->bi_enetaddr[5];
 280         out32 (EMAC_IAL, reg);
 281
 282 #if defined(CONFIG_405GP)
 283         /*
 284          * Set edge conditioning circuitry on PPC405GPr
 285          * for compatibility to existing PPC405GP designs.
 286          */
 287         if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
 288                 mtdcr(ecr, 0x60606000);
 289         }
 290 #endif  /* defined(CONFIG_405GP) */
 291 #endif  /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */
 292         return (0);
 293 }