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git.ipfire.org Git - people/ms/u-boot.git/blob - cpu/ppc4xx/gpio.c
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 #if defined(CFG_4xx_GPIO_TABLE)
30 gpio_param_s gpio_tab
[GPIO_GROUP_MAX
][GPIO_MAX
] = CFG_4xx_GPIO_TABLE
;
33 #if defined(GPIO0_OSRL)
34 /* Only some 4xx variants support alternate funtions on the GPIO's */
35 void gpio_config(int pin
, int in_out
, int gpio_alt
, int out_val
)
44 if (pin
>= GPIO_MAX
) {
49 if (pin
>= GPIO_MAX
/2) {
51 pin2
= (pin
- GPIO_MAX
/2) << 1;
54 mask
= 0x80000000 >> pin
;
55 mask2
= 0xc0000000 >> (pin2
<< 1);
57 /* first set TCR to 0 */
58 out_be32((void *)GPIO0_TCR
+ offs
, in_be32((void *)GPIO0_TCR
+ offs
) & ~mask
);
60 if (in_out
== GPIO_OUT
) {
61 val
= in_be32((void *)GPIO0_OSRL
+ offs
+ offs2
) & ~mask2
;
64 val
|= GPIO_ALT1_SEL
>> pin2
;
67 val
|= GPIO_ALT2_SEL
>> pin2
;
70 val
|= GPIO_ALT3_SEL
>> pin2
;
73 out_be32((void *)GPIO0_OSRL
+ offs
+ offs2
, val
);
75 /* setup requested output value */
76 if (out_val
== GPIO_OUT_0
)
77 out_be32((void *)GPIO0_OR
+ offs
,
78 in_be32((void *)GPIO0_OR
+ offs
) & ~mask
);
79 else if (out_val
== GPIO_OUT_1
)
80 out_be32((void *)GPIO0_OR
+ offs
,
81 in_be32((void *)GPIO0_OR
+ offs
) | mask
);
83 /* now configure TCR to drive output if selected */
84 out_be32((void *)GPIO0_TCR
+ offs
,
85 in_be32((void *)GPIO0_TCR
+ offs
) | mask
);
87 val
= in_be32((void *)GPIO0_ISR1L
+ offs
+ offs2
) & ~mask2
;
88 val
|= GPIO_IN_SEL
>> pin2
;
89 out_be32((void *)GPIO0_ISR1L
+ offs
+ offs2
, val
);
92 #endif /* GPIO_OSRL */
94 void gpio_write_bit(int pin
, int val
)
98 if (pin
>= GPIO_MAX
) {
104 out_be32((void *)GPIO0_OR
+ offs
,
105 in_be32((void *)GPIO0_OR
+ offs
) | GPIO_VAL(pin
));
107 out_be32((void *)GPIO0_OR
+ offs
,
108 in_be32((void *)GPIO0_OR
+ offs
) & ~GPIO_VAL(pin
));
111 int gpio_read_out_bit(int pin
)
115 if (pin
>= GPIO_MAX
) {
120 return (in_be32((void *)GPIO0_OR
+ offs
) & GPIO_VAL(pin
) ? 1 : 0);
123 #if defined(CFG_4xx_GPIO_TABLE)
124 void gpio_set_chip_configuration(void)
126 unsigned char i
=0, j
=0, offs
=0, gpio_core
;
127 unsigned long reg
, core_add
;
129 for (gpio_core
=0; gpio_core
<GPIO_GROUP_MAX
; gpio_core
++) {
132 /* GPIO config of the GPIOs 0 to 31 */
133 for (i
=0; i
<GPIO_MAX
; i
++, j
++) {
134 if (i
== GPIO_MAX
/2) {
139 core_add
= gpio_tab
[gpio_core
][i
].add
;
141 if ((gpio_tab
[gpio_core
][i
].in_out
== GPIO_IN
) ||
142 (gpio_tab
[gpio_core
][i
].in_out
== GPIO_BI
)) {
144 switch (gpio_tab
[gpio_core
][i
].alt_nb
) {
149 reg
= in_be32((void *)GPIO_IS1(core_add
+offs
))
150 & ~(GPIO_MASK
>> (j
*2));
151 reg
= reg
| (GPIO_IN_SEL
>> (j
*2));
152 out_be32((void *)GPIO_IS1(core_add
+offs
), reg
);
156 reg
= in_be32((void *)GPIO_IS2(core_add
+offs
))
157 & ~(GPIO_MASK
>> (j
*2));
158 reg
= reg
| (GPIO_IN_SEL
>> (j
*2));
159 out_be32((void *)GPIO_IS2(core_add
+offs
), reg
);
163 reg
= in_be32((void *)GPIO_IS3(core_add
+offs
))
164 & ~(GPIO_MASK
>> (j
*2));
165 reg
= reg
| (GPIO_IN_SEL
>> (j
*2));
166 out_be32((void *)GPIO_IS3(core_add
+offs
), reg
);
171 if ((gpio_tab
[gpio_core
][i
].in_out
== GPIO_OUT
) ||
172 (gpio_tab
[gpio_core
][i
].in_out
== GPIO_BI
)) {
174 switch (gpio_tab
[gpio_core
][i
].alt_nb
) {
180 * else -> don't touch
182 reg
= in_be32((void *)GPIO_OR(core_add
));
183 if (gpio_tab
[gpio_core
][i
].out_val
== GPIO_OUT_1
)
184 reg
|= (0x80000000 >> (i
));
185 else if (gpio_tab
[gpio_core
][i
].out_val
== GPIO_OUT_0
)
186 reg
&= ~(0x80000000 >> (i
));
187 out_be32((void *)GPIO_OR(core_add
), reg
);
189 reg
= in_be32((void *)GPIO_TCR(core_add
)) |
191 out_be32((void *)GPIO_TCR(core_add
), reg
);
193 reg
= in_be32((void *)GPIO_OS(core_add
+offs
))
194 & ~(GPIO_MASK
>> (j
*2));
195 out_be32((void *)GPIO_OS(core_add
+offs
), reg
);
196 reg
= in_be32((void *)GPIO_TS(core_add
+offs
))
197 & ~(GPIO_MASK
>> (j
*2));
198 out_be32((void *)GPIO_TS(core_add
+offs
), reg
);
202 reg
= in_be32((void *)GPIO_OS(core_add
+offs
))
203 & ~(GPIO_MASK
>> (j
*2));
204 reg
= reg
| (GPIO_ALT1_SEL
>> (j
*2));
205 out_be32((void *)GPIO_OS(core_add
+offs
), reg
);
206 reg
= in_be32((void *)GPIO_TS(core_add
+offs
))
207 & ~(GPIO_MASK
>> (j
*2));
208 reg
= reg
| (GPIO_ALT1_SEL
>> (j
*2));
209 out_be32((void *)GPIO_TS(core_add
+offs
), reg
);
213 reg
= in_be32((void *)GPIO_OS(core_add
+offs
))
214 & ~(GPIO_MASK
>> (j
*2));
215 reg
= reg
| (GPIO_ALT2_SEL
>> (j
*2));
216 out_be32((void *)GPIO_OS(core_add
+offs
), reg
);
217 reg
= in_be32((void *)GPIO_TS(core_add
+offs
))
218 & ~(GPIO_MASK
>> (j
*2));
219 reg
= reg
| (GPIO_ALT2_SEL
>> (j
*2));
220 out_be32((void *)GPIO_TS(core_add
+offs
), reg
);
224 reg
= in_be32((void *)GPIO_OS(core_add
+offs
))
225 & ~(GPIO_MASK
>> (j
*2));
226 reg
= reg
| (GPIO_ALT3_SEL
>> (j
*2));
227 out_be32((void *)GPIO_OS(core_add
+offs
), reg
);
228 reg
= in_be32((void *)GPIO_TS(core_add
+offs
))
229 & ~(GPIO_MASK
>> (j
*2));
230 reg
= reg
| (GPIO_ALT3_SEL
>> (j
*2));
231 out_be32((void *)GPIO_TS(core_add
+offs
), reg
);
238 #endif /* CFG_4xx_GPIO_TABLE */