cpu/ppc4xx/i2c.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
   6  *
   7  * (C) Copyright 2001
   8  * Bill Hunter,  Wave 7 Optics, williamhunter@mediaone.net
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <ppc4xx.h>
  31 #include <4xx_i2c.h>
  32 #include <i2c.h>
  33 #include <asm-ppc/io.h>
  34
  35 #ifdef CONFIG_HARD_I2C
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #if defined(CONFIG_I2C_MULTI_BUS)
  40 /* Initialize the bus pointer to whatever one the SPD EEPROM is on.
  41  * Default is bus 0.  This is necessary because the DDR initialization
  42  * runs from ROM, and we can't switch buses because we can't modify
  43  * the global variables.
  44  */
  45 #ifdef CFG_SPD_BUS_NUM
  46 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
  47 #else
  48 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
  49 #endif
  50 #endif /* CONFIG_I2C_MULTI_BUS */
  51
  52 static void _i2c_bus_reset(void)
  53 {
  54         int i;
  55         u8 dc;
  56
  57         /* Reset status register */
  58         /* write 1 in SCMP and IRQA to clear these fields */
  59         out_8((u8 *)IIC_STS, 0x0A);
  60
  61         /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
  62         out_8((u8 *)IIC_EXTSTS, 0x8F);
  63
  64         /* Place chip in the reset state */
  65         out_8((u8 *)IIC_XTCNTLSS, IIC_XTCNTLSS_SRST);
  66
  67         /* Check if bus is free */
  68         dc = in_8((u8 *)IIC_DIRECTCNTL);
  69         if (!DIRCTNL_FREE(dc)){
  70                 /* Try to set bus free state */
  71                 out_8((u8 *)IIC_DIRECTCNTL, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
  72
  73                 /* Wait until we regain bus control */
  74                 for (i = 0; i < 100; ++i) {
  75                         dc = in_8((u8 *)IIC_DIRECTCNTL);
  76                         if (DIRCTNL_FREE(dc))
  77                                 break;
  78
  79                         /* Toggle SCL line */
  80                         dc ^= IIC_DIRCNTL_SCC;
  81                         out_8((u8 *)IIC_DIRECTCNTL, dc);
  82                         udelay(10);
  83                         dc ^= IIC_DIRCNTL_SCC;
  84                         out_8((u8 *)IIC_DIRECTCNTL, dc);
  85                 }
  86         }
  87
  88         /* Remove reset */
  89         out_8((u8 *)IIC_XTCNTLSS, 0);
  90 }
  91
  92 void i2c_init(int speed, int slaveadd)
  93 {
  94         sys_info_t sysInfo;
  95         unsigned long freqOPB;
  96         int val, divisor;
  97         int bus;
  98
  99 #ifdef CFG_I2C_INIT_BOARD
 100         /* call board specific i2c bus reset routine before accessing the   */
 101         /* environment, which might be in a chip on that bus. For details   */
 102         /* about this problem see doc/I2C_Edge_Conditions.                  */
 103         i2c_init_board();
 104 #endif
 105
 106         for (bus = 0; bus < CFG_MAX_I2C_BUS; bus++) {
 107                 I2C_SET_BUS(bus);
 108
 109                 /* Handle possible failed I2C state */
 110                 /* FIXME: put this into i2c_init_board()? */
 111                 _i2c_bus_reset();
 112
 113                 /* clear lo master address */
 114                 out_8((u8 *)IIC_LMADR, 0);
 115
 116                 /* clear hi master address */
 117                 out_8((u8 *)IIC_HMADR, 0);
 118
 119                 /* clear lo slave address */
 120                 out_8((u8 *)IIC_LSADR, 0);
 121
 122                 /* clear hi slave address */
 123                 out_8((u8 *)IIC_HSADR, 0);
 124
 125                 /* Clock divide Register */
 126                 /* get OPB frequency */
 127                 get_sys_info(&sysInfo);
 128                 freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv;
 129                 /* set divisor according to freqOPB */
 130                 divisor = (freqOPB - 1) / 10000000;
 131                 if (divisor == 0)
 132                         divisor = 1;
 133                 out_8((u8 *)IIC_CLKDIV, divisor);
 134
 135                 /* no interrupts */
 136                 out_8((u8 *)IIC_INTRMSK, 0);
 137
 138                 /* clear transfer count */
 139                 out_8((u8 *)IIC_XFRCNT, 0);
 140
 141                 /* clear extended control & stat */
 142                 /* write 1 in SRC SRS SWC SWS to clear these fields */
 143                 out_8((u8 *)IIC_XTCNTLSS, 0xF0);
 144
 145                 /* Mode Control Register
 146                    Flush Slave/Master data buffer */
 147                 out_8((u8 *)IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
 148
 149                 val = in_8((u8 *)IIC_MDCNTL);
 150
 151                 /* Ignore General Call, slave transfers are ignored,
 152                  * disable interrupts, exit unknown bus state, enable hold
 153                  * SCL 100kHz normaly or FastMode for 400kHz and above
 154                  */
 155
 156                 val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
 157                 if (speed >= 400000)
 158                         val |= IIC_MDCNTL_FSM;
 159                 out_8((u8 *)IIC_MDCNTL, val);
 160
 161                 /* clear control reg */
 162                 out_8((u8 *)IIC_CNTL, 0x00);
 163         }
 164
 165         /* set to SPD bus as default bus upon powerup */
 166         I2C_SET_BUS(CFG_SPD_BUS_NUM);
 167 }
 168
 169 /*
 170  * This code tries to use the features of the 405GP i2c
 171  * controller. It will transfer up to 4 bytes in one pass
 172  * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
 173  * is possible to do out16(lhz) transfers.
 174  *
 175  * cmd_type is 0 for write 1 for read.
 176  *
 177  * addr_len can take any value from 0-255, it is only limited
 178  * by the char, we could make it larger if needed. If it is
 179  * 0 we skip the address write cycle.
 180  *
 181  * Typical case is a Write of an addr followd by a Read. The
 182  * IBM FAQ does not cover this. On the last byte of the write
 183  * we don't set the creg CHT bit, and on the first bytes of the
 184  * read we set the RPST bit.
 185  *
 186  * It does not support address only transfers, there must be
 187  * a data part. If you want to write the address yourself, put
 188  * it in the data pointer.
 189  *
 190  * It does not support transfer to/from address 0.
 191  *
 192  * It does not check XFRCNT.
 193  */
 194 static int i2c_transfer(unsigned char cmd_type,
 195                         unsigned char chip,
 196                         unsigned char addr[],
 197                         unsigned char addr_len,
 198                         unsigned char data[],
 199                         unsigned short data_len)
 200 {
 201         unsigned char* ptr;
 202         int reading;
 203         int tran,cnt;
 204         int result;
 205         int status;
 206         int i;
 207         uchar creg;
 208
 209         if (data == 0 || data_len == 0) {
 210                 /* Don't support data transfer of no length or to address 0 */
 211                 printf( "i2c_transfer: bad call\n" );
 212                 return IIC_NOK;
 213         }
 214         if (addr && addr_len) {
 215                 ptr = addr;
 216                 cnt = addr_len;
 217                 reading = 0;
 218         } else {
 219                 ptr = data;
 220                 cnt = data_len;
 221                 reading = cmd_type;
 222         }
 223
 224         /* Clear Stop Complete Bit */
 225         out_8((u8 *)IIC_STS, IIC_STS_SCMP);
 226         /* Check init */
 227         i = 10;
 228         do {
 229                 /* Get status */
 230                 status = in_8((u8 *)IIC_STS);
 231                 i--;
 232         } while ((status & IIC_STS_PT) && (i > 0));
 233
 234         if (status & IIC_STS_PT) {
 235                 result = IIC_NOK_TOUT;
 236                 return(result);
 237         }
 238         /* flush the Master/Slave Databuffers */
 239         out_8((u8 *)IIC_MDCNTL, ((in_8((u8 *)IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
 240         /* need to wait 4 OPB clocks? code below should take that long */
 241
 242         /* 7-bit adressing */
 243         out_8((u8 *)IIC_HMADR, 0);
 244         out_8((u8 *)IIC_LMADR, chip);
 245
 246         tran = 0;
 247         result = IIC_OK;
 248         creg = 0;
 249
 250         while (tran != cnt && (result == IIC_OK)) {
 251                 int  bc,j;
 252
 253                 /* Control register =
 254                  * Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
 255                  * Transfer is a sequence of transfers
 256                  */
 257                 creg |= IIC_CNTL_PT;
 258
 259                 bc = (cnt - tran) > 4 ? 4 : cnt - tran;
 260                 creg |= (bc - 1) << 4;
 261                 /* if the real cmd type is write continue trans */
 262                 if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
 263                         creg |= IIC_CNTL_CHT;
 264
 265                 if (reading)
 266                         creg |= IIC_CNTL_READ;
 267                 else
 268                         for(j=0; j < bc; j++)
 269                                 /* Set buffer */
 270                                 out_8((u8 *)IIC_MDBUF, ptr[tran+j]);
 271                 out_8((u8 *)IIC_CNTL, creg);
 272
 273                 /* Transfer is in progress
 274                  * we have to wait for upto 5 bytes of data
 275                  * 1 byte chip address+r/w bit then bc bytes
 276                  * of data.
 277                  * udelay(10) is 1 bit time at 100khz
 278                  * Doubled for slop. 20 is too small.
 279                  */
 280                 i = 2*5*8;
 281                 do {
 282                         /* Get status */
 283                         status = in_8((u8 *)IIC_STS);
 284                         udelay(10);
 285                         i--;
 286                 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && (i > 0));
 287
 288                 if (status & IIC_STS_ERR) {
 289                         result = IIC_NOK;
 290                         status = in_8((u8 *)IIC_EXTSTS);
 291                         /* Lost arbitration? */
 292                         if (status & IIC_EXTSTS_LA)
 293                                 result = IIC_NOK_LA;
 294                         /* Incomplete transfer? */
 295                         if (status & IIC_EXTSTS_ICT)
 296                                 result = IIC_NOK_ICT;
 297                         /* Transfer aborted? */
 298                         if (status & IIC_EXTSTS_XFRA)
 299                                 result = IIC_NOK_XFRA;
 300                 } else if ( status & IIC_STS_PT) {
 301                         result = IIC_NOK_TOUT;
 302                 }
 303                 /* Command is reading => get buffer */
 304                 if ((reading) && (result == IIC_OK)) {
 305                         /* Are there data in buffer */
 306                         if (status & IIC_STS_MDBS) {
 307                                 /*
 308                                  * even if we have data we have to wait 4OPB clocks
 309                                  * for it to hit the front of the FIFO, after that
 310                                  * we can just read. We should check XFCNT here and
 311                                  * if the FIFO is full there is no need to wait.
 312                                  */
 313                                 udelay(1);
 314                                 for (j=0; j<bc; j++)
 315                                         ptr[tran+j] = in_8((u8 *)IIC_MDBUF);
 316                         } else
 317                                 result = IIC_NOK_DATA;
 318                 }
 319                 creg = 0;
 320                 tran += bc;
 321                 if (ptr == addr && tran == cnt) {
 322                         ptr = data;
 323                         cnt = data_len;
 324                         tran = 0;
 325                         reading = cmd_type;
 326                         if (reading)
 327                                 creg = IIC_CNTL_RPST;
 328                 }
 329         }
 330         return (result);
 331 }
 332
 333 int i2c_probe(uchar chip)
 334 {
 335         uchar buf[1];
 336
 337         buf[0] = 0;
 338
 339         /*
 340          * What is needed is to send the chip address and verify that the
 341          * address was <ACK>ed (i.e. there was a chip at that address which
 342          * drove the data line low).
 343          */
 344         return (i2c_transfer(1, chip << 1, 0,0, buf, 1) != 0);
 345 }
 346
 347
 348 int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
 349 {
 350         uchar xaddr[4];
 351         int ret;
 352
 353         if (alen > 4) {
 354                 printf ("I2C read: addr len %d not supported\n", alen);
 355                 return 1;
 356         }
 357
 358         if (alen > 0) {
 359                 xaddr[0] = (addr >> 24) & 0xFF;
 360                 xaddr[1] = (addr >> 16) & 0xFF;
 361                 xaddr[2] = (addr >> 8) & 0xFF;
 362                 xaddr[3] = addr & 0xFF;
 363         }
 364
 365
 366 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
 367         /*
 368          * EEPROM chips that implement "address overflow" are ones
 369          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 370          * address and the extra bits end up in the "chip address"
 371          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 372          * four 256 byte chips.
 373          *
 374          * Note that we consider the length of the address field to
 375          * still be one byte because the extra address bits are
 376          * hidden in the chip address.
 377          */
 378         if (alen > 0)
 379                 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
 380 #endif
 381         if ((ret = i2c_transfer(1, chip<<1, &xaddr[4-alen], alen, buffer, len)) != 0) {
 382                 if (gd->have_console)
 383                         printf( "I2c read: failed %d\n", ret);
 384                 return 1;
 385         }
 386         return 0;
 387 }
 388
 389 int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
 390 {
 391         uchar xaddr[4];
 392
 393         if (alen > 4) {
 394                 printf ("I2C write: addr len %d not supported\n", alen);
 395                 return 1;
 396
 397         }
 398
 399         if (alen > 0) {
 400                 xaddr[0] = (addr >> 24) & 0xFF;
 401                 xaddr[1] = (addr >> 16) & 0xFF;
 402                 xaddr[2] = (addr >> 8) & 0xFF;
 403                 xaddr[3] = addr & 0xFF;
 404         }
 405
 406 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
 407         /*
 408          * EEPROM chips that implement "address overflow" are ones
 409          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 410          * address and the extra bits end up in the "chip address"
 411          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 412          * four 256 byte chips.
 413          *
 414          * Note that we consider the length of the address field to
 415          * still be one byte because the extra address bits are
 416          * hidden in the chip address.
 417          */
 418         if (alen > 0)
 419                 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
 420 #endif
 421
 422         return (i2c_transfer(0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
 423 }
 424
 425 /*-----------------------------------------------------------------------
 426  * Read a register
 427  */
 428 uchar i2c_reg_read(uchar i2c_addr, uchar reg)
 429 {
 430         uchar buf;
 431
 432         i2c_read(i2c_addr, reg, 1, &buf, 1);
 433
 434         return (buf);
 435 }
 436
 437 /*-----------------------------------------------------------------------
 438  * Write a register
 439  */
 440 void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
 441 {
 442         i2c_write(i2c_addr, reg, 1, &val, 1);
 443 }
 444
 445 #if defined(CONFIG_I2C_MULTI_BUS)
 446 /*
 447  * Functions for multiple I2C bus handling
 448  */
 449 unsigned int i2c_get_bus_num(void)
 450 {
 451         return i2c_bus_num;
 452 }
 453
 454 int i2c_set_bus_num(unsigned int bus)
 455 {
 456         if (bus >= CFG_MAX_I2C_BUS)
 457                 return -1;
 458
 459         i2c_bus_num = bus;
 460
 461         return 0;
 462 }
 463 #endif  /* CONFIG_I2C_MULTI_BUS */
 464
 465 /* TODO: add 100/400k switching */
 466 unsigned int i2c_get_bus_speed(void)
 467 {
 468         return CFG_I2C_SPEED;
 469 }
 470
 471 int i2c_set_bus_speed(unsigned int speed)
 472 {
 473         if (speed != CFG_I2C_SPEED)
 474                 return -1;
 475
 476         return 0;
 477 }
 478 #endif  /* CONFIG_HARD_I2C */