cpu/ppc4xx/miiphy.c

   1 /*-----------------------------------------------------------------------------+
   2   |
   3   |       This source code has been made available to you by IBM on an AS-IS
   4   |       basis.  Anyone receiving this source is licensed under IBM
   5   |       copyrights to use it in any way he or she deems fit, including
   6   |       copying it, modifying it, compiling it, and redistributing it either
   7   |       with or without modifications.  No license under IBM patents or
   8   |       patent applications is to be implied by the copyright license.
   9   |
  10   |       Any user of this software should understand that IBM cannot provide
  11   |       technical support for this software and will not be responsible for
  12   |       any consequences resulting from the use of this software.
  13   |
  14   |       Any person who transfers this source code or any derivative work
  15   |       must include the IBM copyright notice, this paragraph, and the
  16   |       preceding two paragraphs in the transferred software.
  17   |
  18   |       COPYRIGHT   I B M   CORPORATION 1995
  19   |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  20   +-----------------------------------------------------------------------------*/
  21 /*-----------------------------------------------------------------------------+
  22   |
  23   |  File Name:  miiphy.c
  24   |
  25   |  Function:   This module has utilities for accessing the MII PHY through
  26   |            the EMAC3 macro.
  27   |
  28   |  Author:     Mark Wisner
  29   |
  30   |  Change Activity-
  31   |
  32   |  Date        Description of Change                                       BY
  33   |  ---------   ---------------------                                       ---
  34   |  05-May-99   Created                                                     MKW
  35   |  01-Jul-99   Changed clock setting of sta_reg from 66Mhz to 50Mhz to
  36   |              better match OPB speed. Also modified delay times.                JWB
  37   |  29-Jul-99   Added Full duplex support                                   MKW
  38   |  24-Aug-99   Removed printf from dp83843_duplex()                      JWB
  39   |  19-Jul-00   Ported to esd cpci405                                       sr
  40   |
  41   +-----------------------------------------------------------------------------*/
  42
  43 #include <common.h>
  44 #include <asm/processor.h>
  45 #include <ppc_asm.tmpl>
  46 #include <commproc.h>
  47 #include <405gp_enet.h>
  48 #include <405_mal.h>
  49 #include <miiphy.h>
  50
  51 #if (defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440)) \
  52    && !defined (CONFIG_NET_MULTI)
  53
  54 /***********************************************************/
  55 /* Dump out to the screen PHY regs                         */
  56 /***********************************************************/
  57
  58 void miiphy_dump (unsigned char addr)
  59 {
  60         unsigned long i;
  61         unsigned short data;
  62
  63
  64         for (i = 0; i < 0x1A; i++) {
  65                 if (miiphy_read (addr, i, &data)) {
  66                         printf ("read error for reg %lx\n", i);
  67                         return;
  68                 }
  69                 printf ("Phy reg %lx ==> %4x\n", i, data);
  70
  71                 /* jump to the next set of regs */
  72                 if (i == 0x07)
  73                         i = 0x0f;
  74
  75         } /* end for loop */
  76 } /* end dump */
  77
  78
  79 /***********************************************************/
  80 /* read a phy reg and return the value with a rc           */
  81 /***********************************************************/
  82
  83 int miiphy_read (unsigned char addr, unsigned char reg,
  84                                  unsigned short *value)
  85 {
  86         unsigned long sta_reg;          /* STA scratch area */
  87         unsigned long i;
  88
  89         /* see if it is ready for 1000 nsec */
  90         i = 0;
  91
  92         /* see if it is ready for  sec */
  93         while ((in32 (EMAC_STACR) & EMAC_STACR_OC) == 0) {
  94                 udelay (7);
  95                 if (i > 5) {
  96 #if 0   /* test-only */
  97                         printf ("read err 1\n");
  98 #endif
  99                         return -1;
 100                 }
 101                 i++;
 102         }
 103         sta_reg = reg;                          /* reg address */
 104         /* set clock (50Mhz) and read flags */
 105         sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
 106 #ifdef CONFIG_PHY_CLK_FREQ
 107         sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
 108 #endif
 109         sta_reg = sta_reg | (addr << 5);        /* Phy address */
 110
 111         out32 (EMAC_STACR, sta_reg);
 112 #if 0   /* test-only */
 113         printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg);      /* test-only */
 114 #endif
 115
 116         sta_reg = in32 (EMAC_STACR);
 117         i = 0;
 118         while ((sta_reg & EMAC_STACR_OC) == 0) {
 119                 udelay (7);
 120                 if (i > 5) {
 121 #if 0   /* test-only */
 122                         printf ("read err 2\n");
 123 #endif
 124                         return -1;
 125                 }
 126                 i++;
 127                 sta_reg = in32 (EMAC_STACR);
 128         }
 129         if ((sta_reg & EMAC_STACR_PHYE) != 0) {
 130 #if 0   /* test-only */
 131                 printf ("read err 3\n");
 132                 printf ("a2: read: EMAC_STACR=0x%0lx, i=%d\n",
 133                         sta_reg, (int) i);      /* test-only */
 134 #endif
 135                 return -1;
 136         }
 137
 138         *value = *(short *) (&sta_reg);
 139         return 0;
 140
 141
 142 } /* phy_read */
 143
 144
 145 /***********************************************************/
 146 /* write a phy reg and return the value with a rc           */
 147 /***********************************************************/
 148
 149 int miiphy_write (unsigned char addr, unsigned char reg,
 150                   unsigned short value)
 151 {
 152         unsigned long sta_reg;          /* STA scratch area */
 153         unsigned long i;
 154
 155         /* see if it is ready for 1000 nsec */
 156         i = 0;
 157
 158         while ((in32 (EMAC_STACR) & EMAC_STACR_OC) == 0) {
 159                 if (i > 5)
 160                         return -1;
 161                 udelay (7);
 162                 i++;
 163         }
 164         sta_reg = 0;
 165         sta_reg = reg;                          /* reg address */
 166         /* set clock (50Mhz) and read flags */
 167         sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
 168 #ifdef CONFIG_PHY_CLK_FREQ
 169         sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
 170 #endif
 171         sta_reg = sta_reg | ((unsigned long) addr << 5);        /* Phy address */
 172         memcpy (&sta_reg, &value, 2);   /* put in data */
 173
 174         out32 (EMAC_STACR, sta_reg);
 175
 176         /* wait for completion */
 177         i = 0;
 178         sta_reg = in32 (EMAC_STACR);
 179         while ((sta_reg & EMAC_STACR_OC) == 0) {
 180                 udelay (7);
 181                 if (i > 5)
 182                         return -1;
 183                 i++;
 184                 sta_reg = in32 (EMAC_STACR);
 185         }
 186
 187         if ((sta_reg & EMAC_STACR_PHYE) != 0)
 188                 return -1;
 189         return 0;
 190
 191 } /* phy_read */
 192
 193 #endif  /* CONFIG_405GP */