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* Patch by Leif Lindholm, 23 Sep 2004:
[people/ms/u-boot.git] / cpu / ppc4xx / serial.c
1 /*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23 /*------------------------------------------------------------------------------+ */
24 /*
25 * This source code has been made available to you by IBM on an AS-IS
26 * basis. Anyone receiving this source is licensed under IBM
27 * copyrights to use it in any way he or she deems fit, including
28 * copying it, modifying it, compiling it, and redistributing it either
29 * with or without modifications. No license under IBM patents or
30 * patent applications is to be implied by the copyright license.
31 *
32 * Any user of this software should understand that IBM cannot provide
33 * technical support for this software and will not be responsible for
34 * any consequences resulting from the use of this software.
35 *
36 * Any person who transfers this source code or any derivative work
37 * must include the IBM copyright notice, this paragraph, and the
38 * preceding two paragraphs in the transferred software.
39 *
40 * COPYRIGHT I B M CORPORATION 1995
41 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
42 */
43 /*------------------------------------------------------------------------------- */
44 /*
45 * Travis Sawyer 15 September 2004
46 * Added CONFIG_SERIAL_MULTI support
47 */
48 #include <common.h>
49 #include <commproc.h>
50 #include <asm/processor.h>
51 #include <watchdog.h>
52 #include "vecnum.h"
53
54 #ifdef CONFIG_SERIAL_MULTI
55 #include <serial.h>
56 #endif
57
58 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
59 #include <malloc.h>
60 #endif
61
62 /*****************************************************************************/
63 #ifdef CONFIG_IOP480
64
65 #define SPU_BASE 0x40000000
66
67 #define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
68 #define spu_LineStat_w 0x04 /* Line Status Register (Set) */
69 #define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
70 #define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
71 #define spu_BRateDivh 0x10 /* Baud rate divisor high */
72 #define spu_BRateDivl 0x14 /* Baud rate divisor low */
73 #define spu_CtlReg 0x18 /* Control Register */
74 #define spu_RxCmd 0x1c /* Rx Command Register */
75 #define spu_TxCmd 0x20 /* Tx Command Register */
76 #define spu_RxBuff 0x24 /* Rx data buffer */
77 #define spu_TxBuff 0x24 /* Tx data buffer */
78
79 /*-----------------------------------------------------------------------------+
80 | Line Status Register.
81 +-----------------------------------------------------------------------------*/
82 #define asyncLSRport1 0x40000000
83 #define asyncLSRport1set 0x40000004
84 #define asyncLSRDataReady 0x80
85 #define asyncLSRFramingError 0x40
86 #define asyncLSROverrunError 0x20
87 #define asyncLSRParityError 0x10
88 #define asyncLSRBreakInterrupt 0x08
89 #define asyncLSRTxHoldEmpty 0x04
90 #define asyncLSRTxShiftEmpty 0x02
91
92 /*-----------------------------------------------------------------------------+
93 | Handshake Status Register.
94 +-----------------------------------------------------------------------------*/
95 #define asyncHSRport1 0x40000008
96 #define asyncHSRport1set 0x4000000c
97 #define asyncHSRDsr 0x80
98 #define asyncLSRCts 0x40
99
100 /*-----------------------------------------------------------------------------+
101 | Control Register.
102 +-----------------------------------------------------------------------------*/
103 #define asyncCRport1 0x40000018
104 #define asyncCRNormal 0x00
105 #define asyncCRLoopback 0x40
106 #define asyncCRAutoEcho 0x80
107 #define asyncCRDtr 0x20
108 #define asyncCRRts 0x10
109 #define asyncCRWordLength7 0x00
110 #define asyncCRWordLength8 0x08
111 #define asyncCRParityDisable 0x00
112 #define asyncCRParityEnable 0x04
113 #define asyncCREvenParity 0x00
114 #define asyncCROddParity 0x02
115 #define asyncCRStopBitsOne 0x00
116 #define asyncCRStopBitsTwo 0x01
117 #define asyncCRDisableDtrRts 0x00
118
119 /*-----------------------------------------------------------------------------+
120 | Receiver Command Register.
121 +-----------------------------------------------------------------------------*/
122 #define asyncRCRport1 0x4000001c
123 #define asyncRCRDisable 0x00
124 #define asyncRCREnable 0x80
125 #define asyncRCRIntDisable 0x00
126 #define asyncRCRIntEnabled 0x20
127 #define asyncRCRDMACh2 0x40
128 #define asyncRCRDMACh3 0x60
129 #define asyncRCRErrorInt 0x10
130 #define asyncRCRPauseEnable 0x08
131
132 /*-----------------------------------------------------------------------------+
133 | Transmitter Command Register.
134 +-----------------------------------------------------------------------------*/
135 #define asyncTCRport1 0x40000020
136 #define asyncTCRDisable 0x00
137 #define asyncTCREnable 0x80
138 #define asyncTCRIntDisable 0x00
139 #define asyncTCRIntEnabled 0x20
140 #define asyncTCRDMACh2 0x40
141 #define asyncTCRDMACh3 0x60
142 #define asyncTCRTxEmpty 0x10
143 #define asyncTCRErrorInt 0x08
144 #define asyncTCRStopPause 0x04
145 #define asyncTCRBreakGen 0x02
146
147 /*-----------------------------------------------------------------------------+
148 | Miscellanies defines.
149 +-----------------------------------------------------------------------------*/
150 #define asyncTxBufferport1 0x40000024
151 #define asyncRxBufferport1 0x40000024
152 #define asyncDLABLsbport1 0x40000014
153 #define asyncDLABMsbport1 0x40000010
154 #define asyncXOFFchar 0x13
155 #define asyncXONchar 0x11
156
157 /*
158 * Minimal serial functions needed to use one of the SMC ports
159 * as serial console interface.
160 */
161
162 int serial_init (void)
163 {
164 DECLARE_GLOBAL_DATA_PTR;
165
166 volatile char val;
167 unsigned short br_reg;
168
169 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
170
171 /*
172 * Init onboard UART
173 */
174 out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
175 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
176 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
177 out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
178 out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
179 out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
180 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
181 val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
182
183 return (0);
184 }
185
186 void serial_setbrg (void)
187 {
188 DECLARE_GLOBAL_DATA_PTR;
189
190 unsigned short br_reg;
191
192 br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
193
194 out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
195 out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
196 }
197
198 void serial_putc (const char c)
199 {
200 if (c == '\n')
201 serial_putc ('\r');
202
203 /* load status from handshake register */
204 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
205 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
206
207 out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
208
209 while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
210 if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
211 out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
212 }
213 }
214
215 void serial_puts (const char *s)
216 {
217 while (*s) {
218 serial_putc (*s++);
219 }
220 }
221
222 int serial_getc ()
223 {
224 unsigned char status = 0;
225
226 while (1) {
227 status = in8 (asyncLSRport1);
228 if ((status & asyncLSRDataReady) != 0x0) {
229 break;
230 }
231 if ((status & ( asyncLSRFramingError |
232 asyncLSROverrunError |
233 asyncLSRParityError |
234 asyncLSRBreakInterrupt )) != 0) {
235 (void) out8 (asyncLSRport1,
236 asyncLSRFramingError |
237 asyncLSROverrunError |
238 asyncLSRParityError |
239 asyncLSRBreakInterrupt );
240 }
241 }
242 return (0x000000ff & (int) in8 (asyncRxBufferport1));
243 }
244
245 int serial_tstc ()
246 {
247 unsigned char status;
248
249 status = in8 (asyncLSRport1);
250 if ((status & asyncLSRDataReady) != 0x0) {
251 return (1);
252 }
253 if ((status & ( asyncLSRFramingError |
254 asyncLSROverrunError |
255 asyncLSRParityError |
256 asyncLSRBreakInterrupt )) != 0) {
257 (void) out8 (asyncLSRport1,
258 asyncLSRFramingError |
259 asyncLSROverrunError |
260 asyncLSRParityError |
261 asyncLSRBreakInterrupt);
262 }
263 return 0;
264 }
265
266 #endif /* CONFIG_IOP480 */
267
268 /*****************************************************************************/
269 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
270
271 #if defined(CONFIG_440)
272 #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
273 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
274 #if defined(CONFIG_440_GX)
275 #define CR0_MASK 0xdfffffff
276 #define CR0_EXTCLK_ENA 0x00800000
277 #define CR0_UDIV_POS 0
278 #else
279 #define CR0_MASK 0x3fff0000
280 #define CR0_EXTCLK_ENA 0x00600000
281 #define CR0_UDIV_POS 16
282 #endif /* CONFIG_440_GX */
283 #elif defined(CONFIG_405EP)
284 #define UART0_BASE 0xef600300
285 #define UART1_BASE 0xef600400
286 #define UCR0_MASK 0x0000007f
287 #define UCR1_MASK 0x00007f00
288 #define UCR0_UDIV_POS 0
289 #define UCR1_UDIV_POS 8
290 #define UDIV_MAX 127
291 #else /* CONFIG_405GP || CONFIG_405CR */
292 #define UART0_BASE 0xef600300
293 #define UART1_BASE 0xef600400
294 #define CR0_MASK 0x00001fff
295 #define CR0_EXTCLK_ENA 0x000000c0
296 #define CR0_UDIV_POS 1
297 #define UDIV_MAX 32
298 #endif
299
300 /* using serial port 0 or 1 as U-Boot console ? */
301 #if defined(CONFIG_UART1_CONSOLE)
302 #define ACTING_UART0_BASE UART1_BASE
303 #define ACTING_UART1_BASE UART0_BASE
304 #if defined(CONFIG_440_GX)
305 #define UART0_SDR sdr_uart1
306 #define UART1_SDR sdr_uart0
307 #endif /* CONFIG_440_GX */
308 #else
309 #define ACTING_UART0_BASE UART0_BASE
310 #define ACTING_UART1_BASE UART1_BASE
311 #if defined(CONFIG_440_GX)
312 #define UART0_SDR sdr_uart0
313 #define UART1_SDR sdr_uart1
314 #endif /* CONFIG_440_GX */
315 #endif
316
317 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
318 #error "External serial clock not supported on IBM PPC405EP!"
319 #endif
320
321 #define UART_RBR 0x00
322 #define UART_THR 0x00
323 #define UART_IER 0x01
324 #define UART_IIR 0x02
325 #define UART_FCR 0x02
326 #define UART_LCR 0x03
327 #define UART_MCR 0x04
328 #define UART_LSR 0x05
329 #define UART_MSR 0x06
330 #define UART_SCR 0x07
331 #define UART_DLL 0x00
332 #define UART_DLM 0x01
333
334 /*-----------------------------------------------------------------------------+
335 | Line Status Register.
336 +-----------------------------------------------------------------------------*/
337 /*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
338 #define asyncLSRDataReady1 0x01
339 #define asyncLSROverrunError1 0x02
340 #define asyncLSRParityError1 0x04
341 #define asyncLSRFramingError1 0x08
342 #define asyncLSRBreakInterrupt1 0x10
343 #define asyncLSRTxHoldEmpty1 0x20
344 #define asyncLSRTxShiftEmpty1 0x40
345 #define asyncLSRRxFifoError1 0x80
346
347 /*-----------------------------------------------------------------------------+
348 | Miscellanies defines.
349 +-----------------------------------------------------------------------------*/
350 /*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
351 /*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
352
353 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
354 /*-----------------------------------------------------------------------------+
355 | Fifo
356 +-----------------------------------------------------------------------------*/
357 typedef struct {
358 char *rx_buffer;
359 ulong rx_put;
360 ulong rx_get;
361 } serial_buffer_t;
362
363 volatile static serial_buffer_t buf_info;
364 #endif
365
366 #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
367 static void serial_divs (int baudrate, unsigned long *pudiv,
368 unsigned short *pbdiv )
369 {
370 sys_info_t sysinfo;
371 unsigned long div; /* total divisor udiv * bdiv */
372 unsigned long umin; /* minimum udiv */
373 unsigned short diff; /* smallest diff */
374 unsigned long udiv; /* best udiv */
375
376 unsigned short idiff; /* current diff */
377 unsigned short ibdiv; /* current bdiv */
378 unsigned long i;
379 unsigned long est; /* current estimate */
380
381 get_sys_info( &sysinfo );
382
383 udiv = 32; /* Assume lowest possible serial clk */
384 div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
385 umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
386 diff = 32; /* highest possible */
387
388 /* i is the test udiv value -- start with the largest
389 * possible (32) to minimize serial clock and constrain
390 * search to umin.
391 */
392 for( i = 32; i > umin; i-- ){
393 ibdiv = div/i;
394 est = i * ibdiv;
395 idiff = (est > div) ? (est-div) : (div-est);
396 if( idiff == 0 ){
397 udiv = i;
398 break; /* can't do better */
399 }
400 else if( idiff < diff ){
401 udiv = i; /* best so far */
402 diff = idiff; /* update lowest diff*/
403 }
404 }
405
406 *pudiv = udiv;
407 *pbdiv = div/udiv;
408
409 }
410 #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
411
412 /*
413 * Minimal serial functions needed to use one of the SMC ports
414 * as serial console interface.
415 */
416
417 #if defined(CONFIG_440)
418 #if defined(CONFIG_SERIAL_MULTI)
419 int serial_init_dev (unsigned long dev_base)
420 #else
421 int serial_init(void)
422 #endif
423 {
424 DECLARE_GLOBAL_DATA_PTR;
425
426 unsigned long reg;
427 unsigned long udiv;
428 unsigned short bdiv;
429 volatile char val;
430 #ifdef CFG_EXT_SERIAL_CLOCK
431 unsigned long tmp;
432 #endif
433
434 #if defined(CONFIG_440_GX)
435 #if defined(CONFIG_SERIAL_MULTI)
436 if (UART0_BASE == dev_base) {
437 mfsdr(UART0_SDR,reg);
438 reg &= ~CR0_MASK;
439 } else {
440 mfsdr(UART1_SDR,reg);
441 reg &= ~CR0_MASK;
442 }
443 #else
444 mfsdr(UART0_SDR,reg);
445 reg &= ~CR0_MASK;
446 #endif
447 #else
448 reg = mfdcr(cntrl0) & ~CR0_MASK;
449 #endif /* CONFIG_440_GX */
450 #ifdef CFG_EXT_SERIAL_CLOCK
451 reg |= CR0_EXTCLK_ENA;
452 udiv = 1;
453 tmp = gd->baudrate * 16;
454 bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
455 #else
456 /* For 440, the cpu clock is on divider chain A, UART on divider
457 * chain B ... so cpu clock is irrelevant. Get the "optimized"
458 * values that are subject to the 1/2 opb clock constraint
459 */
460 serial_divs (gd->baudrate, &udiv, &bdiv);
461 #endif
462
463 #if defined(CONFIG_440_GX)
464 reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
465 #if defined(CONFIG_SERIAL_MULTI)
466 if (UART0_BASE == dev_base) {
467 mtsdr (UART0_SDR,reg);
468 } else {
469 mtsdr (UART1_SDR,reg);
470 }
471 #else
472 mtsdr (UART0_SDR,reg);
473 #endif
474 #else
475 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
476 mtdcr (cntrl0, reg);
477 #endif
478
479 #if defined(CONFIG_SERIAL_MULTI)
480 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
481 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
482 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
483 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
484 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
485 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
486 val = in8 (dev_base + UART_LSR); /* clear line status */
487 val = in8 (dev_base + UART_RBR); /* read receive buffer */
488 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
489 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
490 #else
491 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
492 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
493 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
494 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
495 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
496 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
497 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
498 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
499 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
500 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
501 #endif
502 return (0);
503 }
504
505 #else /* !defined(CONFIG_440) */
506
507 #if defined(CONFIG_SERIAL_MULTI)
508 int serial_init_dev (unsigned long dev_base)
509 #else
510 int serial_init (void)
511 #endif
512 {
513 DECLARE_GLOBAL_DATA_PTR;
514
515 unsigned long reg;
516 unsigned long tmp;
517 unsigned long clk;
518 unsigned long udiv;
519 unsigned short bdiv;
520 volatile char val;
521
522 #ifdef CONFIG_405EP
523 reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
524 clk = gd->cpu_clk;
525 tmp = CFG_BASE_BAUD * 16;
526 udiv = (clk + tmp / 2) / tmp;
527 if (udiv > UDIV_MAX) /* max. n bits for udiv */
528 udiv = UDIV_MAX;
529 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
530 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
531 mtdcr (cpc0_ucr, reg);
532 #else /* CONFIG_405EP */
533 reg = mfdcr(cntrl0) & ~CR0_MASK;
534 #ifdef CFG_EXT_SERIAL_CLOCK
535 clk = CFG_EXT_SERIAL_CLOCK;
536 udiv = 1;
537 reg |= CR0_EXTCLK_ENA;
538 #else
539 clk = gd->cpu_clk;
540 #ifdef CFG_405_UART_ERRATA_59
541 udiv = 31; /* Errata 59: stuck at 31 */
542 #else
543 tmp = CFG_BASE_BAUD * 16;
544 udiv = (clk + tmp / 2) / tmp;
545 if (udiv > UDIV_MAX) /* max. n bits for udiv */
546 udiv = UDIV_MAX;
547 #endif
548 #endif
549 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
550 mtdcr (cntrl0, reg);
551 #endif /* CONFIG_405EP */
552
553 tmp = gd->baudrate * udiv * 16;
554 bdiv = (clk + tmp / 2) / tmp;
555
556 #if defined(CONFIG_SERIAL_MULTI)
557 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
558 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
559 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
560 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
561 out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
562 out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
563 val = in8 (dev_base + UART_LSR); /* clear line status */
564 val = in8 (dev_base + UART_RBR); /* read receive buffer */
565 out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
566 out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
567 #else
568 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
569 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
570 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
571 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
572 out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
573 out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
574 val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
575 val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
576 out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
577 out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
578 #endif
579 return (0);
580 }
581
582 #endif /* if defined(CONFIG_440) */
583
584 #if defined(CONFIG_SERIAL_MULTI)
585 void serial_setbrg_dev (unsigned long dev_base)
586 #else
587 void serial_setbrg (void)
588 #endif
589 {
590 DECLARE_GLOBAL_DATA_PTR;
591
592 unsigned long tmp;
593 unsigned long clk;
594 unsigned long udiv;
595 unsigned short bdiv;
596
597 #ifdef CFG_EXT_SERIAL_CLOCK
598 clk = CFG_EXT_SERIAL_CLOCK;
599 #else
600 clk = gd->cpu_clk;
601 #endif
602
603 #ifdef CONFIG_405EP
604 udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
605 #else
606 udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
607 #endif /* CONFIG_405EP */
608 tmp = gd->baudrate * udiv * 16;
609 bdiv = (clk + tmp / 2) / tmp;
610
611 #if defined(CONFIG_SERIAL_MULTI)
612 out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
613 out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
614 out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
615 out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
616 #else
617 out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
618 out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
619 out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
620 out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
621 #endif
622 }
623
624 #if defined(CONFIG_SERIAL_MULTI)
625 void serial_putc_dev (unsigned long dev_base, const char c)
626 #else
627 void serial_putc (const char c)
628 #endif
629 {
630 int i;
631
632 if (c == '\n')
633 #if defined(CONFIG_SERIAL_MULTI)
634 serial_putc_dev (dev_base, '\r');
635 #else
636 serial_putc ('\r');
637 #endif
638
639 /* check THRE bit, wait for transmiter available */
640 for (i = 1; i < 3500; i++) {
641 #if defined(CONFIG_SERIAL_MULTI)
642 if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
643 #else
644 if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
645 #endif
646 break;
647 udelay (100);
648 }
649 #if defined(CONFIG_SERIAL_MULTI)
650 out8 (dev_base + UART_THR, c); /* put character out */
651 #else
652 out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
653 #endif
654 }
655
656 #if defined(CONFIG_SERIAL_MULTI)
657 void serial_puts_dev (unsigned long dev_base, const char *s)
658 #else
659 void serial_puts (const char *s)
660 #endif
661 {
662 while (*s) {
663 #if defined(CONFIG_SERIAL_MULTI)
664 serial_putc_dev (dev_base, *s++);
665 #else
666 serial_putc (*s++);
667 #endif
668 }
669 }
670
671 #if defined(CONFIG_SERIAL_MULTI)
672 int serial_getc_dev (unsigned long dev_base)
673 #else
674 int serial_getc (void)
675 #endif
676 {
677 unsigned char status = 0;
678
679 while (1) {
680 #if defined(CONFIG_HW_WATCHDOG)
681 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
682 #endif /* CONFIG_HW_WATCHDOG */
683 #if defined(CONFIG_SERIAL_MULTI)
684 status = in8 (dev_base + UART_LSR);
685 #else
686 status = in8 (ACTING_UART0_BASE + UART_LSR);
687 #endif
688 if ((status & asyncLSRDataReady1) != 0x0) {
689 break;
690 }
691 if ((status & ( asyncLSRFramingError1 |
692 asyncLSROverrunError1 |
693 asyncLSRParityError1 |
694 asyncLSRBreakInterrupt1 )) != 0) {
695 #if defined(CONFIG_SERIAL_MULTI)
696 out8 (dev_base + UART_LSR,
697 #else
698 out8 (ACTING_UART0_BASE + UART_LSR,
699 #endif
700 asyncLSRFramingError1 |
701 asyncLSROverrunError1 |
702 asyncLSRParityError1 |
703 asyncLSRBreakInterrupt1);
704 }
705 }
706 #if defined(CONFIG_SERIAL_MULTI)
707 return (0x000000ff & (int) in8 (dev_base));
708 #else
709 return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
710 #endif
711 }
712
713 #if defined(CONFIG_SERIAL_MULTI)
714 int serial_tstc_dev (unsigned long dev_base)
715 #else
716 int serial_tstc (void)
717 #endif
718 {
719 unsigned char status;
720
721 #if defined(CONFIG_SERIAL_MULTI)
722 status = in8 (dev_base + UART_LSR);
723 #else
724 status = in8 (ACTING_UART0_BASE + UART_LSR);
725 #endif
726 if ((status & asyncLSRDataReady1) != 0x0) {
727 return (1);
728 }
729 if ((status & ( asyncLSRFramingError1 |
730 asyncLSROverrunError1 |
731 asyncLSRParityError1 |
732 asyncLSRBreakInterrupt1 )) != 0) {
733 #if defined(CONFIG_SERIAL_MULTI)
734 out8 (dev_base + UART_LSR,
735 #else
736 out8 (ACTING_UART0_BASE + UART_LSR,
737 #endif
738 asyncLSRFramingError1 |
739 asyncLSROverrunError1 |
740 asyncLSRParityError1 |
741 asyncLSRBreakInterrupt1);
742 }
743 return 0;
744 }
745
746 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
747
748 void serial_isr (void *arg)
749 {
750 int space;
751 int c;
752 const int rx_get = buf_info.rx_get;
753 int rx_put = buf_info.rx_put;
754
755 if (rx_get <= rx_put) {
756 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
757 } else {
758 space = rx_get - rx_put;
759 }
760 while (serial_tstc_dev (ACTING_UART0_BASE)) {
761 c = serial_getc_dev (ACTING_UART0_BASE);
762 if (space) {
763 buf_info.rx_buffer[rx_put++] = c;
764 space--;
765 }
766 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
767 rx_put = 0;
768 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
769 /* Stop flow by setting RTS inactive */
770 out8 (ACTING_UART0_BASE + UART_MCR,
771 in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
772 }
773 }
774 buf_info.rx_put = rx_put;
775 }
776
777 void serial_buffered_init (void)
778 {
779 serial_puts ("Switching to interrupt driven serial input mode.\n");
780 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
781 buf_info.rx_put = 0;
782 buf_info.rx_get = 0;
783
784 if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
785 serial_puts ("Check CTS signal present on serial port: OK.\n");
786 } else {
787 serial_puts ("WARNING: CTS signal not present on serial port.\n");
788 }
789
790 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
791 serial_isr /*interrupt_handler_t *handler */ ,
792 (void *) &buf_info /*void *arg */ );
793
794 /* Enable "RX Data Available" Interrupt on UART */
795 /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
796 out8 (ACTING_UART0_BASE + UART_IER, 0x01);
797 /* Set DTR active */
798 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
799 /* Start flow by setting RTS active */
800 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
801 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
802 out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
803 }
804
805 void serial_buffered_putc (const char c)
806 {
807 /* Wait for CTS */
808 #if defined(CONFIG_HW_WATCHDOG)
809 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
810 WATCHDOG_RESET ();
811 #else
812 while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
813 #endif
814 serial_putc (c);
815 }
816
817 void serial_buffered_puts (const char *s)
818 {
819 serial_puts (s);
820 }
821
822 int serial_buffered_getc (void)
823 {
824 int space;
825 int c;
826 int rx_get = buf_info.rx_get;
827 int rx_put;
828
829 #if defined(CONFIG_HW_WATCHDOG)
830 while (rx_get == buf_info.rx_put)
831 WATCHDOG_RESET ();
832 #else
833 while (rx_get == buf_info.rx_put);
834 #endif
835 c = buf_info.rx_buffer[rx_get++];
836 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
837 rx_get = 0;
838 buf_info.rx_get = rx_get;
839
840 rx_put = buf_info.rx_put;
841 if (rx_get <= rx_put) {
842 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
843 } else {
844 space = rx_get - rx_put;
845 }
846 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
847 /* Start flow by setting RTS active */
848 out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
849 }
850
851 return c;
852 }
853
854 int serial_buffered_tstc (void)
855 {
856 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
857 }
858
859 #endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
860
861 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
862 /*
863 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
864 number 0 or number 1
865 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
866 configuration has been already done
867 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
868 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
869 */
870 #if (CONFIG_KGDB_SER_INDEX & 2)
871 void kgdb_serial_init (void)
872 {
873 DECLARE_GLOBAL_DATA_PTR;
874
875 volatile char val;
876 unsigned short br_reg;
877
878 get_clocks ();
879 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
880 5) / 10;
881 /*
882 * Init onboard 16550 UART
883 */
884 out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
885 out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
886 out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
887 out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
888 out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
889 out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
890 val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
891 val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
892 out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
893 out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
894 }
895
896 void putDebugChar (const char c)
897 {
898 if (c == '\n')
899 serial_putc ('\r');
900
901 out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
902
903 /* check THRE bit, wait for transfer done */
904 while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
905 }
906
907 void putDebugStr (const char *s)
908 {
909 while (*s) {
910 serial_putc (*s++);
911 }
912 }
913
914 int getDebugChar (void)
915 {
916 unsigned char status = 0;
917
918 while (1) {
919 status = in8 (ACTING_UART1_BASE + UART_LSR);
920 if ((status & asyncLSRDataReady1) != 0x0) {
921 break;
922 }
923 if ((status & ( asyncLSRFramingError1 |
924 asyncLSROverrunError1 |
925 asyncLSRParityError1 |
926 asyncLSRBreakInterrupt1 )) != 0) {
927 out8 (ACTING_UART1_BASE + UART_LSR,
928 asyncLSRFramingError1 |
929 asyncLSROverrunError1 |
930 asyncLSRParityError1 |
931 asyncLSRBreakInterrupt1);
932 }
933 }
934 return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
935 }
936
937 void kgdb_interruptible (int yes)
938 {
939 return;
940 }
941
942 #else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
943
944 void kgdb_serial_init (void)
945 {
946 serial_printf ("[on serial] ");
947 }
948
949 void putDebugChar (int c)
950 {
951 serial_putc (c);
952 }
953
954 void putDebugStr (const char *str)
955 {
956 serial_puts (str);
957 }
958
959 int getDebugChar (void)
960 {
961 return serial_getc ();
962 }
963
964 void kgdb_interruptible (int yes)
965 {
966 return;
967 }
968 #endif /* (CONFIG_KGDB_SER_INDEX & 2) */
969 #endif /* CFG_CMD_KGDB */
970
971
972 #if defined(CONFIG_SERIAL_MULTI)
973 int serial0_init(void)
974 {
975 return (serial_init_dev(UART0_BASE));
976 }
977
978 int serial1_init(void)
979 {
980 return (serial_init_dev(UART1_BASE));
981 }
982 void serial0_setbrg (void)
983 {
984 serial_setbrg_dev(UART0_BASE);
985 }
986 void serial1_setbrg (void)
987 {
988 serial_setbrg_dev(UART1_BASE);
989 }
990
991 void serial0_putc(const char c)
992 {
993 serial_putc_dev(UART0_BASE,c);
994 }
995
996 void serial1_putc(const char c)
997 {
998 serial_putc_dev(UART1_BASE, c);
999 }
1000 void serial0_puts(const char *s)
1001 {
1002 serial_puts_dev(UART0_BASE, s);
1003 }
1004
1005 void serial1_puts(const char *s)
1006 {
1007 serial_puts_dev(UART1_BASE, s);
1008 }
1009
1010 int serial0_getc(void)
1011 {
1012 return(serial_getc_dev(UART0_BASE));
1013 }
1014
1015 int serial1_getc(void)
1016 {
1017 return(serial_getc_dev(UART1_BASE));
1018 }
1019 int serial0_tstc(void)
1020 {
1021 return (serial_tstc_dev(UART0_BASE));
1022 }
1023
1024 int serial1_tstc(void)
1025 {
1026 return (serial_tstc_dev(UART1_BASE));
1027 }
1028
1029 struct serial_device serial0_device =
1030 {
1031 "serial0",
1032 "UART0",
1033 serial0_init,
1034 serial0_setbrg,
1035 serial0_getc,
1036 serial0_tstc,
1037 serial0_putc,
1038 serial0_puts,
1039 };
1040
1041 struct serial_device serial1_device =
1042 {
1043 "serial1",
1044 "UART1",
1045 serial1_init,
1046 serial1_setbrg,
1047 serial1_getc,
1048 serial1_tstc,
1049 serial1_putc,
1050 serial1_puts,
1051 };
1052 #endif /* CONFIG_SERIAL_MULTI */
1053
1054 #endif /* CONFIG_405GP || CONFIG_405CR */
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