cpu/ppc4xx/start.S

   1 /*
   2  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24 /*------------------------------------------------------------------------------+ */
  25 /* */
  26 /*       This source code has been made available to you by IBM on an AS-IS */
  27 /*       basis.  Anyone receiving this source is licensed under IBM */
  28 /*       copyrights to use it in any way he or she deems fit, including */
  29 /*       copying it, modifying it, compiling it, and redistributing it either */
  30 /*       with or without modifications.  No license under IBM patents or */
  31 /*       patent applications is to be implied by the copyright license. */
  32 /* */
  33 /*       Any user of this software should understand that IBM cannot provide */
  34 /*       technical support for this software and will not be responsible for */
  35 /*       any consequences resulting from the use of this software. */
  36 /* */
  37 /*       Any person who transfers this source code or any derivative work */
  38 /*       must include the IBM copyright notice, this paragraph, and the */
  39 /*       preceding two paragraphs in the transferred software. */
  40 /* */
  41 /*       COPYRIGHT   I B M   CORPORATION 1995 */
  42 /*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
  43 /*------------------------------------------------------------------------------- */
  44
  45 /*  U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
  46  *
  47  *
  48  *  The processor starts at 0xfffffffc and the code is executed
  49  *  from flash/rom.
  50  *  in memory, but as long we don't jump around before relocating.
  51  *  board_init lies at a quite high address and when the cpu has
  52  *  jumped there, everything is ok.
  53  *  This works because the cpu gives the FLASH (CS0) the whole
  54  *  address space at startup, and board_init lies as a echo of
  55  *  the flash somewhere up there in the memorymap.
  56  *
  57  *  board_init will change CS0 to be positioned at the correct
  58  *  address and (s)dram will be positioned at address 0
  59  */
  60 #include <config.h>
  61 #include <mpc8xx.h>
  62 #include <ppc4xx.h>
  63 #include <version.h>
  64
  65 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  66
  67 #include <ppc_asm.tmpl>
  68 #include <ppc_defs.h>
  69
  70 #include <asm/cache.h>
  71 #include <asm/mmu.h>
  72
  73 #ifndef  CONFIG_IDENT_STRING
  74 #define  CONFIG_IDENT_STRING ""
  75 #endif
  76
  77 #ifdef CFG_INIT_DCACHE_CS
  78 # if (CFG_INIT_DCACHE_CS == 0)
  79 #  define PBxAP pb0ap
  80 #  define PBxCR pb0cr
  81 # endif
  82 # if (CFG_INIT_DCACHE_CS == 1)
  83 #  define PBxAP pb1ap
  84 #  define PBxCR pb1cr
  85 # endif
  86 # if (CFG_INIT_DCACHE_CS == 2)
  87 #  define PBxAP pb2ap
  88 #  define PBxCR pb2cr
  89 # endif
  90 # if (CFG_INIT_DCACHE_CS == 3)
  91 #  define PBxAP pb3ap
  92 #  define PBxCR pb3cr
  93 # endif
  94 # if (CFG_INIT_DCACHE_CS == 4)
  95 #  define PBxAP pb4ap
  96 #  define PBxCR pb4cr
  97 # endif
  98 # if (CFG_INIT_DCACHE_CS == 5)
  99 #  define PBxAP pb5ap
 100 #  define PBxCR pb5cr
 101 # endif
 102 # if (CFG_INIT_DCACHE_CS == 6)
 103 #  define PBxAP pb6ap
 104 #  define PBxCR pb6cr
 105 # endif
 106 # if (CFG_INIT_DCACHE_CS == 7)
 107 #  define PBxAP pb7ap
 108 #  define PBxCR pb7cr
 109 # endif
 110 #endif /* CFG_INIT_DCACHE_CS */
 111
 112 /* We don't want the  MMU yet.
 113 */
 114 #undef  MSR_KERNEL
 115 #define MSR_KERNEL ( MSR_ME  )  /* Machine Check */
 116
 117
 118         .extern ext_bus_cntlr_init
 119         .extern sdram_init
 120 #ifdef CONFIG_NAND_U_BOOT
 121         .extern reconfig_tlb0
 122 #endif
 123
 124 /*
 125  * Set up GOT: Global Offset Table
 126  *
 127  * Use r14 to access the GOT
 128  */
 129 #if !defined(CONFIG_NAND_SPL)
 130         START_GOT
 131         GOT_ENTRY(_GOT2_TABLE_)
 132         GOT_ENTRY(_FIXUP_TABLE_)
 133
 134         GOT_ENTRY(_start)
 135         GOT_ENTRY(_start_of_vectors)
 136         GOT_ENTRY(_end_of_vectors)
 137         GOT_ENTRY(transfer_to_handler)
 138
 139         GOT_ENTRY(__init_end)
 140         GOT_ENTRY(_end)
 141         GOT_ENTRY(__bss_start)
 142         END_GOT
 143 #endif /* CONFIG_NAND_SPL */
 144
 145 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 146         /*
 147          * NAND U-Boot image is started from offset 0
 148          */
 149         .text
 150         bl      reconfig_tlb0
 151         GET_GOT
 152         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 153         bl      board_init_f
 154 #endif
 155
 156 /*
 157  * 440 Startup -- on reset only the top 4k of the effective
 158  * address space is mapped in by an entry in the instruction
 159  * and data shadow TLB. The .bootpg section is located in the
 160  * top 4k & does only what's necessary to map in the the rest
 161  * of the boot rom. Once the boot rom is mapped in we can
 162  * proceed with normal startup.
 163  *
 164  * NOTE: CS0 only covers the top 2MB of the effective address
 165  * space after reset.
 166  */
 167
 168 #if defined(CONFIG_440)
 169 #if !defined(CONFIG_NAND_SPL)
 170     .section .bootpg,"ax"
 171 #endif
 172     .globl _start_440
 173
 174 /**************************************************************************/
 175 _start_440:
 176         /*--------------------------------------------------------------------+
 177         | 440EPX BUP Change - Hardware team request
 178         +--------------------------------------------------------------------*/
 179 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 180         sync
 181         nop
 182         nop
 183 #endif
 184         /*----------------------------------------------------------------+
 185         | Core bug fix.  Clear the esr
 186         +-----------------------------------------------------------------*/
 187         li      r0,0
 188         mtspr   esr,r0
 189         /*----------------------------------------------------------------*/
 190         /* Clear and set up some registers. */
 191         /*----------------------------------------------------------------*/
 192         iccci   r0,r0           /* NOTE: operands not used for 440 */
 193         dccci   r0,r0           /* NOTE: operands not used for 440 */
 194         sync
 195         li      r0,0
 196         mtspr   srr0,r0
 197         mtspr   srr1,r0
 198         mtspr   csrr0,r0
 199         mtspr   csrr1,r0
 200         /* NOTE: 440GX adds machine check status regs */
 201 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
 202         mtspr   mcsrr0,r0
 203         mtspr   mcsrr1,r0
 204         mfspr   r1,mcsr
 205         mtspr   mcsr,r1
 206 #endif
 207
 208         /*----------------------------------------------------------------*/
 209         /* CCR0 init */
 210         /*----------------------------------------------------------------*/
 211         /* Disable store gathering & broadcast, guarantee inst/data
 212         * cache block touch, force load/store alignment
 213         * (see errata 1.12: 440_33)
 214         */
 215         lis     r1,0x0030       /* store gathering & broadcast disable */
 216         ori     r1,r1,0x6000    /* cache touch */
 217         mtspr   ccr0,r1
 218
 219         /*----------------------------------------------------------------*/
 220         /* Initialize debug */
 221         /*----------------------------------------------------------------*/
 222         mfspr   r1,dbcr0
 223         andis.  r1, r1, 0x8000  /* test DBCR0[EDM] bit                  */
 224         bne     skip_debug_init /* if set, don't clear debug register   */
 225         mtspr   dbcr0,r0
 226         mtspr   dbcr1,r0
 227         mtspr   dbcr2,r0
 228         mtspr   iac1,r0
 229         mtspr   iac2,r0
 230         mtspr   iac3,r0
 231         mtspr   dac1,r0
 232         mtspr   dac2,r0
 233         mtspr   dvc1,r0
 234         mtspr   dvc2,r0
 235
 236         mfspr   r1,dbsr
 237         mtspr   dbsr,r1         /* Clear all valid bits */
 238 skip_debug_init:
 239
 240 #if defined (CONFIG_440SPE)
 241         /*----------------------------------------------------------------+
 242         | Initialize Core Configuration Reg1.
 243         | a. ICDPEI: Record even parity. Normal operation.
 244         | b. ICTPEI: Record even parity. Normal operation.
 245         | c. DCTPEI: Record even parity. Normal operation.
 246         | d. DCDPEI: Record even parity. Normal operation.
 247         | e. DCUPEI: Record even parity. Normal operation.
 248         | f. DCMPEI: Record even parity. Normal operation.
 249         | g. FCOM:   Normal operation
 250         | h. MMUPEI: Record even parity. Normal operation.
 251         | i. FFF:    Flush only as much data as necessary.
 252         | j. TCS:    Timebase increments from CPU clock.
 253         +-----------------------------------------------------------------*/
 254         li      r0,0
 255         mtspr   ccr1, r0
 256
 257         /*----------------------------------------------------------------+
 258         | Reset the timebase.
 259         | The previous write to CCR1 sets the timebase source.
 260         +-----------------------------------------------------------------*/
 261         mtspr   tbl, r0
 262         mtspr   tbu, r0
 263 #endif
 264
 265         /*----------------------------------------------------------------*/
 266         /* Setup interrupt vectors */
 267         /*----------------------------------------------------------------*/
 268         mtspr   ivpr,r0         /* Vectors start at 0x0000_0000 */
 269         li      r1,0x0100
 270         mtspr   ivor0,r1        /* Critical input */
 271         li      r1,0x0200
 272         mtspr   ivor1,r1        /* Machine check */
 273         li      r1,0x0300
 274         mtspr   ivor2,r1        /* Data storage */
 275         li      r1,0x0400
 276         mtspr   ivor3,r1        /* Instruction storage */
 277         li      r1,0x0500
 278         mtspr   ivor4,r1        /* External interrupt */
 279         li      r1,0x0600
 280         mtspr   ivor5,r1        /* Alignment */
 281         li      r1,0x0700
 282         mtspr   ivor6,r1        /* Program check */
 283         li      r1,0x0800
 284         mtspr   ivor7,r1        /* Floating point unavailable */
 285         li      r1,0x0c00
 286         mtspr   ivor8,r1        /* System call */
 287         li      r1,0x1000
 288         mtspr   ivor10,r1       /* Decrementer (PIT for 440) */
 289         li      r1,0x1400
 290         mtspr   ivor13,r1       /* Data TLB error */
 291         li      r1,0x1300
 292         mtspr   ivor14,r1       /* Instr TLB error */
 293         li      r1,0x2000
 294         mtspr   ivor15,r1       /* Debug */
 295
 296         /*----------------------------------------------------------------*/
 297         /* Configure cache regions  */
 298         /*----------------------------------------------------------------*/
 299         mtspr   inv0,r0
 300         mtspr   inv1,r0
 301         mtspr   inv2,r0
 302         mtspr   inv3,r0
 303         mtspr   dnv0,r0
 304         mtspr   dnv1,r0
 305         mtspr   dnv2,r0
 306         mtspr   dnv3,r0
 307         mtspr   itv0,r0
 308         mtspr   itv1,r0
 309         mtspr   itv2,r0
 310         mtspr   itv3,r0
 311         mtspr   dtv0,r0
 312         mtspr   dtv1,r0
 313         mtspr   dtv2,r0
 314         mtspr   dtv3,r0
 315
 316         /*----------------------------------------------------------------*/
 317         /* Cache victim limits */
 318         /*----------------------------------------------------------------*/
 319         /* floors 0, ceiling max to use the entire cache -- nothing locked
 320         */
 321         lis     r1,0x0001
 322         ori     r1,r1,0xf800
 323         mtspr   ivlim,r1
 324         mtspr   dvlim,r1
 325
 326         /*----------------------------------------------------------------+
 327         |Initialize MMUCR[STID] = 0.
 328         +-----------------------------------------------------------------*/
 329         mfspr   r0,mmucr
 330         addis   r1,0,0xFFFF
 331         ori     r1,r1,0xFF00
 332         and     r0,r0,r1
 333         mtspr   mmucr,r0
 334
 335         /*----------------------------------------------------------------*/
 336         /* Clear all TLB entries -- TID = 0, TS = 0 */
 337         /*----------------------------------------------------------------*/
 338         addis   r0,0,0x0000
 339         li      r1,0x003f       /* 64 TLB entries */
 340         mtctr   r1
 341 rsttlb: tlbwe   r0,r1,0x0000    /* Invalidate all entries (V=0)*/
 342         tlbwe   r0,r1,0x0001
 343         tlbwe   r0,r1,0x0002
 344         subi    r1,r1,0x0001
 345         bdnz    rsttlb
 346
 347         /*----------------------------------------------------------------*/
 348         /* TLB entry setup -- step thru tlbtab */
 349         /*----------------------------------------------------------------*/
 350 #if defined(CONFIG_440SPE)
 351         /*----------------------------------------------------------------*/
 352         /* We have different TLB tables for revA and rev B of 440SPe */
 353         /*----------------------------------------------------------------*/
 354         mfspr   r1, PVR
 355         lis     r0,0x5342
 356         ori     r0,r0,0x1891
 357         cmpw    r7,r1,r0
 358         bne     r7,..revA
 359         bl      tlbtabB
 360         b       ..goon
 361 ..revA:
 362         bl      tlbtabA
 363 ..goon:
 364 #else
 365         bl      tlbtab          /* Get tlbtab pointer */
 366 #endif
 367         mr      r5,r0
 368         li      r1,0x003f       /* 64 TLB entries max */
 369         mtctr   r1
 370         li      r4,0            /* TLB # */
 371
 372         addi    r5,r5,-4
 373 1:      lwzu    r0,4(r5)
 374         cmpwi   r0,0
 375         beq     2f              /* 0 marks end */
 376         lwzu    r1,4(r5)
 377         lwzu    r2,4(r5)
 378         tlbwe   r0,r4,0         /* TLB Word 0 */
 379         tlbwe   r1,r4,1         /* TLB Word 1 */
 380         tlbwe   r2,r4,2         /* TLB Word 2 */
 381         addi    r4,r4,1         /* Next TLB */
 382         bdnz    1b
 383
 384         /*----------------------------------------------------------------*/
 385         /* Continue from 'normal' start */
 386         /*----------------------------------------------------------------*/
 387 2:
 388
 389 #if defined(CONFIG_NAND_SPL)
 390         /*
 391          * Enable internal SRAM
 392          */
 393         lis     r2,0x7fff
 394         ori     r2,r2,0xffff
 395         mfdcr   r1,isram0_dpc
 396         and     r1,r1,r2                /* Disable parity check */
 397         mtdcr   isram0_dpc,r1
 398         mfdcr   r1,isram0_pmeg
 399         and     r1,r1,r2                /* Disable pwr mgmt */
 400         mtdcr   isram0_pmeg,r1
 401
 402         /*
 403          * Copy SPL from cache into internal SRAM
 404          */
 405         li      r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
 406         mtctr   r4
 407         lis     r2,CFG_NAND_BOOT_SPL_SRC@h
 408         ori     r2,r2,CFG_NAND_BOOT_SPL_SRC@l
 409         lis     r3,CFG_NAND_BOOT_SPL_DST@h
 410         ori     r3,r3,CFG_NAND_BOOT_SPL_DST@l
 411 spl_loop:
 412         lwzu    r4,4(r2)
 413         stwu    r4,4(r3)
 414         bdnz    spl_loop
 415
 416         /*
 417          * Jump to code in RAM
 418          */
 419         bl      00f
 420 00:     mflr    r10
 421         lis     r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
 422         ori     r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
 423         sub     r10,r10,r3
 424         addi    r10,r10,28
 425         mtlr    r10
 426         blr
 427
 428 start_ram:
 429         sync
 430         isync
 431 #endif
 432
 433         bl      3f
 434         b       _start
 435
 436 3:      li      r0,0
 437         mtspr   srr1,r0         /* Keep things disabled for now */
 438         mflr    r1
 439         mtspr   srr0,r1
 440         rfi
 441 #endif /* CONFIG_440 */
 442
 443 /*
 444  * r3 - 1st arg to board_init(): IMMP pointer
 445  * r4 - 2nd arg to board_init(): boot flag
 446  */
 447 #ifndef CONFIG_NAND_SPL
 448         .text
 449         .long   0x27051956              /* U-Boot Magic Number                  */
 450         .globl  version_string
 451 version_string:
 452         .ascii U_BOOT_VERSION
 453         .ascii " (", __DATE__, " - ", __TIME__, ")"
 454         .ascii CONFIG_IDENT_STRING, "\0"
 455
 456 /*
 457  * Maybe this should be moved somewhere else because the current
 458  * location (0x100) is where the CriticalInput Execption should be.
 459  */
 460         . = EXC_OFF_SYS_RESET
 461 #endif
 462         .globl  _start
 463 _start:
 464
 465 /*****************************************************************************/
 466 #if defined(CONFIG_440)
 467
 468         /*----------------------------------------------------------------*/
 469         /* Clear and set up some registers. */
 470         /*----------------------------------------------------------------*/
 471         li      r0,0x0000
 472         lis     r1,0xffff
 473         mtspr   dec,r0                  /* prevent dec exceptions */
 474         mtspr   tbl,r0                  /* prevent fit & wdt exceptions */
 475         mtspr   tbu,r0
 476         mtspr   tsr,r1                  /* clear all timer exception status */
 477         mtspr   tcr,r0                  /* disable all */
 478         mtspr   esr,r0                  /* clear exception syndrome register */
 479         mtxer   r0                      /* clear integer exception register */
 480
 481         /*----------------------------------------------------------------*/
 482         /* Debug setup -- some (not very good) ice's need an event*/
 483         /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
 484         /* value you need in this case 0x8cff 0000 should do the trick */
 485         /*----------------------------------------------------------------*/
 486 #if defined(CFG_INIT_DBCR)
 487         lis     r1,0xffff
 488         ori     r1,r1,0xffff
 489         mtspr   dbsr,r1                 /* Clear all status bits */
 490         lis     r0,CFG_INIT_DBCR@h
 491         ori     r0,r0,CFG_INIT_DBCR@l
 492         mtspr   dbcr0,r0
 493         isync
 494 #endif
 495
 496         /*----------------------------------------------------------------*/
 497         /* Setup the internal SRAM */
 498         /*----------------------------------------------------------------*/
 499         li      r0,0
 500
 501 #ifdef CFG_INIT_RAM_DCACHE
 502         /* Clear Dcache to use as RAM */
 503         addis   r3,r0,CFG_INIT_RAM_ADDR@h
 504         ori     r3,r3,CFG_INIT_RAM_ADDR@l
 505         addis   r4,r0,CFG_INIT_RAM_END@h
 506         ori     r4,r4,CFG_INIT_RAM_END@l
 507         rlwinm. r5,r4,0,27,31
 508         rlwinm  r5,r4,27,5,31
 509         beq     ..d_ran
 510         addi    r5,r5,0x0001
 511 ..d_ran:
 512         mtctr   r5
 513 ..d_ag:
 514         dcbz    r0,r3
 515         addi    r3,r3,32
 516         bdnz    ..d_ag
 517 #endif /* CFG_INIT_RAM_DCACHE */
 518
 519         /* 440EP & 440GR are only 440er PPC's without internal SRAM */
 520 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
 521         /* not all PPC's have internal SRAM usable as L2-cache */
 522 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 523         mtdcr   l2_cache_cfg,r0         /* Ensure L2 Cache is off */
 524 #endif
 525
 526         lis     r2,0x7fff
 527         ori     r2,r2,0xffff
 528         mfdcr   r1,isram0_dpc
 529         and     r1,r1,r2                /* Disable parity check */
 530         mtdcr   isram0_dpc,r1
 531         mfdcr   r1,isram0_pmeg
 532         and     r1,r1,r2                /* Disable pwr mgmt */
 533         mtdcr   isram0_pmeg,r1
 534
 535         lis     r1,0x8000               /* BAS = 8000_0000 */
 536 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 537         ori     r1,r1,0x0980            /* first 64k */
 538         mtdcr   isram0_sb0cr,r1
 539         lis     r1,0x8001
 540         ori     r1,r1,0x0980            /* second 64k */
 541         mtdcr   isram0_sb1cr,r1
 542         lis     r1, 0x8002
 543         ori     r1,r1, 0x0980           /* third 64k */
 544         mtdcr   isram0_sb2cr,r1
 545         lis     r1, 0x8003
 546         ori     r1,r1, 0x0980           /* fourth 64k */
 547         mtdcr   isram0_sb3cr,r1
 548 #elif defined(CONFIG_440SPE)
 549         lis     r1,0x0000               /* BAS = 0000_0000 */
 550         ori     r1,r1,0x0984            /* first 64k */
 551         mtdcr   isram0_sb0cr,r1
 552         lis     r1,0x0001
 553         ori     r1,r1,0x0984            /* second 64k */
 554         mtdcr   isram0_sb1cr,r1
 555         lis     r1, 0x0002
 556         ori     r1,r1, 0x0984           /* third 64k */
 557         mtdcr   isram0_sb2cr,r1
 558         lis     r1, 0x0003
 559         ori     r1,r1, 0x0984           /* fourth 64k */
 560         mtdcr   isram0_sb3cr,r1
 561 #elif defined(CONFIG_440GP)
 562         ori     r1,r1,0x0380            /* 8k rw */
 563         mtdcr   isram0_sb0cr,r1
 564         mtdcr   isram0_sb1cr,r0         /* Disable bank 1 */
 565 #endif
 566 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
 567
 568         /*----------------------------------------------------------------*/
 569         /* Setup the stack in internal SRAM */
 570         /*----------------------------------------------------------------*/
 571         lis     r1,CFG_INIT_RAM_ADDR@h
 572         ori     r1,r1,CFG_INIT_SP_OFFSET@l
 573         li      r0,0
 574         stwu    r0,-4(r1)
 575         stwu    r0,-4(r1)               /* Terminate call chain */
 576
 577         stwu    r1,-8(r1)               /* Save back chain and move SP */
 578         lis     r0,RESET_VECTOR@h       /* Address of reset vector */
 579         ori     r0,r0, RESET_VECTOR@l
 580         stwu    r1,-8(r1)               /* Save back chain and move SP */
 581         stw     r0,+12(r1)              /* Save return addr (underflow vect) */
 582
 583 #ifdef CONFIG_NAND_SPL
 584         bl      nand_boot               /* will not return */
 585 #else
 586         GET_GOT
 587
 588         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 589         bl      board_init_f
 590 #endif
 591
 592 #endif /* CONFIG_440 */
 593
 594 /*****************************************************************************/
 595 #ifdef CONFIG_IOP480
 596         /*----------------------------------------------------------------------- */
 597         /* Set up some machine state registers. */
 598         /*----------------------------------------------------------------------- */
 599         addi    r0,r0,0x0000            /* initialize r0 to zero */
 600         mtspr   esr,r0                  /* clear Exception Syndrome Reg */
 601         mttcr   r0                      /* timer control register */
 602         mtexier r0                      /* disable all interrupts */
 603         addis   r4,r0,0xFFFF            /* set r4 to 0xFFFFFFFF (status in the */
 604         ori     r4,r4,0xFFFF            /* dbsr is cleared by setting bits to 1) */
 605         mtdbsr  r4                      /* clear/reset the dbsr */
 606         mtexisr r4                      /* clear all pending interrupts */
 607         addis   r4,r0,0x8000
 608         mtexier r4                      /* enable critical exceptions */
 609         addis   r4,r0,0x0000            /* assume 403GCX - enable core clk */
 610         ori     r4,r4,0x4020            /* dbling (no harm done on GA and GC */
 611         mtiocr  r4                      /* since bit not used) & DRC to latch */
 612                                         /* data bus on rising edge of CAS */
 613         /*----------------------------------------------------------------------- */
 614         /* Clear XER. */
 615         /*----------------------------------------------------------------------- */
 616         mtxer   r0
 617         /*----------------------------------------------------------------------- */
 618         /* Invalidate i-cache and d-cache TAG arrays. */
 619         /*----------------------------------------------------------------------- */
 620         addi    r3,0,1024               /* 1/4 of I-cache size, half of D-cache */
 621         addi    r4,0,1024               /* 1/4 of I-cache */
 622 ..cloop:
 623         iccci   0,r3
 624         iccci   r4,r3
 625         dccci   0,r3
 626         addic.  r3,r3,-16               /* move back one cache line */
 627         bne     ..cloop                 /* loop back to do rest until r3 = 0 */
 628
 629         /* */
 630         /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
 631         /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
 632         /* */
 633
 634         /* first copy IOP480 register base address into r3 */
 635         addis   r3,0,0x5000             /* IOP480 register base address hi */
 636 /*      ori     r3,r3,0x0000            /  IOP480 register base address lo */
 637
 638 #ifdef CONFIG_ADCIOP
 639         /* use r4 as the working variable */
 640         /* turn on CS3 (LOCCTL.7) */
 641         lwz     r4,0x84(r3)             /* LOCTL is at offset 0x84 */
 642         andi.   r4,r4,0xff7f            /* make bit 7 = 0 -- CS3 mode */
 643         stw     r4,0x84(r3)             /* LOCTL is at offset 0x84 */
 644 #endif
 645
 646 #ifdef CONFIG_DASA_SIM
 647         /* use r4 as the working variable */
 648         /* turn on MA17 (LOCCTL.7) */
 649         lwz     r4,0x84(r3)             /* LOCTL is at offset 0x84 */
 650         ori     r4,r4,0x80              /* make bit 7 = 1 -- MA17 mode */
 651         stw     r4,0x84(r3)             /* LOCTL is at offset 0x84 */
 652 #endif
 653
 654         /* turn on MA16..13 (LCS0BRD.12 = 0) */
 655         lwz     r4,0x100(r3)            /* LCS0BRD is at offset 0x100 */
 656         andi.   r4,r4,0xefff            /* make bit 12 = 0 */
 657         stw     r4,0x100(r3)            /* LCS0BRD is at offset 0x100 */
 658
 659         /* make sure above stores all comlete before going on */
 660         sync
 661
 662         /* last thing, set local init status done bit (DEVINIT.31) */
 663         lwz     r4,0x80(r3)             /* DEVINIT is at offset 0x80 */
 664         oris    r4,r4,0x8000            /* make bit 31 = 1 */
 665         stw     r4,0x80(r3)             /* DEVINIT is at offset 0x80 */
 666
 667         /* clear all pending interrupts and disable all interrupts */
 668         li      r4,-1                   /* set p1 to 0xffffffff */
 669         stw     r4,0x1b0(r3)            /* clear all pending interrupts */
 670         stw     r4,0x1b8(r3)            /* clear all pending interrupts */
 671         li      r4,0                    /* set r4 to 0 */
 672         stw     r4,0x1b4(r3)            /* disable all interrupts */
 673         stw     r4,0x1bc(r3)            /* disable all interrupts */
 674
 675         /* make sure above stores all comlete before going on */
 676         sync
 677
 678         /*----------------------------------------------------------------------- */
 679         /* Enable two 128MB cachable regions. */
 680         /*----------------------------------------------------------------------- */
 681         addis   r1,r0,0x8000
 682         addi    r1,r1,0x0001
 683         mticcr  r1                      /* instruction cache */
 684
 685         addis   r1,r0,0x0000
 686         addi    r1,r1,0x0000
 687         mtdccr  r1                      /* data cache */
 688
 689         addis   r1,r0,CFG_INIT_RAM_ADDR@h
 690         ori     r1,r1,CFG_INIT_SP_OFFSET          /* set up the stack to SDRAM */
 691         li      r0, 0                   /* Make room for stack frame header and */
 692         stwu    r0, -4(r1)              /* clear final stack frame so that      */
 693         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
 694
 695         GET_GOT                 /* initialize GOT access                        */
 696
 697         bl      board_init_f    /* run first part of init code (from Flash)     */
 698
 699 #endif  /* CONFIG_IOP480 */
 700
 701 /*****************************************************************************/
 702 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP)
 703         /*----------------------------------------------------------------------- */
 704         /* Clear and set up some registers. */
 705         /*----------------------------------------------------------------------- */
 706         addi    r4,r0,0x0000
 707         mtspr   sgr,r4
 708         mtspr   dcwr,r4
 709         mtesr   r4                      /* clear Exception Syndrome Reg */
 710         mttcr   r4                      /* clear Timer Control Reg */
 711         mtxer   r4                      /* clear Fixed-Point Exception Reg */
 712         mtevpr  r4                      /* clear Exception Vector Prefix Reg */
 713         addi    r4,r0,(0xFFFF-0x10000)          /* set r4 to 0xFFFFFFFF (status in the */
 714                                         /* dbsr is cleared by setting bits to 1) */
 715         mtdbsr  r4                      /* clear/reset the dbsr */
 716
 717         /*----------------------------------------------------------------------- */
 718         /* Invalidate I and D caches. Enable I cache for defined memory regions */
 719         /* to speed things up. Leave the D cache disabled for now. It will be */
 720         /* enabled/left disabled later based on user selected menu options. */
 721         /* Be aware that the I cache may be disabled later based on the menu */
 722         /* options as well. See miscLib/main.c. */
 723         /*----------------------------------------------------------------------- */
 724         bl      invalidate_icache
 725         bl      invalidate_dcache
 726
 727         /*----------------------------------------------------------------------- */
 728         /* Enable two 128MB cachable regions. */
 729         /*----------------------------------------------------------------------- */
 730         addis   r4,r0,0x8000
 731         addi    r4,r4,0x0001
 732         mticcr  r4                      /* instruction cache */
 733         isync
 734
 735         addis   r4,r0,0x0000
 736         addi    r4,r4,0x0000
 737         mtdccr  r4                      /* data cache */
 738
 739 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
 740         /*----------------------------------------------------------------------- */
 741         /* Tune the speed and size for flash CS0  */
 742         /*----------------------------------------------------------------------- */
 743         bl      ext_bus_cntlr_init
 744 #endif
 745
 746 #if defined(CONFIG_405EP)
 747         /*----------------------------------------------------------------------- */
 748         /* DMA Status, clear to come up clean */
 749         /*----------------------------------------------------------------------- */
 750         addis   r3,r0, 0xFFFF         /* Clear all existing DMA status */
 751         ori     r3,r3, 0xFFFF
 752         mtdcr   dmasr, r3
 753
 754         bl      ppc405ep_init         /* do ppc405ep specific init */
 755 #endif /* CONFIG_405EP */
 756
 757 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
 758         /********************************************************************
 759          * Setup OCM - On Chip Memory
 760          *******************************************************************/
 761         /* Setup OCM */
 762         lis     r0, 0x7FFF
 763         ori     r0, r0, 0xFFFF
 764         mfdcr   r3, ocmiscntl           /* get instr-side IRAM config */
 765         mfdcr   r4, ocmdscntl   /* get data-side IRAM config */
 766         and     r3, r3, r0      /* disable data-side IRAM */
 767         and     r4, r4, r0      /* disable data-side IRAM */
 768         mtdcr   ocmiscntl, r3   /* set instr-side IRAM config */
 769         mtdcr   ocmdscntl, r4   /* set data-side IRAM config */
 770         isync
 771
 772         addis   r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */
 773         mtdcr   ocmdsarc, r3
 774         addis   r4, 0, 0xC000           /* OCM data area enabled */
 775         mtdcr   ocmdscntl, r4
 776         isync
 777 #endif
 778
 779         /*----------------------------------------------------------------------- */
 780         /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
 781         /*----------------------------------------------------------------------- */
 782 #ifdef CFG_INIT_DCACHE_CS
 783         /*----------------------------------------------------------------------- */
 784         /* Memory Bank x (nothingness) initialization 1GB+64MEG */
 785         /* used as temporary stack pointer for stage0  */
 786         /*----------------------------------------------------------------------- */
 787         li      r4,PBxAP
 788         mtdcr   ebccfga,r4
 789         lis     r4,0x0380
 790         ori     r4,r4,0x0480
 791         mtdcr   ebccfgd,r4
 792
 793         addi    r4,0,PBxCR
 794         mtdcr   ebccfga,r4
 795         lis     r4,0x400D
 796         ori     r4,r4,0xa000
 797         mtdcr   ebccfgd,r4
 798
 799         /* turn on data chache for this region */
 800         lis     r4,0x0080
 801         mtdccr  r4
 802
 803         /* set stack pointer and clear stack to known value */
 804
 805         lis     r1,CFG_INIT_RAM_ADDR@h
 806         ori     r1,r1,CFG_INIT_SP_OFFSET@l
 807
 808         li      r4,2048                 /* we store 2048 words to stack */
 809         mtctr   r4
 810
 811         lis     r2,CFG_INIT_RAM_ADDR@h          /* we also clear data area */
 812         ori     r2,r2,CFG_INIT_RAM_END@l        /* so cant copy value from r1 */
 813
 814         lis     r4,0xdead               /* we store 0xdeaddead in the stack */
 815         ori     r4,r4,0xdead
 816
 817 ..stackloop:
 818         stwu    r4,-4(r2)
 819         bdnz    ..stackloop
 820
 821         li      r0, 0                   /* Make room for stack frame header and */
 822         stwu    r0, -4(r1)              /* clear final stack frame so that      */
 823         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
 824         /*
 825          * Set up a dummy frame to store reset vector as return address.
 826          * this causes stack underflow to reset board.
 827          */
 828         stwu    r1, -8(r1)              /* Save back chain and move SP */
 829         addis   r0, 0, RESET_VECTOR@h   /* Address of reset vector */
 830         ori     r0, r0, RESET_VECTOR@l
 831         stwu    r1, -8(r1)              /* Save back chain and move SP */
 832         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
 833
 834 #elif defined(CFG_TEMP_STACK_OCM) && \
 835         (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
 836         /*
 837          * Stack in OCM.
 838          */
 839
 840         /* Set up Stack at top of OCM */
 841         lis     r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
 842         ori     r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
 843
 844         /* Set up a zeroized stack frame so that backtrace works right */
 845         li      r0, 0
 846         stwu    r0, -4(r1)
 847         stwu    r0, -4(r1)
 848
 849         /*
 850          * Set up a dummy frame to store reset vector as return address.
 851          * this causes stack underflow to reset board.
 852          */
 853         stwu    r1, -8(r1)              /* Save back chain and move SP */
 854         lis     r0, RESET_VECTOR@h      /* Address of reset vector */
 855         ori     r0, r0, RESET_VECTOR@l
 856         stwu    r1, -8(r1)              /* Save back chain and move SP */
 857         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
 858 #endif /* CFG_INIT_DCACHE_CS */
 859
 860         /*----------------------------------------------------------------------- */
 861         /* Initialize SDRAM Controller  */
 862         /*----------------------------------------------------------------------- */
 863         bl      sdram_init
 864
 865         /*
 866          * Setup temporary stack pointer only for boards
 867          * that do not use SDRAM SPD I2C stuff since it
 868          * is already initialized to use DCACHE or OCM
 869          * stacks.
 870          */
 871 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
 872         lis     r1, CFG_INIT_RAM_ADDR@h
 873         ori     r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
 874
 875         li      r0, 0                   /* Make room for stack frame header and */
 876         stwu    r0, -4(r1)              /* clear final stack frame so that      */
 877         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
 878         /*
 879          * Set up a dummy frame to store reset vector as return address.
 880          * this causes stack underflow to reset board.
 881          */
 882         stwu    r1, -8(r1)              /* Save back chain and move SP */
 883         lis     r0, RESET_VECTOR@h      /* Address of reset vector */
 884         ori     r0, r0, RESET_VECTOR@l
 885         stwu    r1, -8(r1)              /* Save back chain and move SP */
 886         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
 887 #endif /* !(CFG_INIT_DCACHE_CS  || !CFG_TEM_STACK_OCM) */
 888
 889         GET_GOT                 /* initialize GOT access                        */
 890
 891         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 892
 893         /* NEVER RETURNS! */
 894         bl      board_init_f    /* run first part of init code (from Flash)     */
 895
 896 #endif  /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
 897         /*----------------------------------------------------------------------- */
 898
 899
 900 #ifndef CONFIG_NAND_SPL
 901 /*****************************************************************************/
 902         .globl  _start_of_vectors
 903 _start_of_vectors:
 904
 905 #if 0
 906 /*TODO Fixup _start above so we can do this*/
 907 /* Critical input. */
 908         CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException)
 909 #endif
 910
 911 /* Machine check */
 912         CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 913
 914 /* Data Storage exception. */
 915         STD_EXCEPTION(0x300, DataStorage, UnknownException)
 916
 917 /* Instruction Storage exception. */
 918         STD_EXCEPTION(0x400, InstStorage, UnknownException)
 919
 920 /* External Interrupt exception. */
 921         STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 922
 923 /* Alignment exception. */
 924         . = 0x600
 925 Alignment:
 926         EXCEPTION_PROLOG
 927         mfspr   r4,DAR
 928         stw     r4,_DAR(r21)
 929         mfspr   r5,DSISR
 930         stw     r5,_DSISR(r21)
 931         addi    r3,r1,STACK_FRAME_OVERHEAD
 932         li      r20,MSR_KERNEL
 933         rlwimi  r20,r23,0,16,16         /* copy EE bit from saved MSR */
 934         lwz     r6,GOT(transfer_to_handler)
 935         mtlr    r6
 936         blrl
 937 .L_Alignment:
 938         .long   AlignmentException - _start + EXC_OFF_SYS_RESET
 939         .long   int_return - _start + EXC_OFF_SYS_RESET
 940
 941 /* Program check exception */
 942         . = 0x700
 943 ProgramCheck:
 944         EXCEPTION_PROLOG
 945         addi    r3,r1,STACK_FRAME_OVERHEAD
 946         li      r20,MSR_KERNEL
 947         rlwimi  r20,r23,0,16,16         /* copy EE bit from saved MSR */
 948         lwz     r6,GOT(transfer_to_handler)
 949         mtlr    r6
 950         blrl
 951 .L_ProgramCheck:
 952         .long   ProgramCheckException - _start + EXC_OFF_SYS_RESET
 953         .long   int_return - _start + EXC_OFF_SYS_RESET
 954
 955         /* No FPU on MPC8xx.  This exception is not supposed to happen.
 956         */
 957         STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 958
 959         /* I guess we could implement decrementer, and may have
 960          * to someday for timekeeping.
 961          */
 962         STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 963         STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 964         STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
 965         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 966         STD_EXCEPTION(0xd00, SingleStep, UnknownException)
 967
 968         STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
 969         STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
 970
 971         /* On the MPC8xx, this is a software emulation interrupt.  It occurs
 972          * for all unimplemented and illegal instructions.
 973          */
 974         STD_EXCEPTION(0x1000, PIT, PITException)
 975
 976         STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
 977         STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
 978         STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
 979         STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
 980
 981         STD_EXCEPTION(0x1500, Reserved5, UnknownException)
 982         STD_EXCEPTION(0x1600, Reserved6, UnknownException)
 983         STD_EXCEPTION(0x1700, Reserved7, UnknownException)
 984         STD_EXCEPTION(0x1800, Reserved8, UnknownException)
 985         STD_EXCEPTION(0x1900, Reserved9, UnknownException)
 986         STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
 987         STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
 988
 989         STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
 990         STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
 991         STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
 992         STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
 993
 994         CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
 995
 996         .globl  _end_of_vectors
 997 _end_of_vectors:
 998
 999
1000         . = 0x2100
1001
1002 /*
1003  * This code finishes saving the registers to the exception frame
1004  * and jumps to the appropriate handler for the exception.
1005  * Register r21 is pointer into trap frame, r1 has new stack pointer.
1006  */
1007         .globl  transfer_to_handler
1008 transfer_to_handler:
1009         stw     r22,_NIP(r21)
1010         lis     r22,MSR_POW@h
1011         andc    r23,r23,r22
1012         stw     r23,_MSR(r21)
1013         SAVE_GPR(7, r21)
1014         SAVE_4GPRS(8, r21)
1015         SAVE_8GPRS(12, r21)
1016         SAVE_8GPRS(24, r21)
1017 #if 0
1018         andi.   r23,r23,MSR_PR
1019         mfspr   r23,SPRG3               /* if from user, fix up tss.regs */
1020         beq     2f
1021         addi    r24,r1,STACK_FRAME_OVERHEAD
1022         stw     r24,PT_REGS(r23)
1023 2:      addi    r2,r23,-TSS             /* set r2 to current */
1024         tovirt(r2,r2,r23)
1025 #endif
1026         mflr    r23
1027         andi.   r24,r23,0x3f00          /* get vector offset */
1028         stw     r24,TRAP(r21)
1029         li      r22,0
1030         stw     r22,RESULT(r21)
1031         mtspr   SPRG2,r22               /* r1 is now kernel sp */
1032 #if 0
1033         addi    r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
1034         cmplw   0,r1,r2
1035         cmplw   1,r1,r24
1036         crand   1,1,4
1037         bgt     stack_ovf               /* if r2 < r1 < r2+TASK_STRUCT_SIZE */
1038 #endif
1039         lwz     r24,0(r23)              /* virtual address of handler */
1040         lwz     r23,4(r23)              /* where to go when done */
1041         mtspr   SRR0,r24
1042         mtspr   SRR1,r20
1043         mtlr    r23
1044         SYNC
1045         rfi                             /* jump to handler, enable MMU */
1046
1047 int_return:
1048         mfmsr   r28             /* Disable interrupts */
1049         li      r4,0
1050         ori     r4,r4,MSR_EE
1051         andc    r28,r28,r4
1052         SYNC                    /* Some chip revs need this... */
1053         mtmsr   r28
1054         SYNC
1055         lwz     r2,_CTR(r1)
1056         lwz     r0,_LINK(r1)
1057         mtctr   r2
1058         mtlr    r0
1059         lwz     r2,_XER(r1)
1060         lwz     r0,_CCR(r1)
1061         mtspr   XER,r2
1062         mtcrf   0xFF,r0
1063         REST_10GPRS(3, r1)
1064         REST_10GPRS(13, r1)
1065         REST_8GPRS(23, r1)
1066         REST_GPR(31, r1)
1067         lwz     r2,_NIP(r1)     /* Restore environment */
1068         lwz     r0,_MSR(r1)
1069         mtspr   SRR0,r2
1070         mtspr   SRR1,r0
1071         lwz     r0,GPR0(r1)
1072         lwz     r2,GPR2(r1)
1073         lwz     r1,GPR1(r1)
1074         SYNC
1075         rfi
1076
1077 crit_return:
1078         mfmsr   r28             /* Disable interrupts */
1079         li      r4,0
1080         ori     r4,r4,MSR_EE
1081         andc    r28,r28,r4
1082         SYNC                    /* Some chip revs need this... */
1083         mtmsr   r28
1084         SYNC
1085         lwz     r2,_CTR(r1)
1086         lwz     r0,_LINK(r1)
1087         mtctr   r2
1088         mtlr    r0
1089         lwz     r2,_XER(r1)
1090         lwz     r0,_CCR(r1)
1091         mtspr   XER,r2
1092         mtcrf   0xFF,r0
1093         REST_10GPRS(3, r1)
1094         REST_10GPRS(13, r1)
1095         REST_8GPRS(23, r1)
1096         REST_GPR(31, r1)
1097         lwz     r2,_NIP(r1)     /* Restore environment */
1098         lwz     r0,_MSR(r1)
1099         mtspr   990,r2          /* SRR2 */
1100         mtspr   991,r0          /* SRR3 */
1101         lwz     r0,GPR0(r1)
1102         lwz     r2,GPR2(r1)
1103         lwz     r1,GPR1(r1)
1104         SYNC
1105         rfci
1106 #endif /* CONFIG_NAND_SPL */
1107
1108 /* Cache functions.
1109 */
1110 invalidate_icache:
1111         iccci   r0,r0                   /* for 405, iccci invalidates the */
1112         blr                             /*   entire I cache */
1113
1114 invalidate_dcache:
1115         addi    r6,0,0x0000             /* clear GPR 6 */
1116         /* Do loop for # of dcache congruence classes. */
1117         lis     r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha       /* TBS for large sized cache */
1118         ori     r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1119                                         /* NOTE: dccci invalidates both */
1120         mtctr   r7                      /* ways in the D cache */
1121 ..dcloop:
1122         dccci   0,r6                    /* invalidate line */
1123         addi    r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
1124         bdnz    ..dcloop
1125         blr
1126
1127 flush_dcache:
1128         addis   r9,r0,0x0002            /* set mask for EE and CE msr bits */
1129         ori     r9,r9,0x8000
1130         mfmsr   r12                     /* save msr */
1131         andc    r9,r12,r9
1132         mtmsr   r9                      /* disable EE and CE */
1133         addi    r10,r0,0x0001           /* enable data cache for unused memory */
1134         mfdccr  r9                      /* region 0xF8000000-0xFFFFFFFF via */
1135         or      r10,r10,r9              /* bit 31 in dccr */
1136         mtdccr  r10
1137
1138         /* do loop for # of congruence classes. */
1139         lis     r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha       /* TBS: for large cache sizes */
1140         ori     r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1141         lis     r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
1142         ori     r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
1143         mtctr   r10
1144         addi    r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
1145         add     r11,r10,r11             /* add to get to other side of cache line */
1146 ..flush_dcache_loop:
1147         lwz     r3,0(r10)               /* least recently used side */
1148         lwz     r3,0(r11)               /* the other side */
1149         dccci   r0,r11                  /* invalidate both sides */
1150         addi    r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
1151         addi    r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
1152         bdnz    ..flush_dcache_loop
1153         sync                            /* allow memory access to complete */
1154         mtdccr  r9                      /* restore dccr */
1155         mtmsr   r12                     /* restore msr */
1156         blr
1157
1158         .globl  icache_enable
1159 icache_enable:
1160         mflr    r8
1161         bl      invalidate_icache
1162         mtlr    r8
1163         isync
1164         addis   r3,r0, 0x8000         /* set bit 0 */
1165         mticcr  r3
1166         blr
1167
1168         .globl  icache_disable
1169 icache_disable:
1170         addis   r3,r0, 0x0000         /* clear bit 0 */
1171         mticcr  r3
1172         isync
1173         blr
1174
1175         .globl  icache_status
1176 icache_status:
1177         mficcr  r3
1178         srwi    r3, r3, 31      /* >>31 => select bit 0 */
1179         blr
1180
1181         .globl  dcache_enable
1182 dcache_enable:
1183         mflr    r8
1184         bl      invalidate_dcache
1185         mtlr    r8
1186         isync
1187         addis   r3,r0, 0x8000         /* set bit 0 */
1188         mtdccr  r3
1189         blr
1190
1191         .globl  dcache_disable
1192 dcache_disable:
1193         mflr    r8
1194         bl      flush_dcache
1195         mtlr    r8
1196         addis   r3,r0, 0x0000         /* clear bit 0 */
1197         mtdccr  r3
1198         blr
1199
1200         .globl  dcache_status
1201 dcache_status:
1202         mfdccr  r3
1203         srwi    r3, r3, 31      /* >>31 => select bit 0 */
1204         blr
1205
1206         .globl get_pvr
1207 get_pvr:
1208         mfspr   r3, PVR
1209         blr
1210
1211 #if !defined(CONFIG_440)
1212         .globl wr_pit
1213 wr_pit:
1214         mtspr   pit, r3
1215         blr
1216 #endif
1217
1218         .globl wr_tcr
1219 wr_tcr:
1220         mtspr   tcr, r3
1221         blr
1222
1223 /*------------------------------------------------------------------------------- */
1224 /* Function:     in8 */
1225 /* Description:  Input 8 bits */
1226 /*------------------------------------------------------------------------------- */
1227         .globl  in8
1228 in8:
1229         lbz     r3,0x0000(r3)
1230         blr
1231
1232 /*------------------------------------------------------------------------------- */
1233 /* Function:     out8 */
1234 /* Description:  Output 8 bits */
1235 /*------------------------------------------------------------------------------- */
1236         .globl  out8
1237 out8:
1238         stb     r4,0x0000(r3)
1239         blr
1240
1241 /*------------------------------------------------------------------------------- */
1242 /* Function:     out16 */
1243 /* Description:  Output 16 bits */
1244 /*------------------------------------------------------------------------------- */
1245         .globl  out16
1246 out16:
1247         sth     r4,0x0000(r3)
1248         blr
1249
1250 /*------------------------------------------------------------------------------- */
1251 /* Function:     out16r */
1252 /* Description:  Byte reverse and output 16 bits */
1253 /*------------------------------------------------------------------------------- */
1254         .globl  out16r
1255 out16r:
1256         sthbrx  r4,r0,r3
1257         blr
1258
1259 /*------------------------------------------------------------------------------- */
1260 /* Function:     out32 */
1261 /* Description:  Output 32 bits */
1262 /*------------------------------------------------------------------------------- */
1263         .globl  out32
1264 out32:
1265         stw     r4,0x0000(r3)
1266         blr
1267
1268 /*------------------------------------------------------------------------------- */
1269 /* Function:     out32r */
1270 /* Description:  Byte reverse and output 32 bits */
1271 /*------------------------------------------------------------------------------- */
1272         .globl  out32r
1273 out32r:
1274         stwbrx  r4,r0,r3
1275         blr
1276
1277 /*------------------------------------------------------------------------------- */
1278 /* Function:     in16 */
1279 /* Description:  Input 16 bits */
1280 /*------------------------------------------------------------------------------- */
1281         .globl  in16
1282 in16:
1283         lhz     r3,0x0000(r3)
1284         blr
1285
1286 /*------------------------------------------------------------------------------- */
1287 /* Function:     in16r */
1288 /* Description:  Input 16 bits and byte reverse */
1289 /*------------------------------------------------------------------------------- */
1290         .globl  in16r
1291 in16r:
1292         lhbrx   r3,r0,r3
1293         blr
1294
1295 /*------------------------------------------------------------------------------- */
1296 /* Function:     in32 */
1297 /* Description:  Input 32 bits */
1298 /*------------------------------------------------------------------------------- */
1299         .globl  in32
1300 in32:
1301         lwz     3,0x0000(3)
1302         blr
1303
1304 /*------------------------------------------------------------------------------- */
1305 /* Function:     in32r */
1306 /* Description:  Input 32 bits and byte reverse */
1307 /*------------------------------------------------------------------------------- */
1308         .globl  in32r
1309 in32r:
1310         lwbrx   r3,r0,r3
1311         blr
1312
1313 /*------------------------------------------------------------------------------- */
1314 /* Function:     ppcDcbf */
1315 /* Description:  Data Cache block flush */
1316 /* Input:        r3 = effective address */
1317 /* Output:       none. */
1318 /*------------------------------------------------------------------------------- */
1319         .globl  ppcDcbf
1320 ppcDcbf:
1321         dcbf    r0,r3
1322         blr
1323
1324 /*------------------------------------------------------------------------------- */
1325 /* Function:     ppcDcbi */
1326 /* Description:  Data Cache block Invalidate */
1327 /* Input:        r3 = effective address */
1328 /* Output:       none. */
1329 /*------------------------------------------------------------------------------- */
1330         .globl  ppcDcbi
1331 ppcDcbi:
1332         dcbi    r0,r3
1333         blr
1334
1335 /*------------------------------------------------------------------------------- */
1336 /* Function:     ppcSync */
1337 /* Description:  Processor Synchronize */
1338 /* Input:        none. */
1339 /* Output:       none. */
1340 /*------------------------------------------------------------------------------- */
1341         .globl  ppcSync
1342 ppcSync:
1343         sync
1344         blr
1345
1346 /*------------------------------------------------------------------------------*/
1347
1348 #ifndef CONFIG_NAND_SPL
1349 /*
1350  * void relocate_code (addr_sp, gd, addr_moni)
1351  *
1352  * This "function" does not return, instead it continues in RAM
1353  * after relocating the monitor code.
1354  *
1355  * r3 = dest
1356  * r4 = src
1357  * r5 = length in bytes
1358  * r6 = cachelinesize
1359  */
1360         .globl  relocate_code
1361 relocate_code:
1362 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1363     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1364     defined(CONFIG_440SPE)
1365         /*
1366          * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1367          * to speed up the boot process. Now this cache needs to be disabled.
1368          */
1369         iccci   0,0                     /* Invalidate inst cache */
1370         dccci   0,0                     /* Invalidate data cache, now no longer our stack */
1371         sync
1372         isync
1373         addi    r1,r0,0x0000            /* TLB entry #0 */
1374         tlbre   r0,r1,0x0002            /* Read contents */
1375         ori     r0,r0,0x0c00            /* Or in the inhibit, write through bit */
1376         tlbwe   r0,r1,0x0002            /* Save it out */
1377         sync
1378         isync
1379 #endif
1380         mr      r1,  r3         /* Set new stack pointer                */
1381         mr      r9,  r4         /* Save copy of Init Data pointer       */
1382         mr      r10, r5         /* Save copy of Destination Address     */
1383
1384         mr      r3,  r5                         /* Destination Address  */
1385         lis     r4, CFG_MONITOR_BASE@h          /* Source      Address  */
1386         ori     r4, r4, CFG_MONITOR_BASE@l
1387         lwz     r5, GOT(__init_end)
1388         sub     r5, r5, r4
1389         li      r6, CFG_CACHELINE_SIZE          /* Cache Line Size      */
1390
1391         /*
1392          * Fix GOT pointer:
1393          *
1394          * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1395          *
1396          * Offset:
1397          */
1398         sub     r15, r10, r4
1399
1400         /* First our own GOT */
1401         add     r14, r14, r15
1402         /* the the one used by the C code */
1403         add     r30, r30, r15
1404
1405         /*
1406          * Now relocate code
1407          */
1408
1409         cmplw   cr1,r3,r4
1410         addi    r0,r5,3
1411         srwi.   r0,r0,2
1412         beq     cr1,4f          /* In place copy is not necessary       */
1413         beq     7f              /* Protect against 0 count              */
1414         mtctr   r0
1415         bge     cr1,2f
1416
1417         la      r8,-4(r4)
1418         la      r7,-4(r3)
1419 1:      lwzu    r0,4(r8)
1420         stwu    r0,4(r7)
1421         bdnz    1b
1422         b       4f
1423
1424 2:      slwi    r0,r0,2
1425         add     r8,r4,r0
1426         add     r7,r3,r0
1427 3:      lwzu    r0,-4(r8)
1428         stwu    r0,-4(r7)
1429         bdnz    3b
1430
1431 /*
1432  * Now flush the cache: note that we must start from a cache aligned
1433  * address. Otherwise we might miss one cache line.
1434  */
1435 4:      cmpwi   r6,0
1436         add     r5,r3,r5
1437         beq     7f              /* Always flush prefetch queue in any case */
1438         subi    r0,r6,1
1439         andc    r3,r3,r0
1440         mr      r4,r3
1441 5:      dcbst   0,r4
1442         add     r4,r4,r6
1443         cmplw   r4,r5
1444         blt     5b
1445         sync                    /* Wait for all dcbst to complete on bus */
1446         mr      r4,r3
1447 6:      icbi    0,r4
1448         add     r4,r4,r6
1449         cmplw   r4,r5
1450         blt     6b
1451 7:      sync                    /* Wait for all icbi to complete on bus */
1452         isync
1453
1454 /*
1455  * We are done. Do not return, instead branch to second part of board
1456  * initialization, now running from RAM.
1457  */
1458
1459         addi    r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
1460         mtlr    r0
1461         blr                             /* NEVER RETURNS! */
1462
1463 in_ram:
1464
1465         /*
1466          * Relocation Function, r14 point to got2+0x8000
1467          *
1468          * Adjust got2 pointers, no need to check for 0, this code
1469          * already puts a few entries in the table.
1470          */
1471         li      r0,__got2_entries@sectoff@l
1472         la      r3,GOT(_GOT2_TABLE_)
1473         lwz     r11,GOT(_GOT2_TABLE_)
1474         mtctr   r0
1475         sub     r11,r3,r11
1476         addi    r3,r3,-4
1477 1:      lwzu    r0,4(r3)
1478         add     r0,r0,r11
1479         stw     r0,0(r3)
1480         bdnz    1b
1481
1482         /*
1483          * Now adjust the fixups and the pointers to the fixups
1484          * in case we need to move ourselves again.
1485          */
1486 2:      li      r0,__fixup_entries@sectoff@l
1487         lwz     r3,GOT(_FIXUP_TABLE_)
1488         cmpwi   r0,0
1489         mtctr   r0
1490         addi    r3,r3,-4
1491         beq     4f
1492 3:      lwzu    r4,4(r3)
1493         lwzux   r0,r4,r11
1494         add     r0,r0,r11
1495         stw     r10,0(r3)
1496         stw     r0,0(r4)
1497         bdnz    3b
1498 4:
1499 clear_bss:
1500         /*
1501          * Now clear BSS segment
1502          */
1503         lwz     r3,GOT(__bss_start)
1504         lwz     r4,GOT(_end)
1505
1506         cmplw   0, r3, r4
1507         beq     6f
1508
1509         li      r0, 0
1510 5:
1511         stw     r0, 0(r3)
1512         addi    r3, r3, 4
1513         cmplw   0, r3, r4
1514         bne     5b
1515 6:
1516
1517         mr      r3, r9          /* Init Data pointer            */
1518         mr      r4, r10         /* Destination Address          */
1519         bl      board_init_r
1520
1521         /*
1522          * Copy exception vector code to low memory
1523          *
1524          * r3: dest_addr
1525          * r7: source address, r8: end address, r9: target address
1526          */
1527         .globl  trap_init
1528 trap_init:
1529         lwz     r7, GOT(_start)
1530         lwz     r8, GOT(_end_of_vectors)
1531
1532         li      r9, 0x100               /* reset vector always at 0x100 */
1533
1534         cmplw   0, r7, r8
1535         bgelr                           /* return if r7>=r8 - just in case */
1536
1537         mflr    r4                      /* save link register           */
1538 1:
1539         lwz     r0, 0(r7)
1540         stw     r0, 0(r9)
1541         addi    r7, r7, 4
1542         addi    r9, r9, 4
1543         cmplw   0, r7, r8
1544         bne     1b
1545
1546         /*
1547          * relocate `hdlr' and `int_return' entries
1548          */
1549         li      r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1550         li      r8, Alignment - _start + EXC_OFF_SYS_RESET
1551 2:
1552         bl      trap_reloc
1553         addi    r7, r7, 0x100           /* next exception vector        */
1554         cmplw   0, r7, r8
1555         blt     2b
1556
1557         li      r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1558         bl      trap_reloc
1559
1560         li      r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1561         bl      trap_reloc
1562
1563         li      r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1564         li      r8, SystemCall - _start + EXC_OFF_SYS_RESET
1565 3:
1566         bl      trap_reloc
1567         addi    r7, r7, 0x100           /* next exception vector        */
1568         cmplw   0, r7, r8
1569         blt     3b
1570
1571         li      r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1572         li      r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1573 4:
1574         bl      trap_reloc
1575         addi    r7, r7, 0x100           /* next exception vector        */
1576         cmplw   0, r7, r8
1577         blt     4b
1578
1579 #if !defined(CONFIG_440)
1580         addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
1581         oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
1582         mtmsr   r7                      /* change MSR */
1583 #else
1584         bl      __440_msr_set
1585         b       __440_msr_continue
1586
1587 __440_msr_set:
1588         addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
1589         oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
1590         mtspr   srr1,r7
1591         mflr    r7
1592         mtspr   srr0,r7
1593         rfi
1594 __440_msr_continue:
1595 #endif
1596
1597         mtlr    r4                      /* restore link register        */
1598         blr
1599
1600         /*
1601          * Function: relocate entries for one exception vector
1602          */
1603 trap_reloc:
1604         lwz     r0, 0(r7)               /* hdlr ...                     */
1605         add     r0, r0, r3              /*  ... += dest_addr            */
1606         stw     r0, 0(r7)
1607
1608         lwz     r0, 4(r7)               /* int_return ...               */
1609         add     r0, r0, r3              /*  ... += dest_addr            */
1610         stw     r0, 4(r7)
1611
1612         blr
1613 #endif /* CONFIG_NAND_SPL */
1614
1615
1616 /**************************************************************************/
1617 /* PPC405EP specific stuff                                                */
1618 /**************************************************************************/
1619 #ifdef CONFIG_405EP
1620 ppc405ep_init:
1621
1622 #ifdef CONFIG_BUBINGA
1623         /*
1624          * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1625          * function) to support FPGA and NVRAM accesses below.
1626          */
1627
1628         lis     r3,GPIO0_OSRH@h         /* config GPIO output select */
1629         ori     r3,r3,GPIO0_OSRH@l
1630         lis     r4,CFG_GPIO0_OSRH@h
1631         ori     r4,r4,CFG_GPIO0_OSRH@l
1632         stw     r4,0(r3)
1633         lis     r3,GPIO0_OSRL@h
1634         ori     r3,r3,GPIO0_OSRL@l
1635         lis     r4,CFG_GPIO0_OSRL@h
1636         ori     r4,r4,CFG_GPIO0_OSRL@l
1637         stw     r4,0(r3)
1638
1639         lis     r3,GPIO0_ISR1H@h        /* config GPIO input select */
1640         ori     r3,r3,GPIO0_ISR1H@l
1641         lis     r4,CFG_GPIO0_ISR1H@h
1642         ori     r4,r4,CFG_GPIO0_ISR1H@l
1643         stw     r4,0(r3)
1644         lis     r3,GPIO0_ISR1L@h
1645         ori     r3,r3,GPIO0_ISR1L@l
1646         lis     r4,CFG_GPIO0_ISR1L@h
1647         ori     r4,r4,CFG_GPIO0_ISR1L@l
1648         stw     r4,0(r3)
1649
1650         lis     r3,GPIO0_TSRH@h         /* config GPIO three-state select */
1651         ori     r3,r3,GPIO0_TSRH@l
1652         lis     r4,CFG_GPIO0_TSRH@h
1653         ori     r4,r4,CFG_GPIO0_TSRH@l
1654         stw     r4,0(r3)
1655         lis     r3,GPIO0_TSRL@h
1656         ori     r3,r3,GPIO0_TSRL@l
1657         lis     r4,CFG_GPIO0_TSRL@h
1658         ori     r4,r4,CFG_GPIO0_TSRL@l
1659         stw     r4,0(r3)
1660
1661         lis     r3,GPIO0_TCR@h          /* config GPIO driver output enables */
1662         ori     r3,r3,GPIO0_TCR@l
1663         lis     r4,CFG_GPIO0_TCR@h
1664         ori     r4,r4,CFG_GPIO0_TCR@l
1665         stw     r4,0(r3)
1666
1667         li      r3,pb1ap                /* program EBC bank 1 for RTC access */
1668         mtdcr   ebccfga,r3
1669         lis     r3,CFG_EBC_PB1AP@h
1670         ori     r3,r3,CFG_EBC_PB1AP@l
1671         mtdcr   ebccfgd,r3
1672         li      r3,pb1cr
1673         mtdcr   ebccfga,r3
1674         lis     r3,CFG_EBC_PB1CR@h
1675         ori     r3,r3,CFG_EBC_PB1CR@l
1676         mtdcr   ebccfgd,r3
1677
1678         li      r3,pb1ap                /* program EBC bank 1 for RTC access */
1679         mtdcr   ebccfga,r3
1680         lis     r3,CFG_EBC_PB1AP@h
1681         ori     r3,r3,CFG_EBC_PB1AP@l
1682         mtdcr   ebccfgd,r3
1683         li      r3,pb1cr
1684         mtdcr   ebccfga,r3
1685         lis     r3,CFG_EBC_PB1CR@h
1686         ori     r3,r3,CFG_EBC_PB1CR@l
1687         mtdcr   ebccfgd,r3
1688
1689         li      r3,pb4ap                /* program EBC bank 4 for FPGA access */
1690         mtdcr   ebccfga,r3
1691         lis     r3,CFG_EBC_PB4AP@h
1692         ori     r3,r3,CFG_EBC_PB4AP@l
1693         mtdcr   ebccfgd,r3
1694         li      r3,pb4cr
1695         mtdcr   ebccfga,r3
1696         lis     r3,CFG_EBC_PB4CR@h
1697         ori     r3,r3,CFG_EBC_PB4CR@l
1698         mtdcr   ebccfgd,r3
1699 #endif
1700
1701 #ifndef CFG_CPC0_PCI
1702         li      r3,CPC0_PCI_HOST_CFG_EN
1703 #ifdef CONFIG_BUBINGA
1704         /*
1705         !-----------------------------------------------------------------------
1706         ! Check FPGA for PCI internal/external arbitration
1707         !   If board is set to internal arbitration, update cpc0_pci
1708         !-----------------------------------------------------------------------
1709         */
1710         addis   r5,r0,FPGA_REG1@h      /* set offset for FPGA_REG1 */
1711         ori     r5,r5,FPGA_REG1@l
1712         lbz     r5,0x0(r5)              /* read to get PCI arb selection */
1713         andi.   r6,r5,FPGA_REG1_PCI_INT_ARB  /* using internal arbiter ?*/
1714         beq     ..pci_cfg_set             /* if not set, then bypass reg write*/
1715 #endif
1716         ori     r3,r3,CPC0_PCI_ARBIT_EN
1717 #else /* CFG_CPC0_PCI */
1718         li      r3,CFG_CPC0_PCI
1719 #endif /* CFG_CPC0_PCI */
1720 ..pci_cfg_set:
1721         mtdcr   CPC0_PCI, r3             /* Enable internal arbiter*/
1722
1723         /*
1724         !-----------------------------------------------------------------------
1725         ! Check to see if chip is in bypass mode.
1726         ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1727         ! CPU reset   Otherwise, skip this step and keep going.
1728         ! Note:  Running BIOS in bypass mode is not supported since PLB speed
1729         !        will not be fast enough for the SDRAM (min 66MHz)
1730         !-----------------------------------------------------------------------
1731         */
1732         mfdcr   r5, CPC0_PLLMR1
1733         rlwinm  r4,r5,1,0x1            /* get system clock source (SSCS) */
1734         cmpi    cr0,0,r4,0x1
1735
1736         beq    pll_done                   /* if SSCS =b'1' then PLL has */
1737                                           /* already been set */
1738                                           /* and CPU has been reset */
1739                                           /* so skip to next section */
1740
1741 #ifdef CONFIG_BUBINGA
1742         /*
1743         !-----------------------------------------------------------------------
1744         ! Read NVRAM to get value to write in PLLMR.
1745         ! If value has not been correctly saved, write default value
1746         ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1747         ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1748         !
1749         ! WARNING:  This code assumes the first three words in the nvram_t
1750         !           structure in openbios.h.  Changing the beginning of
1751         !           the structure will break this code.
1752         !
1753         !-----------------------------------------------------------------------
1754         */
1755         addis   r3,0,NVRAM_BASE@h
1756         addi    r3,r3,NVRAM_BASE@l
1757
1758         lwz     r4, 0(r3)
1759         addis   r5,0,NVRVFY1@h
1760         addi    r5,r5,NVRVFY1@l
1761         cmp     cr0,0,r4,r5            /* Compare 1st NVRAM Magic number*/
1762         bne     ..no_pllset
1763         addi    r3,r3,4
1764         lwz     r4, 0(r3)
1765         addis   r5,0,NVRVFY2@h
1766         addi    r5,r5,NVRVFY2@l
1767         cmp     cr0,0,r4,r5            /* Compare 2 NVRAM Magic number */
1768         bne     ..no_pllset
1769         addi    r3,r3,8                 /* Skip over conf_size */
1770         lwz     r4, 4(r3)               /* Load PLLMR1 value from NVRAM */
1771         lwz     r3, 0(r3)               /* Load PLLMR0 value from NVRAM */
1772         rlwinm  r5,r4,1,0x1             /* get system clock source (SSCS) */
1773         cmpi     cr0,0,r5,1             /* See if PLL is locked */
1774         beq     pll_write
1775 ..no_pllset:
1776 #endif /* CONFIG_BUBINGA */
1777
1778         addis   r3,0,PLLMR0_DEFAULT@h       /* PLLMR0 default value */
1779         ori     r3,r3,PLLMR0_DEFAULT@l     /* */
1780         addis   r4,0,PLLMR1_DEFAULT@h       /* PLLMR1 default value */
1781         ori     r4,r4,PLLMR1_DEFAULT@l     /* */
1782
1783         b       pll_write                 /* Write the CPC0_PLLMR with new value */
1784
1785 pll_done:
1786         /*
1787         !-----------------------------------------------------------------------
1788         ! Clear Soft Reset Register
1789         ! This is needed to enable PCI if not booting from serial EPROM
1790         !-----------------------------------------------------------------------
1791                 */
1792         addi    r3, 0, 0x0
1793         mtdcr   CPC0_SRR, r3
1794
1795         addis    r3,0,0x0010
1796         mtctr   r3
1797 pci_wait:
1798         bdnz    pci_wait
1799
1800         blr                               /* return to main code */
1801
1802 /*
1803 !-----------------------------------------------------------------------------
1804 ! Function:     pll_write
1805 ! Description:  Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1806 !               That is:
1807 !                         1.  Pll is first disabled (de-activated by putting in bypass mode)
1808 !                         2.  PLL is reset
1809 !                         3.  Clock dividers are set while PLL is held in reset and bypassed
1810 !                         4.  PLL Reset is cleared
1811 !                         5.  Wait 100us for PLL to lock
1812 !                         6.  A core reset is performed
1813 ! Input: r3 = Value to write to CPC0_PLLMR0
1814 ! Input: r4 = Value to write to CPC0_PLLMR1
1815 ! Output r3 = none
1816 !-----------------------------------------------------------------------------
1817 */
1818 pll_write:
1819         mfdcr  r5, CPC0_UCR
1820         andis. r5,r5,0xFFFF
1821         ori    r5,r5,0x0101              /* Stop the UART clocks */
1822         mtdcr  CPC0_UCR,r5               /* Before changing PLL */
1823
1824         mfdcr  r5, CPC0_PLLMR1
1825         rlwinm r5,r5,0,0x7FFFFFFF        /* Disable PLL */
1826         mtdcr   CPC0_PLLMR1,r5
1827         oris   r5,r5,0x4000              /* Set PLL Reset */
1828         mtdcr   CPC0_PLLMR1,r5
1829
1830         mtdcr   CPC0_PLLMR0,r3           /* Set clock dividers */
1831         rlwinm r5,r4,0,0x3FFFFFFF        /* Reset & Bypass new PLL dividers */
1832         oris   r5,r5,0x4000              /* Set PLL Reset */
1833         mtdcr   CPC0_PLLMR1,r5           /* Set clock dividers */
1834         rlwinm r5,r5,0,0xBFFFFFFF        /* Clear PLL Reset */
1835         mtdcr   CPC0_PLLMR1,r5
1836
1837                 /*
1838         ! Wait min of 100us for PLL to lock.
1839         ! See CMOS 27E databook for more info.
1840         ! At 200MHz, that means waiting 20,000 instructions
1841                  */
1842         addi    r3,0,20000              /* 2000 = 0x4e20 */
1843         mtctr   r3
1844 pll_wait:
1845         bdnz    pll_wait
1846
1847         oris   r5,r5,0x8000             /* Enable PLL */
1848         mtdcr   CPC0_PLLMR1,r5          /* Engage */
1849
1850         /*
1851          * Reset CPU to guarantee timings are OK
1852          * Not sure if this is needed...
1853          */
1854         addis r3,0,0x1000
1855         mtspr dbcr0,r3               /* This will cause a CPU core reset, and */
1856                                      /* execution will continue from the poweron */
1857                                      /* vector of 0xfffffffc */
1858 #endif /* CONFIG_405EP */
1859
1860 #if defined(CONFIG_440)
1861 #define function_prolog(func_name)      .text; \
1862                                         .align 2; \
1863                                         .globl func_name; \
1864                                         func_name:
1865 #define function_epilog(func_name)      .type func_name,@function; \
1866                                         .size func_name,.-func_name
1867
1868 /*----------------------------------------------------------------------------+
1869 | mttlb3.
1870 +----------------------------------------------------------------------------*/
1871         function_prolog(mttlb3)
1872         TLBWE(4,3,2)
1873         blr
1874         function_epilog(mttlb3)
1875
1876 /*----------------------------------------------------------------------------+
1877 | mftlb3.
1878 +----------------------------------------------------------------------------*/
1879         function_prolog(mftlb3)
1880         TLBRE(3,3,2)
1881         blr
1882         function_epilog(mftlb3)
1883
1884 /*----------------------------------------------------------------------------+
1885 | mttlb2.
1886 +----------------------------------------------------------------------------*/
1887         function_prolog(mttlb2)
1888         TLBWE(4,3,1)
1889         blr
1890         function_epilog(mttlb2)
1891
1892 /*----------------------------------------------------------------------------+
1893 | mftlb2.
1894 +----------------------------------------------------------------------------*/
1895         function_prolog(mftlb2)
1896         TLBRE(3,3,1)
1897         blr
1898         function_epilog(mftlb2)
1899
1900 /*----------------------------------------------------------------------------+
1901 | mttlb1.
1902 +----------------------------------------------------------------------------*/
1903         function_prolog(mttlb1)
1904         TLBWE(4,3,0)
1905         blr
1906         function_epilog(mttlb1)
1907
1908 /*----------------------------------------------------------------------------+
1909 | mftlb1.
1910 +----------------------------------------------------------------------------*/
1911         function_prolog(mftlb1)
1912         TLBRE(3,3,0)
1913         blr
1914         function_epilog(mftlb1)
1915
1916 /*----------------------------------------------------------------------------+
1917 | dcbz_area.
1918 +----------------------------------------------------------------------------*/
1919         function_prolog(dcbz_area)
1920         rlwinm. r5,r4,0,27,31
1921         rlwinm  r5,r4,27,5,31
1922         beq     ..d_ra2
1923         addi    r5,r5,0x0001
1924 ..d_ra2:mtctr   r5
1925 ..d_ag2:dcbz    r0,r3
1926         addi    r3,r3,32
1927         bdnz    ..d_ag2
1928         sync
1929         blr
1930         function_epilog(dcbz_area)
1931
1932 /*----------------------------------------------------------------------------+
1933 | dflush.  Assume 32K at vector address is cachable.
1934 +----------------------------------------------------------------------------*/
1935         function_prolog(dflush)
1936         mfmsr   r9
1937         rlwinm  r8,r9,0,15,13
1938         rlwinm  r8,r8,0,17,15
1939         mtmsr   r8
1940         addi    r3,r0,0x0000
1941         mtspr   dvlim,r3
1942         mfspr   r3,ivpr
1943         addi    r4,r0,1024
1944         mtctr   r4
1945 ..dflush_loop:
1946         lwz     r6,0x0(r3)
1947         addi    r3,r3,32
1948         bdnz    ..dflush_loop
1949         addi    r3,r3,-32
1950         mtctr   r4
1951 ..ag:   dcbf    r0,r3
1952         addi    r3,r3,-32
1953         bdnz    ..ag
1954         sync
1955         mtmsr   r9
1956         blr
1957         function_epilog(dflush)
1958 #endif /* CONFIG_440 */