cpu/ppc4xx/start.S

   1 /*
   2  *  Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
   3  *  Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
   4  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
   5  *  Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25 /*------------------------------------------------------------------------------+ */
  26 /* */
  27 /*       This source code has been made available to you by IBM on an AS-IS */
  28 /*       basis.  Anyone receiving this source is licensed under IBM */
  29 /*       copyrights to use it in any way he or she deems fit, including */
  30 /*       copying it, modifying it, compiling it, and redistributing it either */
  31 /*       with or without modifications.  No license under IBM patents or */
  32 /*       patent applications is to be implied by the copyright license. */
  33 /* */
  34 /*       Any user of this software should understand that IBM cannot provide */
  35 /*       technical support for this software and will not be responsible for */
  36 /*       any consequences resulting from the use of this software. */
  37 /* */
  38 /*       Any person who transfers this source code or any derivative work */
  39 /*       must include the IBM copyright notice, this paragraph, and the */
  40 /*       preceding two paragraphs in the transferred software. */
  41 /* */
  42 /*       COPYRIGHT   I B M   CORPORATION 1995 */
  43 /*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
  44 /*------------------------------------------------------------------------------- */
  45
  46 /*  U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
  47  *
  48  *
  49  *  The processor starts at 0xfffffffc and the code is executed
  50  *  from flash/rom.
  51  *  in memory, but as long we don't jump around before relocating.
  52  *  board_init lies at a quite high address and when the cpu has
  53  *  jumped there, everything is ok.
  54  *  This works because the cpu gives the FLASH (CS0) the whole
  55  *  address space at startup, and board_init lies as a echo of
  56  *  the flash somewhere up there in the memorymap.
  57  *
  58  *  board_init will change CS0 to be positioned at the correct
  59  *  address and (s)dram will be positioned at address 0
  60  */
  61 #include <config.h>
  62 #include <mpc8xx.h>
  63 #include <ppc4xx.h>
  64 #include <version.h>
  65
  66 #define _LINUX_CONFIG_H 1       /* avoid reading Linux autoconf.h file  */
  67
  68 #include <ppc_asm.tmpl>
  69 #include <ppc_defs.h>
  70
  71 #include <asm/cache.h>
  72 #include <asm/mmu.h>
  73
  74 #ifndef  CONFIG_IDENT_STRING
  75 #define  CONFIG_IDENT_STRING ""
  76 #endif
  77
  78 #ifdef CFG_INIT_DCACHE_CS
  79 # if (CFG_INIT_DCACHE_CS == 0)
  80 #  define PBxAP pb0ap
  81 #  define PBxCR pb0cr
  82 # endif
  83 # if (CFG_INIT_DCACHE_CS == 1)
  84 #  define PBxAP pb1ap
  85 #  define PBxCR pb1cr
  86 # endif
  87 # if (CFG_INIT_DCACHE_CS == 2)
  88 #  define PBxAP pb2ap
  89 #  define PBxCR pb2cr
  90 # endif
  91 # if (CFG_INIT_DCACHE_CS == 3)
  92 #  define PBxAP pb3ap
  93 #  define PBxCR pb3cr
  94 # endif
  95 # if (CFG_INIT_DCACHE_CS == 4)
  96 #  define PBxAP pb4ap
  97 #  define PBxCR pb4cr
  98 # endif
  99 # if (CFG_INIT_DCACHE_CS == 5)
 100 #  define PBxAP pb5ap
 101 #  define PBxCR pb5cr
 102 # endif
 103 # if (CFG_INIT_DCACHE_CS == 6)
 104 #  define PBxAP pb6ap
 105 #  define PBxCR pb6cr
 106 # endif
 107 # if (CFG_INIT_DCACHE_CS == 7)
 108 #  define PBxAP pb7ap
 109 #  define PBxCR pb7cr
 110 # endif
 111 #endif /* CFG_INIT_DCACHE_CS */
 112
 113 #define function_prolog(func_name)      .text; \
 114                                         .align 2; \
 115                                         .globl func_name; \
 116                                         func_name:
 117 #define function_epilog(func_name)      .type func_name,@function; \
 118                                         .size func_name,.-func_name
 119
 120 /* We don't want the  MMU yet.
 121 */
 122 #undef  MSR_KERNEL
 123 #define MSR_KERNEL ( MSR_ME  )  /* Machine Check */
 124
 125
 126         .extern ext_bus_cntlr_init
 127         .extern sdram_init
 128 #ifdef CONFIG_NAND_U_BOOT
 129         .extern reconfig_tlb0
 130 #endif
 131
 132 /*
 133  * Set up GOT: Global Offset Table
 134  *
 135  * Use r14 to access the GOT
 136  */
 137 #if !defined(CONFIG_NAND_SPL)
 138         START_GOT
 139         GOT_ENTRY(_GOT2_TABLE_)
 140         GOT_ENTRY(_FIXUP_TABLE_)
 141
 142         GOT_ENTRY(_start)
 143         GOT_ENTRY(_start_of_vectors)
 144         GOT_ENTRY(_end_of_vectors)
 145         GOT_ENTRY(transfer_to_handler)
 146
 147         GOT_ENTRY(__init_end)
 148         GOT_ENTRY(_end)
 149         GOT_ENTRY(__bss_start)
 150         END_GOT
 151 #endif /* CONFIG_NAND_SPL */
 152
 153 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 154         /*
 155          * NAND U-Boot image is started from offset 0
 156          */
 157         .text
 158 #if defined(CONFIG_440)
 159         bl      reconfig_tlb0
 160 #endif
 161         GET_GOT
 162         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 163         bl      board_init_f
 164 #endif
 165
 166 /*
 167  * 440 Startup -- on reset only the top 4k of the effective
 168  * address space is mapped in by an entry in the instruction
 169  * and data shadow TLB. The .bootpg section is located in the
 170  * top 4k & does only what's necessary to map in the the rest
 171  * of the boot rom. Once the boot rom is mapped in we can
 172  * proceed with normal startup.
 173  *
 174  * NOTE: CS0 only covers the top 2MB of the effective address
 175  * space after reset.
 176  */
 177
 178 #if defined(CONFIG_440)
 179 #if !defined(CONFIG_NAND_SPL)
 180     .section .bootpg,"ax"
 181 #endif
 182     .globl _start_440
 183
 184 /**************************************************************************/
 185 _start_440:
 186         /*--------------------------------------------------------------------+
 187         | 440EPX BUP Change - Hardware team request
 188         +--------------------------------------------------------------------*/
 189 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 190         sync
 191         nop
 192         nop
 193 #endif
 194         /*----------------------------------------------------------------+
 195         | Core bug fix.  Clear the esr
 196         +-----------------------------------------------------------------*/
 197         li      r0,0
 198         mtspr   esr,r0
 199         /*----------------------------------------------------------------*/
 200         /* Clear and set up some registers. */
 201         /*----------------------------------------------------------------*/
 202         iccci   r0,r0           /* NOTE: operands not used for 440 */
 203         dccci   r0,r0           /* NOTE: operands not used for 440 */
 204         sync
 205         li      r0,0
 206         mtspr   srr0,r0
 207         mtspr   srr1,r0
 208         mtspr   csrr0,r0
 209         mtspr   csrr1,r0
 210         /* NOTE: 440GX adds machine check status regs */
 211 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
 212         mtspr   mcsrr0,r0
 213         mtspr   mcsrr1,r0
 214         mfspr   r1,mcsr
 215         mtspr   mcsr,r1
 216 #endif
 217
 218         /*----------------------------------------------------------------*/
 219         /* CCR0 init */
 220         /*----------------------------------------------------------------*/
 221         /* Disable store gathering & broadcast, guarantee inst/data
 222         * cache block touch, force load/store alignment
 223         * (see errata 1.12: 440_33)
 224         */
 225         lis     r1,0x0030       /* store gathering & broadcast disable */
 226         ori     r1,r1,0x6000    /* cache touch */
 227         mtspr   ccr0,r1
 228
 229         /*----------------------------------------------------------------*/
 230         /* Initialize debug */
 231         /*----------------------------------------------------------------*/
 232         mfspr   r1,dbcr0
 233         andis.  r1, r1, 0x8000  /* test DBCR0[EDM] bit                  */
 234         bne     skip_debug_init /* if set, don't clear debug register   */
 235         mtspr   dbcr0,r0
 236         mtspr   dbcr1,r0
 237         mtspr   dbcr2,r0
 238         mtspr   iac1,r0
 239         mtspr   iac2,r0
 240         mtspr   iac3,r0
 241         mtspr   dac1,r0
 242         mtspr   dac2,r0
 243         mtspr   dvc1,r0
 244         mtspr   dvc2,r0
 245
 246         mfspr   r1,dbsr
 247         mtspr   dbsr,r1         /* Clear all valid bits */
 248 skip_debug_init:
 249
 250 #if defined (CONFIG_440SPE)
 251         /*----------------------------------------------------------------+
 252         | Initialize Core Configuration Reg1.
 253         | a. ICDPEI: Record even parity. Normal operation.
 254         | b. ICTPEI: Record even parity. Normal operation.
 255         | c. DCTPEI: Record even parity. Normal operation.
 256         | d. DCDPEI: Record even parity. Normal operation.
 257         | e. DCUPEI: Record even parity. Normal operation.
 258         | f. DCMPEI: Record even parity. Normal operation.
 259         | g. FCOM:   Normal operation
 260         | h. MMUPEI: Record even parity. Normal operation.
 261         | i. FFF:    Flush only as much data as necessary.
 262         | j. TCS:    Timebase increments from CPU clock.
 263         +-----------------------------------------------------------------*/
 264         li      r0,0
 265         mtspr   ccr1, r0
 266
 267         /*----------------------------------------------------------------+
 268         | Reset the timebase.
 269         | The previous write to CCR1 sets the timebase source.
 270         +-----------------------------------------------------------------*/
 271         mtspr   tbl, r0
 272         mtspr   tbu, r0
 273 #endif
 274
 275         /*----------------------------------------------------------------*/
 276         /* Setup interrupt vectors */
 277         /*----------------------------------------------------------------*/
 278         mtspr   ivpr,r0         /* Vectors start at 0x0000_0000 */
 279         li      r1,0x0100
 280         mtspr   ivor0,r1        /* Critical input */
 281         li      r1,0x0200
 282         mtspr   ivor1,r1        /* Machine check */
 283         li      r1,0x0300
 284         mtspr   ivor2,r1        /* Data storage */
 285         li      r1,0x0400
 286         mtspr   ivor3,r1        /* Instruction storage */
 287         li      r1,0x0500
 288         mtspr   ivor4,r1        /* External interrupt */
 289         li      r1,0x0600
 290         mtspr   ivor5,r1        /* Alignment */
 291         li      r1,0x0700
 292         mtspr   ivor6,r1        /* Program check */
 293         li      r1,0x0800
 294         mtspr   ivor7,r1        /* Floating point unavailable */
 295         li      r1,0x0c00
 296         mtspr   ivor8,r1        /* System call */
 297         li      r1,0x0a00
 298         mtspr   ivor9,r1        /* Auxiliary Processor unavailable */
 299         li      r1,0x0900
 300         mtspr   ivor10,r1       /* Decrementer */
 301         li      r1,0x1300
 302         mtspr   ivor13,r1       /* Data TLB error */
 303         li      r1,0x1400
 304         mtspr   ivor14,r1       /* Instr TLB error */
 305         li      r1,0x2000
 306         mtspr   ivor15,r1       /* Debug */
 307
 308         /*----------------------------------------------------------------*/
 309         /* Configure cache regions  */
 310         /*----------------------------------------------------------------*/
 311         mtspr   inv0,r0
 312         mtspr   inv1,r0
 313         mtspr   inv2,r0
 314         mtspr   inv3,r0
 315         mtspr   dnv0,r0
 316         mtspr   dnv1,r0
 317         mtspr   dnv2,r0
 318         mtspr   dnv3,r0
 319         mtspr   itv0,r0
 320         mtspr   itv1,r0
 321         mtspr   itv2,r0
 322         mtspr   itv3,r0
 323         mtspr   dtv0,r0
 324         mtspr   dtv1,r0
 325         mtspr   dtv2,r0
 326         mtspr   dtv3,r0
 327
 328         /*----------------------------------------------------------------*/
 329         /* Cache victim limits */
 330         /*----------------------------------------------------------------*/
 331         /* floors 0, ceiling max to use the entire cache -- nothing locked
 332         */
 333         lis     r1,0x0001
 334         ori     r1,r1,0xf800
 335         mtspr   ivlim,r1
 336         mtspr   dvlim,r1
 337
 338         /*----------------------------------------------------------------+
 339         |Initialize MMUCR[STID] = 0.
 340         +-----------------------------------------------------------------*/
 341         mfspr   r0,mmucr
 342         addis   r1,0,0xFFFF
 343         ori     r1,r1,0xFF00
 344         and     r0,r0,r1
 345         mtspr   mmucr,r0
 346
 347         /*----------------------------------------------------------------*/
 348         /* Clear all TLB entries -- TID = 0, TS = 0 */
 349         /*----------------------------------------------------------------*/
 350         addis   r0,0,0x0000
 351         li      r1,0x003f       /* 64 TLB entries */
 352         mtctr   r1
 353 rsttlb: tlbwe   r0,r1,0x0000    /* Invalidate all entries (V=0)*/
 354         tlbwe   r0,r1,0x0001
 355         tlbwe   r0,r1,0x0002
 356         subi    r1,r1,0x0001
 357         bdnz    rsttlb
 358
 359         /*----------------------------------------------------------------*/
 360         /* TLB entry setup -- step thru tlbtab */
 361         /*----------------------------------------------------------------*/
 362 #if defined(CONFIG_440SPE)
 363         /*----------------------------------------------------------------*/
 364         /* We have different TLB tables for revA and rev B of 440SPe */
 365         /*----------------------------------------------------------------*/
 366         mfspr   r1, PVR
 367         lis     r0,0x5342
 368         ori     r0,r0,0x1891
 369         cmpw    r7,r1,r0
 370         bne     r7,..revA
 371         bl      tlbtabB
 372         b       ..goon
 373 ..revA:
 374         bl      tlbtabA
 375 ..goon:
 376 #else
 377         bl      tlbtab          /* Get tlbtab pointer */
 378 #endif
 379         mr      r5,r0
 380         li      r1,0x003f       /* 64 TLB entries max */
 381         mtctr   r1
 382         li      r4,0            /* TLB # */
 383
 384         addi    r5,r5,-4
 385 1:      lwzu    r0,4(r5)
 386         cmpwi   r0,0
 387         beq     2f              /* 0 marks end */
 388         lwzu    r1,4(r5)
 389         lwzu    r2,4(r5)
 390         tlbwe   r0,r4,0         /* TLB Word 0 */
 391         tlbwe   r1,r4,1         /* TLB Word 1 */
 392         tlbwe   r2,r4,2         /* TLB Word 2 */
 393         addi    r4,r4,1         /* Next TLB */
 394         bdnz    1b
 395
 396         /*----------------------------------------------------------------*/
 397         /* Continue from 'normal' start */
 398         /*----------------------------------------------------------------*/
 399 2:
 400
 401 #if defined(CONFIG_NAND_SPL)
 402 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 403         /*
 404          * Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
 405          */
 406         lis     r2,0x7fff
 407         ori     r2,r2,0xffff
 408         mfdcr   r1,isram0_dpc
 409         and     r1,r1,r2                /* Disable parity check */
 410         mtdcr   isram0_dpc,r1
 411         mfdcr   r1,isram0_pmeg
 412         and     r1,r1,r2                /* Disable pwr mgmt */
 413         mtdcr   isram0_pmeg,r1
 414 #endif
 415 #if defined(CONFIG_440EP)
 416         /*
 417          * On 440EP with no internal SRAM, we setup SDRAM very early
 418          * and copy the NAND_SPL to SDRAM and jump to it
 419          */
 420         /* Clear Dcache to use as RAM */
 421         addis   r3,r0,CFG_INIT_RAM_ADDR@h
 422         ori     r3,r3,CFG_INIT_RAM_ADDR@l
 423         addis   r4,r0,CFG_INIT_RAM_END@h
 424         ori     r4,r4,CFG_INIT_RAM_END@l
 425         rlwinm. r5,r4,0,27,31
 426         rlwinm  r5,r4,27,5,31
 427         beq     ..d_ran3
 428         addi    r5,r5,0x0001
 429 ..d_ran3:
 430         mtctr   r5
 431 ..d_ag3:
 432         dcbz    r0,r3
 433         addi    r3,r3,32
 434         bdnz    ..d_ag3
 435         /*----------------------------------------------------------------*/
 436         /* Setup the stack in internal SRAM */
 437         /*----------------------------------------------------------------*/
 438         lis     r1,CFG_INIT_RAM_ADDR@h
 439         ori     r1,r1,CFG_INIT_SP_OFFSET@l
 440         li      r0,0
 441         stwu    r0,-4(r1)
 442         stwu    r0,-4(r1)               /* Terminate call chain */
 443
 444         stwu    r1,-8(r1)               /* Save back chain and move SP */
 445         lis     r0,RESET_VECTOR@h       /* Address of reset vector */
 446         ori     r0,r0, RESET_VECTOR@l
 447         stwu    r1,-8(r1)               /* Save back chain and move SP */
 448         stw     r0,+12(r1)              /* Save return addr (underflow vect) */
 449         sync
 450         bl      early_sdram_init
 451         sync
 452 #endif /* CONFIG_440EP */
 453
 454         /*
 455          * Copy SPL from cache into internal SRAM
 456          */
 457         li      r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
 458         mtctr   r4
 459         lis     r2,CFG_NAND_BOOT_SPL_SRC@h
 460         ori     r2,r2,CFG_NAND_BOOT_SPL_SRC@l
 461         lis     r3,CFG_NAND_BOOT_SPL_DST@h
 462         ori     r3,r3,CFG_NAND_BOOT_SPL_DST@l
 463 spl_loop:
 464         lwzu    r4,4(r2)
 465         stwu    r4,4(r3)
 466         bdnz    spl_loop
 467
 468         /*
 469          * Jump to code in RAM
 470          */
 471         bl      00f
 472 00:     mflr    r10
 473         lis     r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
 474         ori     r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
 475         sub     r10,r10,r3
 476         addi    r10,r10,28
 477         mtlr    r10
 478         blr
 479
 480 start_ram:
 481         sync
 482         isync
 483 #endif /* CONFIG_NAND_SPL */
 484
 485         bl      3f
 486         b       _start
 487
 488 3:      li      r0,0
 489         mtspr   srr1,r0         /* Keep things disabled for now */
 490         mflr    r1
 491         mtspr   srr0,r1
 492         rfi
 493 #endif /* CONFIG_440 */
 494
 495 /*
 496  * r3 - 1st arg to board_init(): IMMP pointer
 497  * r4 - 2nd arg to board_init(): boot flag
 498  */
 499 #ifndef CONFIG_NAND_SPL
 500         .text
 501         .long   0x27051956              /* U-Boot Magic Number                  */
 502         .globl  version_string
 503 version_string:
 504         .ascii U_BOOT_VERSION
 505         .ascii " (", __DATE__, " - ", __TIME__, ")"
 506         .ascii CONFIG_IDENT_STRING, "\0"
 507
 508         . = EXC_OFF_SYS_RESET
 509         .globl  _start_of_vectors
 510 _start_of_vectors:
 511
 512 /* Critical input. */
 513         CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
 514
 515 #ifdef CONFIG_440
 516 /* Machine check */
 517         MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 518 #else
 519         CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 520 #endif /* CONFIG_440 */
 521
 522 /* Data Storage exception. */
 523         STD_EXCEPTION(0x300, DataStorage, UnknownException)
 524
 525 /* Instruction Storage exception. */
 526         STD_EXCEPTION(0x400, InstStorage, UnknownException)
 527
 528 /* External Interrupt exception. */
 529         STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 530
 531 /* Alignment exception. */
 532         . = 0x600
 533 Alignment:
 534         EXCEPTION_PROLOG(SRR0, SRR1)
 535         mfspr   r4,DAR
 536         stw     r4,_DAR(r21)
 537         mfspr   r5,DSISR
 538         stw     r5,_DSISR(r21)
 539         addi    r3,r1,STACK_FRAME_OVERHEAD
 540         li      r20,MSR_KERNEL
 541         rlwimi  r20,r23,0,16,16         /* copy EE bit from saved MSR */
 542         lwz     r6,GOT(transfer_to_handler)
 543         mtlr    r6
 544         blrl
 545 .L_Alignment:
 546         .long   AlignmentException - _start + _START_OFFSET
 547         .long   int_return - _start + _START_OFFSET
 548
 549 /* Program check exception */
 550         . = 0x700
 551 ProgramCheck:
 552         EXCEPTION_PROLOG(SRR0, SRR1)
 553         addi    r3,r1,STACK_FRAME_OVERHEAD
 554         li      r20,MSR_KERNEL
 555         rlwimi  r20,r23,0,16,16         /* copy EE bit from saved MSR */
 556         lwz     r6,GOT(transfer_to_handler)
 557         mtlr    r6
 558         blrl
 559 .L_ProgramCheck:
 560         .long   ProgramCheckException - _start + _START_OFFSET
 561         .long   int_return - _start + _START_OFFSET
 562
 563 #ifdef CONFIG_440
 564         STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 565         STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
 566         STD_EXCEPTION(0xa00, APU, UnknownException)
 567 #endif
 568         STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 569
 570 #ifdef CONFIG_440
 571         STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
 572         STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
 573 #else
 574         STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
 575         STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
 576         STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
 577 #endif
 578         CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
 579
 580         .globl  _end_of_vectors
 581 _end_of_vectors:
 582         . = _START_OFFSET
 583 #endif
 584         .globl  _start
 585 _start:
 586
 587 /*****************************************************************************/
 588 #if defined(CONFIG_440)
 589
 590         /*----------------------------------------------------------------*/
 591         /* Clear and set up some registers. */
 592         /*----------------------------------------------------------------*/
 593         li      r0,0x0000
 594         lis     r1,0xffff
 595         mtspr   dec,r0                  /* prevent dec exceptions */
 596         mtspr   tbl,r0                  /* prevent fit & wdt exceptions */
 597         mtspr   tbu,r0
 598         mtspr   tsr,r1                  /* clear all timer exception status */
 599         mtspr   tcr,r0                  /* disable all */
 600         mtspr   esr,r0                  /* clear exception syndrome register */
 601         mtxer   r0                      /* clear integer exception register */
 602
 603         /*----------------------------------------------------------------*/
 604         /* Debug setup -- some (not very good) ice's need an event*/
 605         /* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
 606         /* value you need in this case 0x8cff 0000 should do the trick */
 607         /*----------------------------------------------------------------*/
 608 #if defined(CFG_INIT_DBCR)
 609         lis     r1,0xffff
 610         ori     r1,r1,0xffff
 611         mtspr   dbsr,r1                 /* Clear all status bits */
 612         lis     r0,CFG_INIT_DBCR@h
 613         ori     r0,r0,CFG_INIT_DBCR@l
 614         mtspr   dbcr0,r0
 615         isync
 616 #endif
 617
 618         /*----------------------------------------------------------------*/
 619         /* Setup the internal SRAM */
 620         /*----------------------------------------------------------------*/
 621         li      r0,0
 622
 623 #ifdef CFG_INIT_RAM_DCACHE
 624         /* Clear Dcache to use as RAM */
 625         addis   r3,r0,CFG_INIT_RAM_ADDR@h
 626         ori     r3,r3,CFG_INIT_RAM_ADDR@l
 627         addis   r4,r0,CFG_INIT_RAM_END@h
 628         ori     r4,r4,CFG_INIT_RAM_END@l
 629         rlwinm. r5,r4,0,27,31
 630         rlwinm  r5,r4,27,5,31
 631         beq     ..d_ran
 632         addi    r5,r5,0x0001
 633 ..d_ran:
 634         mtctr   r5
 635 ..d_ag:
 636         dcbz    r0,r3
 637         addi    r3,r3,32
 638         bdnz    ..d_ag
 639 #endif /* CFG_INIT_RAM_DCACHE */
 640
 641         /* 440EP & 440GR are only 440er PPC's without internal SRAM */
 642 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
 643         /* not all PPC's have internal SRAM usable as L2-cache */
 644 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 645         mtdcr   l2_cache_cfg,r0         /* Ensure L2 Cache is off */
 646 #endif
 647
 648         lis     r2,0x7fff
 649         ori     r2,r2,0xffff
 650         mfdcr   r1,isram0_dpc
 651         and     r1,r1,r2                /* Disable parity check */
 652         mtdcr   isram0_dpc,r1
 653         mfdcr   r1,isram0_pmeg
 654         and     r1,r1,r2                /* Disable pwr mgmt */
 655         mtdcr   isram0_pmeg,r1
 656
 657         lis     r1,0x8000               /* BAS = 8000_0000 */
 658 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
 659         ori     r1,r1,0x0980            /* first 64k */
 660         mtdcr   isram0_sb0cr,r1
 661         lis     r1,0x8001
 662         ori     r1,r1,0x0980            /* second 64k */
 663         mtdcr   isram0_sb1cr,r1
 664         lis     r1, 0x8002
 665         ori     r1,r1, 0x0980           /* third 64k */
 666         mtdcr   isram0_sb2cr,r1
 667         lis     r1, 0x8003
 668         ori     r1,r1, 0x0980           /* fourth 64k */
 669         mtdcr   isram0_sb3cr,r1
 670 #elif defined(CONFIG_440SPE)
 671         lis     r1,0x0000               /* BAS = 0000_0000 */
 672         ori     r1,r1,0x0984            /* first 64k */
 673         mtdcr   isram0_sb0cr,r1
 674         lis     r1,0x0001
 675         ori     r1,r1,0x0984            /* second 64k */
 676         mtdcr   isram0_sb1cr,r1
 677         lis     r1, 0x0002
 678         ori     r1,r1, 0x0984           /* third 64k */
 679         mtdcr   isram0_sb2cr,r1
 680         lis     r1, 0x0003
 681         ori     r1,r1, 0x0984           /* fourth 64k */
 682         mtdcr   isram0_sb3cr,r1
 683 #elif defined(CONFIG_440GP)
 684         ori     r1,r1,0x0380            /* 8k rw */
 685         mtdcr   isram0_sb0cr,r1
 686         mtdcr   isram0_sb1cr,r0         /* Disable bank 1 */
 687 #endif
 688 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
 689
 690         /*----------------------------------------------------------------*/
 691         /* Setup the stack in internal SRAM */
 692         /*----------------------------------------------------------------*/
 693         lis     r1,CFG_INIT_RAM_ADDR@h
 694         ori     r1,r1,CFG_INIT_SP_OFFSET@l
 695         li      r0,0
 696         stwu    r0,-4(r1)
 697         stwu    r0,-4(r1)               /* Terminate call chain */
 698
 699         stwu    r1,-8(r1)               /* Save back chain and move SP */
 700         lis     r0,RESET_VECTOR@h       /* Address of reset vector */
 701         ori     r0,r0, RESET_VECTOR@l
 702         stwu    r1,-8(r1)               /* Save back chain and move SP */
 703         stw     r0,+12(r1)              /* Save return addr (underflow vect) */
 704
 705 #ifdef CONFIG_NAND_SPL
 706         bl      nand_boot               /* will not return */
 707 #else
 708         GET_GOT
 709
 710         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 711         bl      board_init_f
 712 #endif
 713
 714 #endif /* CONFIG_440 */
 715
 716 /*****************************************************************************/
 717 #ifdef CONFIG_IOP480
 718         /*----------------------------------------------------------------------- */
 719         /* Set up some machine state registers. */
 720         /*----------------------------------------------------------------------- */
 721         addi    r0,r0,0x0000            /* initialize r0 to zero */
 722         mtspr   esr,r0                  /* clear Exception Syndrome Reg */
 723         mttcr   r0                      /* timer control register */
 724         mtexier r0                      /* disable all interrupts */
 725         addis   r4,r0,0xFFFF            /* set r4 to 0xFFFFFFFF (status in the */
 726         ori     r4,r4,0xFFFF            /* dbsr is cleared by setting bits to 1) */
 727         mtdbsr  r4                      /* clear/reset the dbsr */
 728         mtexisr r4                      /* clear all pending interrupts */
 729         addis   r4,r0,0x8000
 730         mtexier r4                      /* enable critical exceptions */
 731         addis   r4,r0,0x0000            /* assume 403GCX - enable core clk */
 732         ori     r4,r4,0x4020            /* dbling (no harm done on GA and GC */
 733         mtiocr  r4                      /* since bit not used) & DRC to latch */
 734                                         /* data bus on rising edge of CAS */
 735         /*----------------------------------------------------------------------- */
 736         /* Clear XER. */
 737         /*----------------------------------------------------------------------- */
 738         mtxer   r0
 739         /*----------------------------------------------------------------------- */
 740         /* Invalidate i-cache and d-cache TAG arrays. */
 741         /*----------------------------------------------------------------------- */
 742         addi    r3,0,1024               /* 1/4 of I-cache size, half of D-cache */
 743         addi    r4,0,1024               /* 1/4 of I-cache */
 744 ..cloop:
 745         iccci   0,r3
 746         iccci   r4,r3
 747         dccci   0,r3
 748         addic.  r3,r3,-16               /* move back one cache line */
 749         bne     ..cloop                 /* loop back to do rest until r3 = 0 */
 750
 751         /* */
 752         /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
 753         /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
 754         /* */
 755
 756         /* first copy IOP480 register base address into r3 */
 757         addis   r3,0,0x5000             /* IOP480 register base address hi */
 758 /*      ori     r3,r3,0x0000            /  IOP480 register base address lo */
 759
 760 #ifdef CONFIG_ADCIOP
 761         /* use r4 as the working variable */
 762         /* turn on CS3 (LOCCTL.7) */
 763         lwz     r4,0x84(r3)             /* LOCTL is at offset 0x84 */
 764         andi.   r4,r4,0xff7f            /* make bit 7 = 0 -- CS3 mode */
 765         stw     r4,0x84(r3)             /* LOCTL is at offset 0x84 */
 766 #endif
 767
 768 #ifdef CONFIG_DASA_SIM
 769         /* use r4 as the working variable */
 770         /* turn on MA17 (LOCCTL.7) */
 771         lwz     r4,0x84(r3)             /* LOCTL is at offset 0x84 */
 772         ori     r4,r4,0x80              /* make bit 7 = 1 -- MA17 mode */
 773         stw     r4,0x84(r3)             /* LOCTL is at offset 0x84 */
 774 #endif
 775
 776         /* turn on MA16..13 (LCS0BRD.12 = 0) */
 777         lwz     r4,0x100(r3)            /* LCS0BRD is at offset 0x100 */
 778         andi.   r4,r4,0xefff            /* make bit 12 = 0 */
 779         stw     r4,0x100(r3)            /* LCS0BRD is at offset 0x100 */
 780
 781         /* make sure above stores all comlete before going on */
 782         sync
 783
 784         /* last thing, set local init status done bit (DEVINIT.31) */
 785         lwz     r4,0x80(r3)             /* DEVINIT is at offset 0x80 */
 786         oris    r4,r4,0x8000            /* make bit 31 = 1 */
 787         stw     r4,0x80(r3)             /* DEVINIT is at offset 0x80 */
 788
 789         /* clear all pending interrupts and disable all interrupts */
 790         li      r4,-1                   /* set p1 to 0xffffffff */
 791         stw     r4,0x1b0(r3)            /* clear all pending interrupts */
 792         stw     r4,0x1b8(r3)            /* clear all pending interrupts */
 793         li      r4,0                    /* set r4 to 0 */
 794         stw     r4,0x1b4(r3)            /* disable all interrupts */
 795         stw     r4,0x1bc(r3)            /* disable all interrupts */
 796
 797         /* make sure above stores all comlete before going on */
 798         sync
 799
 800         /*----------------------------------------------------------------------- */
 801         /* Enable two 128MB cachable regions. */
 802         /*----------------------------------------------------------------------- */
 803         addis   r1,r0,0x8000
 804         addi    r1,r1,0x0001
 805         mticcr  r1                      /* instruction cache */
 806
 807         addis   r1,r0,0x0000
 808         addi    r1,r1,0x0000
 809         mtdccr  r1                      /* data cache */
 810
 811         addis   r1,r0,CFG_INIT_RAM_ADDR@h
 812         ori     r1,r1,CFG_INIT_SP_OFFSET          /* set up the stack to SDRAM */
 813         li      r0, 0                   /* Make room for stack frame header and */
 814         stwu    r0, -4(r1)              /* clear final stack frame so that      */
 815         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
 816
 817         GET_GOT                 /* initialize GOT access                        */
 818
 819         bl      board_init_f    /* run first part of init code (from Flash)     */
 820
 821 #endif  /* CONFIG_IOP480 */
 822
 823 /*****************************************************************************/
 824 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
 825     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
 826     defined(CONFIG_405)
 827         /*----------------------------------------------------------------------- */
 828         /* Clear and set up some registers. */
 829         /*----------------------------------------------------------------------- */
 830         addi    r4,r0,0x0000
 831         mtspr   sgr,r4
 832         mtspr   dcwr,r4
 833         mtesr   r4                      /* clear Exception Syndrome Reg */
 834         mttcr   r4                      /* clear Timer Control Reg */
 835         mtxer   r4                      /* clear Fixed-Point Exception Reg */
 836         mtevpr  r4                      /* clear Exception Vector Prefix Reg */
 837         addi    r4,r0,(0xFFFF-0x10000)          /* set r4 to 0xFFFFFFFF (status in the */
 838                                         /* dbsr is cleared by setting bits to 1) */
 839         mtdbsr  r4                      /* clear/reset the dbsr */
 840
 841         /*----------------------------------------------------------------------- */
 842         /* Invalidate I and D caches. Enable I cache for defined memory regions */
 843         /* to speed things up. Leave the D cache disabled for now. It will be */
 844         /* enabled/left disabled later based on user selected menu options. */
 845         /* Be aware that the I cache may be disabled later based on the menu */
 846         /* options as well. See miscLib/main.c. */
 847         /*----------------------------------------------------------------------- */
 848         bl      invalidate_icache
 849         bl      invalidate_dcache
 850
 851         /*----------------------------------------------------------------------- */
 852         /* Enable two 128MB cachable regions. */
 853         /*----------------------------------------------------------------------- */
 854         lis     r4,0x8000
 855         ori     r4,r4,0x0001
 856         mticcr  r4                      /* instruction cache */
 857         isync
 858
 859         lis     r4,0x0000
 860         ori     r4,r4,0x0000
 861         mtdccr  r4                      /* data cache */
 862
 863 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
 864         /*----------------------------------------------------------------------- */
 865         /* Tune the speed and size for flash CS0  */
 866         /*----------------------------------------------------------------------- */
 867         bl      ext_bus_cntlr_init
 868 #endif
 869
 870 #if defined(CONFIG_405EP)
 871         /*----------------------------------------------------------------------- */
 872         /* DMA Status, clear to come up clean */
 873         /*----------------------------------------------------------------------- */
 874         addis   r3,r0, 0xFFFF         /* Clear all existing DMA status */
 875         ori     r3,r3, 0xFFFF
 876         mtdcr   dmasr, r3
 877
 878         bl      ppc405ep_init         /* do ppc405ep specific init */
 879 #endif /* CONFIG_405EP */
 880
 881 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
 882 #if defined(CONFIG_405EZ)
 883         /********************************************************************
 884          * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
 885          *******************************************************************/
 886         /*
 887          * We can map the OCM on the PLB3, so map it at
 888          * CFG_OCM_DATA_ADDR + 0x8000
 889          */
 890         lis     r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
 891         ori     r3,r3,CFG_OCM_DATA_ADDR@l
 892         ori     r3,r3,0x8270    /* 32K Offset, 16K for Bank 1, R/W/Enable */
 893         mtdcr   ocmplb3cr1,r3           /* Set PLB Access */
 894         ori     r3,r3,0x4000            /* Add 0x4000 for bank 2 */
 895         mtdcr   ocmplb3cr2,r3           /* Set PLB Access */
 896         isync
 897
 898         lis     r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
 899         ori     r3,r3,CFG_OCM_DATA_ADDR@l
 900         ori     r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
 901         mtdcr   ocmdscr1, r3            /* Set Data Side */
 902         mtdcr   ocmiscr1, r3            /* Set Instruction Side */
 903         ori     r3,r3,0x4000            /* Add 0x4000 for bank 2 */
 904         mtdcr   ocmdscr2, r3            /* Set Data Side */
 905         mtdcr   ocmiscr2, r3            /* Set Instruction Side */
 906         addis   r3,0,0x0800             /* OCM Data Parity Disable - 1 Wait State */
 907         mtdcr   ocmdsisdpc,r3
 908
 909         isync
 910 #else /* CONFIG_405EZ */
 911         /********************************************************************
 912          * Setup OCM - On Chip Memory
 913          *******************************************************************/
 914         /* Setup OCM */
 915         lis     r0, 0x7FFF
 916         ori     r0, r0, 0xFFFF
 917         mfdcr   r3, ocmiscntl           /* get instr-side IRAM config */
 918         mfdcr   r4, ocmdscntl           /* get data-side IRAM config */
 919         and     r3, r3, r0              /* disable data-side IRAM */
 920         and     r4, r4, r0              /* disable data-side IRAM */
 921         mtdcr   ocmiscntl, r3           /* set instr-side IRAM config */
 922         mtdcr   ocmdscntl, r4           /* set data-side IRAM config */
 923         isync
 924
 925         lis     r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
 926         ori     r3,r3,CFG_OCM_DATA_ADDR@l
 927         mtdcr   ocmdsarc, r3
 928         addis   r4, 0, 0xC000           /* OCM data area enabled */
 929         mtdcr   ocmdscntl, r4
 930         isync
 931 #endif /* CONFIG_405EZ */
 932 #endif
 933
 934 #ifdef CONFIG_NAND_SPL
 935         /*
 936          * Copy SPL from cache into internal SRAM
 937          */
 938         li      r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
 939         mtctr   r4
 940         lis     r2,CFG_NAND_BOOT_SPL_SRC@h
 941         ori     r2,r2,CFG_NAND_BOOT_SPL_SRC@l
 942         lis     r3,CFG_NAND_BOOT_SPL_DST@h
 943         ori     r3,r3,CFG_NAND_BOOT_SPL_DST@l
 944 spl_loop:
 945         lwzu    r4,4(r2)
 946         stwu    r4,4(r3)
 947         bdnz    spl_loop
 948
 949         /*
 950          * Jump to code in RAM
 951          */
 952         bl      00f
 953 00:     mflr    r10
 954         lis     r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
 955         ori     r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
 956         sub     r10,r10,r3
 957         addi    r10,r10,28
 958         mtlr    r10
 959         blr
 960
 961 start_ram:
 962         sync
 963         isync
 964 #endif /* CONFIG_NAND_SPL */
 965
 966         /*----------------------------------------------------------------------- */
 967         /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
 968         /*----------------------------------------------------------------------- */
 969 #ifdef CFG_INIT_DCACHE_CS
 970         /*----------------------------------------------------------------------- */
 971         /* Memory Bank x (nothingness) initialization 1GB+64MEG */
 972         /* used as temporary stack pointer for stage0  */
 973         /*----------------------------------------------------------------------- */
 974         li      r4,PBxAP
 975         mtdcr   ebccfga,r4
 976         lis     r4,0x0380
 977         ori     r4,r4,0x0480
 978         mtdcr   ebccfgd,r4
 979
 980         addi    r4,0,PBxCR
 981         mtdcr   ebccfga,r4
 982         lis     r4,0x400D
 983         ori     r4,r4,0xa000
 984         mtdcr   ebccfgd,r4
 985
 986         /* turn on data chache for this region */
 987         lis     r4,0x0080
 988         mtdccr  r4
 989
 990         /* set stack pointer and clear stack to known value */
 991
 992         lis     r1,CFG_INIT_RAM_ADDR@h
 993         ori     r1,r1,CFG_INIT_SP_OFFSET@l
 994
 995         li      r4,2048                 /* we store 2048 words to stack */
 996         mtctr   r4
 997
 998         lis     r2,CFG_INIT_RAM_ADDR@h          /* we also clear data area */
 999         ori     r2,r2,CFG_INIT_RAM_END@l        /* so cant copy value from r1 */
1000
1001         lis     r4,0xdead               /* we store 0xdeaddead in the stack */
1002         ori     r4,r4,0xdead
1003
1004 ..stackloop:
1005         stwu    r4,-4(r2)
1006         bdnz    ..stackloop
1007
1008         li      r0, 0                   /* Make room for stack frame header and */
1009         stwu    r0, -4(r1)              /* clear final stack frame so that      */
1010         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
1011         /*
1012          * Set up a dummy frame to store reset vector as return address.
1013          * this causes stack underflow to reset board.
1014          */
1015         stwu    r1, -8(r1)              /* Save back chain and move SP */
1016         addis   r0, 0, RESET_VECTOR@h   /* Address of reset vector */
1017         ori     r0, r0, RESET_VECTOR@l
1018         stwu    r1, -8(r1)              /* Save back chain and move SP */
1019         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
1020
1021 #elif defined(CFG_TEMP_STACK_OCM) && \
1022         (defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
1023         /*
1024          * Stack in OCM.
1025          */
1026
1027         /* Set up Stack at top of OCM */
1028         lis     r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
1029         ori     r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
1030
1031         /* Set up a zeroized stack frame so that backtrace works right */
1032         li      r0, 0
1033         stwu    r0, -4(r1)
1034         stwu    r0, -4(r1)
1035
1036         /*
1037          * Set up a dummy frame to store reset vector as return address.
1038          * this causes stack underflow to reset board.
1039          */
1040         stwu    r1, -8(r1)              /* Save back chain and move SP */
1041         lis     r0, RESET_VECTOR@h      /* Address of reset vector */
1042         ori     r0, r0, RESET_VECTOR@l
1043         stwu    r1, -8(r1)              /* Save back chain and move SP */
1044         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
1045 #endif /* CFG_INIT_DCACHE_CS */
1046
1047         /*----------------------------------------------------------------------- */
1048         /* Initialize SDRAM Controller  */
1049         /*----------------------------------------------------------------------- */
1050         bl      sdram_init
1051
1052         /*
1053          * Setup temporary stack pointer only for boards
1054          * that do not use SDRAM SPD I2C stuff since it
1055          * is already initialized to use DCACHE or OCM
1056          * stacks.
1057          */
1058 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
1059         lis     r1, CFG_INIT_RAM_ADDR@h
1060         ori     r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
1061
1062         li      r0, 0                   /* Make room for stack frame header and */
1063         stwu    r0, -4(r1)              /* clear final stack frame so that      */
1064         stwu    r0, -4(r1)              /* stack backtraces terminate cleanly   */
1065         /*
1066          * Set up a dummy frame to store reset vector as return address.
1067          * this causes stack underflow to reset board.
1068          */
1069         stwu    r1, -8(r1)              /* Save back chain and move SP */
1070         lis     r0, RESET_VECTOR@h      /* Address of reset vector */
1071         ori     r0, r0, RESET_VECTOR@l
1072         stwu    r1, -8(r1)              /* Save back chain and move SP */
1073         stw     r0, +12(r1)             /* Save return addr (underflow vect) */
1074 #endif /* !(CFG_INIT_DCACHE_CS  || !CFG_TEM_STACK_OCM) */
1075
1076 #ifdef CONFIG_NAND_SPL
1077         bl      nand_boot               /* will not return */
1078 #else
1079         GET_GOT                 /* initialize GOT access                        */
1080
1081         bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
1082
1083         /* NEVER RETURNS! */
1084         bl      board_init_f    /* run first part of init code (from Flash)     */
1085 #endif /* CONFIG_NAND_SPL */
1086
1087 #endif  /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
1088         /*----------------------------------------------------------------------- */
1089
1090
1091 #ifndef CONFIG_NAND_SPL
1092 /*
1093  * This code finishes saving the registers to the exception frame
1094  * and jumps to the appropriate handler for the exception.
1095  * Register r21 is pointer into trap frame, r1 has new stack pointer.
1096  */
1097         .globl  transfer_to_handler
1098 transfer_to_handler:
1099         stw     r22,_NIP(r21)
1100         lis     r22,MSR_POW@h
1101         andc    r23,r23,r22
1102         stw     r23,_MSR(r21)
1103         SAVE_GPR(7, r21)
1104         SAVE_4GPRS(8, r21)
1105         SAVE_8GPRS(12, r21)
1106         SAVE_8GPRS(24, r21)
1107         mflr    r23
1108         andi.   r24,r23,0x3f00          /* get vector offset */
1109         stw     r24,TRAP(r21)
1110         li      r22,0
1111         stw     r22,RESULT(r21)
1112         mtspr   SPRG2,r22               /* r1 is now kernel sp */
1113         lwz     r24,0(r23)              /* virtual address of handler */
1114         lwz     r23,4(r23)              /* where to go when done */
1115         mtspr   SRR0,r24
1116         mtspr   SRR1,r20
1117         mtlr    r23
1118         SYNC
1119         rfi                             /* jump to handler, enable MMU */
1120
1121 int_return:
1122         mfmsr   r28             /* Disable interrupts */
1123         li      r4,0
1124         ori     r4,r4,MSR_EE
1125         andc    r28,r28,r4
1126         SYNC                    /* Some chip revs need this... */
1127         mtmsr   r28
1128         SYNC
1129         lwz     r2,_CTR(r1)
1130         lwz     r0,_LINK(r1)
1131         mtctr   r2
1132         mtlr    r0
1133         lwz     r2,_XER(r1)
1134         lwz     r0,_CCR(r1)
1135         mtspr   XER,r2
1136         mtcrf   0xFF,r0
1137         REST_10GPRS(3, r1)
1138         REST_10GPRS(13, r1)
1139         REST_8GPRS(23, r1)
1140         REST_GPR(31, r1)
1141         lwz     r2,_NIP(r1)     /* Restore environment */
1142         lwz     r0,_MSR(r1)
1143         mtspr   SRR0,r2
1144         mtspr   SRR1,r0
1145         lwz     r0,GPR0(r1)
1146         lwz     r2,GPR2(r1)
1147         lwz     r1,GPR1(r1)
1148         SYNC
1149         rfi
1150
1151 crit_return:
1152         mfmsr   r28             /* Disable interrupts */
1153         li      r4,0
1154         ori     r4,r4,MSR_EE
1155         andc    r28,r28,r4
1156         SYNC                    /* Some chip revs need this... */
1157         mtmsr   r28
1158         SYNC
1159         lwz     r2,_CTR(r1)
1160         lwz     r0,_LINK(r1)
1161         mtctr   r2
1162         mtlr    r0
1163         lwz     r2,_XER(r1)
1164         lwz     r0,_CCR(r1)
1165         mtspr   XER,r2
1166         mtcrf   0xFF,r0
1167         REST_10GPRS(3, r1)
1168         REST_10GPRS(13, r1)
1169         REST_8GPRS(23, r1)
1170         REST_GPR(31, r1)
1171         lwz     r2,_NIP(r1)     /* Restore environment */
1172         lwz     r0,_MSR(r1)
1173         mtspr   csrr0,r2
1174         mtspr   csrr1,r0
1175         lwz     r0,GPR0(r1)
1176         lwz     r2,GPR2(r1)
1177         lwz     r1,GPR1(r1)
1178         SYNC
1179         rfci
1180
1181 #ifdef CONFIG_440
1182 mck_return:
1183         mfmsr   r28             /* Disable interrupts */
1184         li      r4,0
1185         ori     r4,r4,MSR_EE
1186         andc    r28,r28,r4
1187         SYNC                    /* Some chip revs need this... */
1188         mtmsr   r28
1189         SYNC
1190         lwz     r2,_CTR(r1)
1191         lwz     r0,_LINK(r1)
1192         mtctr   r2
1193         mtlr    r0
1194         lwz     r2,_XER(r1)
1195         lwz     r0,_CCR(r1)
1196         mtspr   XER,r2
1197         mtcrf   0xFF,r0
1198         REST_10GPRS(3, r1)
1199         REST_10GPRS(13, r1)
1200         REST_8GPRS(23, r1)
1201         REST_GPR(31, r1)
1202         lwz     r2,_NIP(r1)     /* Restore environment */
1203         lwz     r0,_MSR(r1)
1204         mtspr   mcsrr0,r2
1205         mtspr   mcsrr1,r0
1206         lwz     r0,GPR0(r1)
1207         lwz     r2,GPR2(r1)
1208         lwz     r1,GPR1(r1)
1209         SYNC
1210         rfmci
1211 #endif /* CONFIG_440 */
1212
1213
1214 /*
1215  * Cache functions.
1216  *
1217  * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
1218  * although for some cache-ralated calls stubs have to be provided to satisfy
1219  * symbols resolution.
1220  *
1221  */
1222 #ifdef CONFIG_440
1223        .globl  dcache_disable
1224 dcache_disable:
1225         blr
1226
1227         .globl  dcache_status
1228 dcache_status:
1229         blr
1230 #else
1231 flush_dcache:
1232         addis   r9,r0,0x0002            /* set mask for EE and CE msr bits */
1233         ori     r9,r9,0x8000
1234         mfmsr   r12                     /* save msr */
1235         andc    r9,r12,r9
1236         mtmsr   r9                      /* disable EE and CE */
1237         addi    r10,r0,0x0001           /* enable data cache for unused memory */
1238         mfdccr  r9                      /* region 0xF8000000-0xFFFFFFFF via */
1239         or      r10,r10,r9              /* bit 31 in dccr */
1240         mtdccr  r10
1241
1242         /* do loop for # of congruence classes. */
1243         lis     r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha       /* TBS: for large cache sizes */
1244         ori     r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1245         lis     r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */
1246         ori     r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */
1247         mtctr   r10
1248         addi    r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */
1249         add     r11,r10,r11             /* add to get to other side of cache line */
1250 ..flush_dcache_loop:
1251         lwz     r3,0(r10)               /* least recently used side */
1252         lwz     r3,0(r11)               /* the other side */
1253         dccci   r0,r11                  /* invalidate both sides */
1254         addi    r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
1255         addi    r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
1256         bdnz    ..flush_dcache_loop
1257         sync                            /* allow memory access to complete */
1258         mtdccr  r9                      /* restore dccr */
1259         mtmsr   r12                     /* restore msr */
1260         blr
1261
1262         .globl  icache_enable
1263 icache_enable:
1264         mflr    r8
1265         bl      invalidate_icache
1266         mtlr    r8
1267         isync
1268         addis   r3,r0, 0x8000         /* set bit 0 */
1269         mticcr  r3
1270         blr
1271
1272         .globl  icache_disable
1273 icache_disable:
1274         addis   r3,r0, 0x0000         /* clear bit 0 */
1275         mticcr  r3
1276         isync
1277         blr
1278
1279         .globl  icache_status
1280 icache_status:
1281         mficcr  r3
1282         srwi    r3, r3, 31      /* >>31 => select bit 0 */
1283         blr
1284
1285         .globl  dcache_enable
1286 dcache_enable:
1287         mflr    r8
1288         bl      invalidate_dcache
1289         mtlr    r8
1290         isync
1291         addis   r3,r0, 0x8000         /* set bit 0 */
1292         mtdccr  r3
1293         blr
1294
1295         .globl  dcache_disable
1296 dcache_disable:
1297         mflr    r8
1298         bl      flush_dcache
1299         mtlr    r8
1300         addis   r3,r0, 0x0000         /* clear bit 0 */
1301         mtdccr  r3
1302         blr
1303
1304         .globl  dcache_status
1305 dcache_status:
1306         mfdccr  r3
1307         srwi    r3, r3, 31      /* >>31 => select bit 0 */
1308         blr
1309 #endif
1310
1311         .globl get_pvr
1312 get_pvr:
1313         mfspr   r3, PVR
1314         blr
1315
1316 /*------------------------------------------------------------------------------- */
1317 /* Function:     out16 */
1318 /* Description:  Output 16 bits */
1319 /*------------------------------------------------------------------------------- */
1320         .globl  out16
1321 out16:
1322         sth     r4,0x0000(r3)
1323         blr
1324
1325 /*------------------------------------------------------------------------------- */
1326 /* Function:     out16r */
1327 /* Description:  Byte reverse and output 16 bits */
1328 /*------------------------------------------------------------------------------- */
1329         .globl  out16r
1330 out16r:
1331         sthbrx  r4,r0,r3
1332         blr
1333
1334 /*------------------------------------------------------------------------------- */
1335 /* Function:     out32r */
1336 /* Description:  Byte reverse and output 32 bits */
1337 /*------------------------------------------------------------------------------- */
1338         .globl  out32r
1339 out32r:
1340         stwbrx  r4,r0,r3
1341         blr
1342
1343 /*------------------------------------------------------------------------------- */
1344 /* Function:     in16 */
1345 /* Description:  Input 16 bits */
1346 /*------------------------------------------------------------------------------- */
1347         .globl  in16
1348 in16:
1349         lhz     r3,0x0000(r3)
1350         blr
1351
1352 /*------------------------------------------------------------------------------- */
1353 /* Function:     in16r */
1354 /* Description:  Input 16 bits and byte reverse */
1355 /*------------------------------------------------------------------------------- */
1356         .globl  in16r
1357 in16r:
1358         lhbrx   r3,r0,r3
1359         blr
1360
1361 /*------------------------------------------------------------------------------- */
1362 /* Function:     in32r */
1363 /* Description:  Input 32 bits and byte reverse */
1364 /*------------------------------------------------------------------------------- */
1365         .globl  in32r
1366 in32r:
1367         lwbrx   r3,r0,r3
1368         blr
1369
1370 /*------------------------------------------------------------------------------- */
1371 /* Function:     ppcDcbf */
1372 /* Description:  Data Cache block flush */
1373 /* Input:        r3 = effective address */
1374 /* Output:       none. */
1375 /*------------------------------------------------------------------------------- */
1376         .globl  ppcDcbf
1377 ppcDcbf:
1378         dcbf    r0,r3
1379         blr
1380
1381 /*------------------------------------------------------------------------------- */
1382 /* Function:     ppcDcbi */
1383 /* Description:  Data Cache block Invalidate */
1384 /* Input:        r3 = effective address */
1385 /* Output:       none. */
1386 /*------------------------------------------------------------------------------- */
1387         .globl  ppcDcbi
1388 ppcDcbi:
1389         dcbi    r0,r3
1390         blr
1391
1392 /*------------------------------------------------------------------------------- */
1393 /* Function:     ppcSync */
1394 /* Description:  Processor Synchronize */
1395 /* Input:        none. */
1396 /* Output:       none. */
1397 /*------------------------------------------------------------------------------- */
1398         .globl  ppcSync
1399 ppcSync:
1400         sync
1401         blr
1402
1403 /*
1404  * void relocate_code (addr_sp, gd, addr_moni)
1405  *
1406  * This "function" does not return, instead it continues in RAM
1407  * after relocating the monitor code.
1408  *
1409  * r3 = dest
1410  * r4 = src
1411  * r5 = length in bytes
1412  * r6 = cachelinesize
1413  */
1414         .globl  relocate_code
1415 relocate_code:
1416 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1417     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1418     defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1419         /*
1420          * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1421          * to speed up the boot process. Now this cache needs to be disabled.
1422          */
1423         iccci   0,0                     /* Invalidate inst cache */
1424         dccci   0,0                     /* Invalidate data cache, now no longer our stack */
1425         sync
1426         isync
1427         addi    r1,r0,0x0000            /* TLB entry #0 */
1428         tlbre   r0,r1,0x0002            /* Read contents */
1429         ori     r0,r0,0x0c00            /* Or in the inhibit, write through bit */
1430         tlbwe   r0,r1,0x0002            /* Save it out */
1431         sync
1432         isync
1433 #endif
1434         mr      r1,  r3         /* Set new stack pointer                */
1435         mr      r9,  r4         /* Save copy of Init Data pointer       */
1436         mr      r10, r5         /* Save copy of Destination Address     */
1437
1438         mr      r3,  r5                         /* Destination Address  */
1439         lis     r4, CFG_MONITOR_BASE@h          /* Source      Address  */
1440         ori     r4, r4, CFG_MONITOR_BASE@l
1441         lwz     r5, GOT(__init_end)
1442         sub     r5, r5, r4
1443         li      r6, CFG_CACHELINE_SIZE          /* Cache Line Size      */
1444
1445         /*
1446          * Fix GOT pointer:
1447          *
1448          * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
1449          *
1450          * Offset:
1451          */
1452         sub     r15, r10, r4
1453
1454         /* First our own GOT */
1455         add     r14, r14, r15
1456         /* the the one used by the C code */
1457         add     r30, r30, r15
1458
1459         /*
1460          * Now relocate code
1461          */
1462
1463         cmplw   cr1,r3,r4
1464         addi    r0,r5,3
1465         srwi.   r0,r0,2
1466         beq     cr1,4f          /* In place copy is not necessary       */
1467         beq     7f              /* Protect against 0 count              */
1468         mtctr   r0
1469         bge     cr1,2f
1470
1471         la      r8,-4(r4)
1472         la      r7,-4(r3)
1473 1:      lwzu    r0,4(r8)
1474         stwu    r0,4(r7)
1475         bdnz    1b
1476         b       4f
1477
1478 2:      slwi    r0,r0,2
1479         add     r8,r4,r0
1480         add     r7,r3,r0
1481 3:      lwzu    r0,-4(r8)
1482         stwu    r0,-4(r7)
1483         bdnz    3b
1484
1485 /*
1486  * Now flush the cache: note that we must start from a cache aligned
1487  * address. Otherwise we might miss one cache line.
1488  */
1489 4:      cmpwi   r6,0
1490         add     r5,r3,r5
1491         beq     7f              /* Always flush prefetch queue in any case */
1492         subi    r0,r6,1
1493         andc    r3,r3,r0
1494         mr      r4,r3
1495 5:      dcbst   0,r4
1496         add     r4,r4,r6
1497         cmplw   r4,r5
1498         blt     5b
1499         sync                    /* Wait for all dcbst to complete on bus */
1500         mr      r4,r3
1501 6:      icbi    0,r4
1502         add     r4,r4,r6
1503         cmplw   r4,r5
1504         blt     6b
1505 7:      sync                    /* Wait for all icbi to complete on bus */
1506         isync
1507
1508 /*
1509  * We are done. Do not return, instead branch to second part of board
1510  * initialization, now running from RAM.
1511  */
1512
1513         addi    r0, r10, in_ram - _start + _START_OFFSET
1514         mtlr    r0
1515         blr                             /* NEVER RETURNS! */
1516
1517 in_ram:
1518
1519         /*
1520          * Relocation Function, r14 point to got2+0x8000
1521          *
1522          * Adjust got2 pointers, no need to check for 0, this code
1523          * already puts a few entries in the table.
1524          */
1525         li      r0,__got2_entries@sectoff@l
1526         la      r3,GOT(_GOT2_TABLE_)
1527         lwz     r11,GOT(_GOT2_TABLE_)
1528         mtctr   r0
1529         sub     r11,r3,r11
1530         addi    r3,r3,-4
1531 1:      lwzu    r0,4(r3)
1532         add     r0,r0,r11
1533         stw     r0,0(r3)
1534         bdnz    1b
1535
1536         /*
1537          * Now adjust the fixups and the pointers to the fixups
1538          * in case we need to move ourselves again.
1539          */
1540 2:      li      r0,__fixup_entries@sectoff@l
1541         lwz     r3,GOT(_FIXUP_TABLE_)
1542         cmpwi   r0,0
1543         mtctr   r0
1544         addi    r3,r3,-4
1545         beq     4f
1546 3:      lwzu    r4,4(r3)
1547         lwzux   r0,r4,r11
1548         add     r0,r0,r11
1549         stw     r10,0(r3)
1550         stw     r0,0(r4)
1551         bdnz    3b
1552 4:
1553 clear_bss:
1554         /*
1555          * Now clear BSS segment
1556          */
1557         lwz     r3,GOT(__bss_start)
1558         lwz     r4,GOT(_end)
1559
1560         cmplw   0, r3, r4
1561         beq     6f
1562
1563         li      r0, 0
1564 5:
1565         stw     r0, 0(r3)
1566         addi    r3, r3, 4
1567         cmplw   0, r3, r4
1568         bne     5b
1569 6:
1570
1571         mr      r3, r9          /* Init Data pointer            */
1572         mr      r4, r10         /* Destination Address          */
1573         bl      board_init_r
1574
1575         /*
1576          * Copy exception vector code to low memory
1577          *
1578          * r3: dest_addr
1579          * r7: source address, r8: end address, r9: target address
1580          */
1581         .globl  trap_init
1582 trap_init:
1583         lwz     r7, GOT(_start_of_vectors)
1584         lwz     r8, GOT(_end_of_vectors)
1585
1586         li      r9, 0x100               /* reset vector always at 0x100 */
1587
1588         cmplw   0, r7, r8
1589         bgelr                           /* return if r7>=r8 - just in case */
1590
1591         mflr    r4                      /* save link register           */
1592 1:
1593         lwz     r0, 0(r7)
1594         stw     r0, 0(r9)
1595         addi    r7, r7, 4
1596         addi    r9, r9, 4
1597         cmplw   0, r7, r8
1598         bne     1b
1599
1600         /*
1601          * relocate `hdlr' and `int_return' entries
1602          */
1603         li      r7, .L_MachineCheck - _start + _START_OFFSET
1604         li      r8, Alignment - _start + _START_OFFSET
1605 2:
1606         bl      trap_reloc
1607         addi    r7, r7, 0x100           /* next exception vector */
1608         cmplw   0, r7, r8
1609         blt     2b
1610
1611         li      r7, .L_Alignment - _start + _START_OFFSET
1612         bl      trap_reloc
1613
1614         li      r7, .L_ProgramCheck - _start + _START_OFFSET
1615         bl      trap_reloc
1616
1617 #ifdef CONFIG_440
1618         li      r7, .L_FPUnavailable - _start + _START_OFFSET
1619         bl      trap_reloc
1620
1621         li      r7, .L_Decrementer - _start + _START_OFFSET
1622         bl      trap_reloc
1623
1624         li      r7, .L_APU - _start + _START_OFFSET
1625         bl      trap_reloc
1626
1627         li      r7, .L_InstructionTLBError - _start + _START_OFFSET
1628         bl      trap_reloc
1629
1630         li      r7, .L_DataTLBError - _start + _START_OFFSET
1631         bl      trap_reloc
1632 #else /* CONFIG_440 */
1633         li      r7, .L_PIT - _start + _START_OFFSET
1634         bl      trap_reloc
1635
1636         li      r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1637         bl      trap_reloc
1638
1639         li      r7, .L_DataTLBMiss - _start + _START_OFFSET
1640         bl      trap_reloc
1641 #endif /* CONFIG_440 */
1642
1643         li      r7, .L_DebugBreakpoint - _start + _START_OFFSET
1644         bl      trap_reloc
1645
1646 #if !defined(CONFIG_440)
1647         addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
1648         oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
1649         mtmsr   r7                      /* change MSR */
1650 #else
1651         bl      __440_msr_set
1652         b       __440_msr_continue
1653
1654 __440_msr_set:
1655         addi    r7,r0,0x1000            /* set ME bit (Machine Exceptions) */
1656         oris    r7,r7,0x0002            /* set CE bit (Critical Exceptions) */
1657         mtspr   srr1,r7
1658         mflr    r7
1659         mtspr   srr0,r7
1660         rfi
1661 __440_msr_continue:
1662 #endif
1663
1664         mtlr    r4                      /* restore link register        */
1665         blr
1666
1667         /*
1668          * Function: relocate entries for one exception vector
1669          */
1670 trap_reloc:
1671         lwz     r0, 0(r7)               /* hdlr ...                     */
1672         add     r0, r0, r3              /*  ... += dest_addr            */
1673         stw     r0, 0(r7)
1674
1675         lwz     r0, 4(r7)               /* int_return ...               */
1676         add     r0, r0, r3              /*  ... += dest_addr            */
1677         stw     r0, 4(r7)
1678
1679         blr
1680
1681 #if defined(CONFIG_440)
1682 /*----------------------------------------------------------------------------+
1683 | dcbz_area.
1684 +----------------------------------------------------------------------------*/
1685         function_prolog(dcbz_area)
1686         rlwinm. r5,r4,0,27,31
1687         rlwinm  r5,r4,27,5,31
1688         beq     ..d_ra2
1689         addi    r5,r5,0x0001
1690 ..d_ra2:mtctr   r5
1691 ..d_ag2:dcbz    r0,r3
1692         addi    r3,r3,32
1693         bdnz    ..d_ag2
1694         sync
1695         blr
1696         function_epilog(dcbz_area)
1697
1698 /*----------------------------------------------------------------------------+
1699 | dflush.  Assume 32K at vector address is cachable.
1700 +----------------------------------------------------------------------------*/
1701         function_prolog(dflush)
1702         mfmsr   r9
1703         rlwinm  r8,r9,0,15,13
1704         rlwinm  r8,r8,0,17,15
1705         mtmsr   r8
1706         addi    r3,r0,0x0000
1707         mtspr   dvlim,r3
1708         mfspr   r3,ivpr
1709         addi    r4,r0,1024
1710         mtctr   r4
1711 ..dflush_loop:
1712         lwz     r6,0x0(r3)
1713         addi    r3,r3,32
1714         bdnz    ..dflush_loop
1715         addi    r3,r3,-32
1716         mtctr   r4
1717 ..ag:   dcbf    r0,r3
1718         addi    r3,r3,-32
1719         bdnz    ..ag
1720         sync
1721         mtmsr   r9
1722         blr
1723         function_epilog(dflush)
1724 #endif /* CONFIG_440 */
1725 #endif /* CONFIG_NAND_SPL */
1726
1727 /*------------------------------------------------------------------------------- */
1728 /* Function:     in8 */
1729 /* Description:  Input 8 bits */
1730 /*------------------------------------------------------------------------------- */
1731         .globl  in8
1732 in8:
1733         lbz     r3,0x0000(r3)
1734         blr
1735
1736 /*------------------------------------------------------------------------------- */
1737 /* Function:     out8 */
1738 /* Description:  Output 8 bits */
1739 /*------------------------------------------------------------------------------- */
1740         .globl  out8
1741 out8:
1742         stb     r4,0x0000(r3)
1743         blr
1744
1745 /*------------------------------------------------------------------------------- */
1746 /* Function:     out32 */
1747 /* Description:  Output 32 bits */
1748 /*------------------------------------------------------------------------------- */
1749         .globl  out32
1750 out32:
1751         stw     r4,0x0000(r3)
1752         blr
1753
1754 /*------------------------------------------------------------------------------- */
1755 /* Function:     in32 */
1756 /* Description:  Input 32 bits */
1757 /*------------------------------------------------------------------------------- */
1758         .globl  in32
1759 in32:
1760         lwz     3,0x0000(3)
1761         blr
1762
1763 invalidate_icache:
1764         iccci   r0,r0                   /* for 405, iccci invalidates the */
1765         blr                             /*   entire I cache */
1766
1767 invalidate_dcache:
1768         addi    r6,0,0x0000             /* clear GPR 6 */
1769         /* Do loop for # of dcache congruence classes. */
1770         lis     r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha       /* TBS for large sized cache */
1771         ori     r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
1772                                         /* NOTE: dccci invalidates both */
1773         mtctr   r7                      /* ways in the D cache */
1774 ..dcloop:
1775         dccci   0,r6                    /* invalidate line */
1776         addi    r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
1777         bdnz    ..dcloop
1778         blr
1779
1780 /**************************************************************************/
1781 /* PPC405EP specific stuff                                                */
1782 /**************************************************************************/
1783 #ifdef CONFIG_405EP
1784 ppc405ep_init:
1785
1786 #ifdef CONFIG_BUBINGA
1787         /*
1788          * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1789          * function) to support FPGA and NVRAM accesses below.
1790          */
1791
1792         lis     r3,GPIO0_OSRH@h         /* config GPIO output select */
1793         ori     r3,r3,GPIO0_OSRH@l
1794         lis     r4,CFG_GPIO0_OSRH@h
1795         ori     r4,r4,CFG_GPIO0_OSRH@l
1796         stw     r4,0(r3)
1797         lis     r3,GPIO0_OSRL@h
1798         ori     r3,r3,GPIO0_OSRL@l
1799         lis     r4,CFG_GPIO0_OSRL@h
1800         ori     r4,r4,CFG_GPIO0_OSRL@l
1801         stw     r4,0(r3)
1802
1803         lis     r3,GPIO0_ISR1H@h        /* config GPIO input select */
1804         ori     r3,r3,GPIO0_ISR1H@l
1805         lis     r4,CFG_GPIO0_ISR1H@h
1806         ori     r4,r4,CFG_GPIO0_ISR1H@l
1807         stw     r4,0(r3)
1808         lis     r3,GPIO0_ISR1L@h
1809         ori     r3,r3,GPIO0_ISR1L@l
1810         lis     r4,CFG_GPIO0_ISR1L@h
1811         ori     r4,r4,CFG_GPIO0_ISR1L@l
1812         stw     r4,0(r3)
1813
1814         lis     r3,GPIO0_TSRH@h         /* config GPIO three-state select */
1815         ori     r3,r3,GPIO0_TSRH@l
1816         lis     r4,CFG_GPIO0_TSRH@h
1817         ori     r4,r4,CFG_GPIO0_TSRH@l
1818         stw     r4,0(r3)
1819         lis     r3,GPIO0_TSRL@h
1820         ori     r3,r3,GPIO0_TSRL@l
1821         lis     r4,CFG_GPIO0_TSRL@h
1822         ori     r4,r4,CFG_GPIO0_TSRL@l
1823         stw     r4,0(r3)
1824
1825         lis     r3,GPIO0_TCR@h          /* config GPIO driver output enables */
1826         ori     r3,r3,GPIO0_TCR@l
1827         lis     r4,CFG_GPIO0_TCR@h
1828         ori     r4,r4,CFG_GPIO0_TCR@l
1829         stw     r4,0(r3)
1830
1831         li      r3,pb1ap                /* program EBC bank 1 for RTC access */
1832         mtdcr   ebccfga,r3
1833         lis     r3,CFG_EBC_PB1AP@h
1834         ori     r3,r3,CFG_EBC_PB1AP@l
1835         mtdcr   ebccfgd,r3
1836         li      r3,pb1cr
1837         mtdcr   ebccfga,r3
1838         lis     r3,CFG_EBC_PB1CR@h
1839         ori     r3,r3,CFG_EBC_PB1CR@l
1840         mtdcr   ebccfgd,r3
1841
1842         li      r3,pb1ap                /* program EBC bank 1 for RTC access */
1843         mtdcr   ebccfga,r3
1844         lis     r3,CFG_EBC_PB1AP@h
1845         ori     r3,r3,CFG_EBC_PB1AP@l
1846         mtdcr   ebccfgd,r3
1847         li      r3,pb1cr
1848         mtdcr   ebccfga,r3
1849         lis     r3,CFG_EBC_PB1CR@h
1850         ori     r3,r3,CFG_EBC_PB1CR@l
1851         mtdcr   ebccfgd,r3
1852
1853         li      r3,pb4ap                /* program EBC bank 4 for FPGA access */
1854         mtdcr   ebccfga,r3
1855         lis     r3,CFG_EBC_PB4AP@h
1856         ori     r3,r3,CFG_EBC_PB4AP@l
1857         mtdcr   ebccfgd,r3
1858         li      r3,pb4cr
1859         mtdcr   ebccfga,r3
1860         lis     r3,CFG_EBC_PB4CR@h
1861         ori     r3,r3,CFG_EBC_PB4CR@l
1862         mtdcr   ebccfgd,r3
1863 #endif
1864
1865 #ifndef CFG_CPC0_PCI
1866         li      r3,CPC0_PCI_HOST_CFG_EN
1867 #ifdef CONFIG_BUBINGA
1868         /*
1869         !-----------------------------------------------------------------------
1870         ! Check FPGA for PCI internal/external arbitration
1871         !   If board is set to internal arbitration, update cpc0_pci
1872         !-----------------------------------------------------------------------
1873         */
1874         addis   r5,r0,FPGA_REG1@h      /* set offset for FPGA_REG1 */
1875         ori     r5,r5,FPGA_REG1@l
1876         lbz     r5,0x0(r5)              /* read to get PCI arb selection */
1877         andi.   r6,r5,FPGA_REG1_PCI_INT_ARB  /* using internal arbiter ?*/
1878         beq     ..pci_cfg_set             /* if not set, then bypass reg write*/
1879 #endif
1880         ori     r3,r3,CPC0_PCI_ARBIT_EN
1881 #else /* CFG_CPC0_PCI */
1882         li      r3,CFG_CPC0_PCI
1883 #endif /* CFG_CPC0_PCI */
1884 ..pci_cfg_set:
1885         mtdcr   CPC0_PCI, r3             /* Enable internal arbiter*/
1886
1887         /*
1888         !-----------------------------------------------------------------------
1889         ! Check to see if chip is in bypass mode.
1890         ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1891         ! CPU reset   Otherwise, skip this step and keep going.
1892         ! Note:  Running BIOS in bypass mode is not supported since PLB speed
1893         !        will not be fast enough for the SDRAM (min 66MHz)
1894         !-----------------------------------------------------------------------
1895         */
1896         mfdcr   r5, CPC0_PLLMR1
1897         rlwinm  r4,r5,1,0x1            /* get system clock source (SSCS) */
1898         cmpi    cr0,0,r4,0x1
1899
1900         beq    pll_done                   /* if SSCS =b'1' then PLL has */
1901                                           /* already been set */
1902                                           /* and CPU has been reset */
1903                                           /* so skip to next section */
1904
1905 #ifdef CONFIG_BUBINGA
1906         /*
1907         !-----------------------------------------------------------------------
1908         ! Read NVRAM to get value to write in PLLMR.
1909         ! If value has not been correctly saved, write default value
1910         ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1911         ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1912         !
1913         ! WARNING:  This code assumes the first three words in the nvram_t
1914         !           structure in openbios.h.  Changing the beginning of
1915         !           the structure will break this code.
1916         !
1917         !-----------------------------------------------------------------------
1918         */
1919         addis   r3,0,NVRAM_BASE@h
1920         addi    r3,r3,NVRAM_BASE@l
1921
1922         lwz     r4, 0(r3)
1923         addis   r5,0,NVRVFY1@h
1924         addi    r5,r5,NVRVFY1@l
1925         cmp     cr0,0,r4,r5            /* Compare 1st NVRAM Magic number*/
1926         bne     ..no_pllset
1927         addi    r3,r3,4
1928         lwz     r4, 0(r3)
1929         addis   r5,0,NVRVFY2@h
1930         addi    r5,r5,NVRVFY2@l
1931         cmp     cr0,0,r4,r5            /* Compare 2 NVRAM Magic number */
1932         bne     ..no_pllset
1933         addi    r3,r3,8                 /* Skip over conf_size */
1934         lwz     r4, 4(r3)               /* Load PLLMR1 value from NVRAM */
1935         lwz     r3, 0(r3)               /* Load PLLMR0 value from NVRAM */
1936         rlwinm  r5,r4,1,0x1             /* get system clock source (SSCS) */
1937         cmpi     cr0,0,r5,1             /* See if PLL is locked */
1938         beq     pll_write
1939 ..no_pllset:
1940 #endif /* CONFIG_BUBINGA */
1941
1942         addis   r3,0,PLLMR0_DEFAULT@h       /* PLLMR0 default value */
1943         ori     r3,r3,PLLMR0_DEFAULT@l     /* */
1944         addis   r4,0,PLLMR1_DEFAULT@h       /* PLLMR1 default value */
1945         ori     r4,r4,PLLMR1_DEFAULT@l     /* */
1946
1947         b       pll_write                 /* Write the CPC0_PLLMR with new value */
1948
1949 pll_done:
1950         /*
1951         !-----------------------------------------------------------------------
1952         ! Clear Soft Reset Register
1953         ! This is needed to enable PCI if not booting from serial EPROM
1954         !-----------------------------------------------------------------------
1955                 */
1956         addi    r3, 0, 0x0
1957         mtdcr   CPC0_SRR, r3
1958
1959         addis    r3,0,0x0010
1960         mtctr   r3
1961 pci_wait:
1962         bdnz    pci_wait
1963
1964         blr                               /* return to main code */
1965
1966 /*
1967 !-----------------------------------------------------------------------------
1968 ! Function:     pll_write
1969 ! Description:  Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1970 !               That is:
1971 !                         1.  Pll is first disabled (de-activated by putting in bypass mode)
1972 !                         2.  PLL is reset
1973 !                         3.  Clock dividers are set while PLL is held in reset and bypassed
1974 !                         4.  PLL Reset is cleared
1975 !                         5.  Wait 100us for PLL to lock
1976 !                         6.  A core reset is performed
1977 ! Input: r3 = Value to write to CPC0_PLLMR0
1978 ! Input: r4 = Value to write to CPC0_PLLMR1
1979 ! Output r3 = none
1980 !-----------------------------------------------------------------------------
1981 */
1982 pll_write:
1983         mfdcr  r5, CPC0_UCR
1984         andis. r5,r5,0xFFFF
1985         ori    r5,r5,0x0101              /* Stop the UART clocks */
1986         mtdcr  CPC0_UCR,r5               /* Before changing PLL */
1987
1988         mfdcr  r5, CPC0_PLLMR1
1989         rlwinm r5,r5,0,0x7FFFFFFF        /* Disable PLL */
1990         mtdcr   CPC0_PLLMR1,r5
1991         oris   r5,r5,0x4000              /* Set PLL Reset */
1992         mtdcr   CPC0_PLLMR1,r5
1993
1994         mtdcr   CPC0_PLLMR0,r3           /* Set clock dividers */
1995         rlwinm r5,r4,0,0x3FFFFFFF        /* Reset & Bypass new PLL dividers */
1996         oris   r5,r5,0x4000              /* Set PLL Reset */
1997         mtdcr   CPC0_PLLMR1,r5           /* Set clock dividers */
1998         rlwinm r5,r5,0,0xBFFFFFFF        /* Clear PLL Reset */
1999         mtdcr   CPC0_PLLMR1,r5
2000
2001                 /*
2002         ! Wait min of 100us for PLL to lock.
2003         ! See CMOS 27E databook for more info.
2004         ! At 200MHz, that means waiting 20,000 instructions
2005                  */
2006         addi    r3,0,20000              /* 2000 = 0x4e20 */
2007         mtctr   r3
2008 pll_wait:
2009         bdnz    pll_wait
2010
2011         oris   r5,r5,0x8000             /* Enable PLL */
2012         mtdcr   CPC0_PLLMR1,r5          /* Engage */
2013
2014         /*
2015          * Reset CPU to guarantee timings are OK
2016          * Not sure if this is needed...
2017          */
2018         addis r3,0,0x1000
2019         mtspr dbcr0,r3               /* This will cause a CPU core reset, and */
2020                                      /* execution will continue from the poweron */
2021                                      /* vector of 0xfffffffc */
2022 #endif /* CONFIG_405EP */
2023
2024 #if defined(CONFIG_440)
2025 /*----------------------------------------------------------------------------+
2026 | mttlb3.
2027 +----------------------------------------------------------------------------*/
2028         function_prolog(mttlb3)
2029         TLBWE(4,3,2)
2030         blr
2031         function_epilog(mttlb3)
2032
2033 /*----------------------------------------------------------------------------+
2034 | mftlb3.
2035 +----------------------------------------------------------------------------*/
2036         function_prolog(mftlb3)
2037         TLBRE(3,3,2)
2038         blr
2039         function_epilog(mftlb3)
2040
2041 /*----------------------------------------------------------------------------+
2042 | mttlb2.
2043 +----------------------------------------------------------------------------*/
2044         function_prolog(mttlb2)
2045         TLBWE(4,3,1)
2046         blr
2047         function_epilog(mttlb2)
2048
2049 /*----------------------------------------------------------------------------+
2050 | mftlb2.
2051 +----------------------------------------------------------------------------*/
2052         function_prolog(mftlb2)
2053         TLBRE(3,3,1)
2054         blr
2055         function_epilog(mftlb2)
2056
2057 /*----------------------------------------------------------------------------+
2058 | mttlb1.
2059 +----------------------------------------------------------------------------*/
2060         function_prolog(mttlb1)
2061         TLBWE(4,3,0)
2062         blr
2063         function_epilog(mttlb1)
2064
2065 /*----------------------------------------------------------------------------+
2066 | mftlb1.
2067 +----------------------------------------------------------------------------*/
2068         function_prolog(mftlb1)
2069         TLBRE(3,3,0)
2070         blr
2071         function_epilog(mftlb1)
2072 #endif /* CONFIG_440 */