doc/README.fsl-ddr

   1 Table of interleaving 2-4 controllers
   2 =====================================
   3   +--------------+-----------------------------------------------------------+
   4   |Configuration |                    Memory Controller                      |
   5   |              |       1              2              3             4       |
   6   |--------------+--------------+--------------+-----------------------------+
   7   | Two memory   | Not Intlv'ed | Not Intlv'ed |                             |
   8   | complexes    +--------------+--------------+                             |
   9   |              |      2-way Intlv'ed         |                             |
  10   |--------------+--------------+--------------+--------------+              |
  11   |              | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |              |
  12   | Three memory +--------------+--------------+--------------+              |
  13   | complexes    |         2-way Intlv'ed      | Not Intlv'ed |              |
  14   |              +-----------------------------+--------------+              |
  15   |              |                  3-way Intlv'ed            |              |
  16   +--------------+--------------+--------------+--------------+--------------+
  17   |              | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |
  18   | Four memory  +--------------+--------------+--------------+--------------+
  19   | complexes    |       2-way Intlv'ed        |       2-way Intlv'ed        |
  20   |              +-----------------------------+-----------------------------+
  21   |              |                      4-way Intlv'ed                       |
  22   +--------------+-----------------------------------------------------------+
  23
  24
  25 Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
  26 ======================================================
  27   +-------------+---------------------------------------------------------+
  28   |             |                   Rank Interleaving                     |
  29   |             +--------+-----------+-----------+------------+-----------+
  30   |Memory       |        |           |           |    2x2     |    4x1    |
  31   |Controller   |  None  | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
  32   |Interleaving |        | {CS0+CS1} | {CS2+CS3} | {CS2+CS3}  |  CS2+CS3} |
  33   +-------------+--------+-----------+-----------+------------+-----------+
  34   |None         |  Yes   | Yes       | Yes       | Yes        | Yes       |
  35   +-------------+--------+-----------+-----------+------------+-----------+
  36   |Cacheline    |  Yes   | Yes       | No        | No, Only(*)| Yes       |
  37   |             |CS0 Only|           |           | {CS0+CS1}  |           |
  38   +-------------+--------+-----------+-----------+------------+-----------+
  39   |Page         |  Yes   | Yes       | No        | No, Only(*)| Yes       |
  40   |             |CS0 Only|           |           | {CS0+CS1}  |           |
  41   +-------------+--------+-----------+-----------+------------+-----------+
  42   |Bank         |  Yes   | Yes       | No        | No, Only(*)| Yes       |
  43   |             |CS0 Only|           |           | {CS0+CS1}  |           |
  44   +-------------+--------+-----------+-----------+------------+-----------+
  45   |Superbank    |  No    | Yes       | No        | No, Only(*)| Yes       |
  46   |             |        |           |           | {CS0+CS1}  |           |
  47   +-------------+--------+-----------+-----------+------------+-----------+
  48  (*) Although the hardware can be configured with memory controller
  49  interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
  50  from each controller. {CS2+CS3} on each controller are only rank
  51  interleaved on that controller.
  52
  53  For memory controller interleaving, identical DIMMs are suggested. Software
  54  doesn't check the size or organization of interleaved DIMMs.
  55
  56 The ways to configure the ddr interleaving mode
  57 ==============================================
  58 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
  59    under "CONFIG_EXTRA_ENV_SETTINGS", like:
  60         #define CONFIG_EXTRA_ENV_SETTINGS                               \
  61          "hwconfig=fsl_ddr:ctlr_intlv=bank"                     \
  62          ......
  63
  64 2. Run u-boot "setenv" command to configure the memory interleaving mode.
  65    Either numerical or string value is accepted.
  66
  67   # disable memory controller interleaving
  68   setenv hwconfig "fsl_ddr:ctlr_intlv=null"
  69
  70   # cacheline interleaving
  71   setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
  72
  73   # page interleaving
  74   setenv hwconfig "fsl_ddr:ctlr_intlv=page"
  75
  76   # bank interleaving
  77   setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
  78
  79   # superbank
  80   setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
  81
  82   # 1KB 3-way interleaving
  83   setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
  84
  85   # 4KB 3-way interleaving
  86   setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
  87
  88   # 8KB 3-way interleaving
  89   setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
  90
  91   # disable bank (chip-select) interleaving
  92   setenv hwconfig "fsl_ddr:bank_intlv=null"
  93
  94   # bank(chip-select) interleaving cs0+cs1
  95   setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
  96
  97   # bank(chip-select) interleaving cs2+cs3
  98   setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
  99
 100   # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3)  (2x2)
 101   setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
 102
 103   # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
 104   setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
 105
 106   # bank(chip-select) interleaving (auto)
 107   setenv hwconfig "fsl_ddr:bank_intlv=auto"
 108   This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
 109   on DIMMs.
 110
 111 Memory controller address hashing
 112 ==================================
 113 If the DDR controller supports address hashing, it can be enabled by hwconfig.
 114
 115 Syntax is:
 116 hwconfig=fsl_ddr:addr_hash=true
 117
 118 Memory controller ECC on/off
 119 ============================
 120 If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
 121 ECC can be turned on/off by hwconfig.
 122
 123 Syntax is
 124 hwconfig=fsl_ddr:ecc=off
 125
 126 Memory testing options for mpc85xx
 127 ==================================
 128 1. Memory test can be done once U-boot prompt comes up using mtest, or
 129 2. Memory test can be done with Power-On-Self-Test function, activated at
 130    compile time.
 131
 132    In order to enable the POST memory test, CONFIG_POST needs to be
 133    defined in board configuraiton header file. By default, POST memory test
 134    performs a fast test. A slow test can be enabled by changing the flag at
 135    compiling time. To test memory bigger than 2GB, 36BIT support is needed.
 136    Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
 137    window to physical address so that all physical memory can be tested.
 138
 139 Combination of hwconfig
 140 =======================
 141 Hwconfig can be combined with multiple parameters, for example, on a supported
 142 platform
 143
 144 hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
 145
 146 Table for dynamic ODT for DDR3
 147 ==============================
 148 For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
 149 be needed, depending on the configuration. The numbers in the following tables are
 150 in Ohms.
 151
 152 * denotes dynamic ODT
 153
 154 Two slots system
 155 +-----------------------+----------+---------------+-----------------------------+-----------------------------+
 156 |     Configuration     |          |DRAM controller|           Slot 1            |            Slot 2           |
 157 +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
 158 |           |           |          |       |       |     Rank 1   |     Rank 2   |   Rank 1     |    Rank 2    |
 159 +  Slot 1   |   Slot 2  |Write/Read| Write | Read  |-------+------+-------+------+-------+------+-------+------+
 160 |           |           |          |       |       | Write | Read | Write | Read | Write | Read | Write | Read |
 161 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 162 |           |           |  Slot 1  |  off  | 75    | 120   | off  | off   | off  | off   | off  | 30    | 30   |
 163 | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 164 |           |           |  Slot 2  |  off  | 75    | off   | off  | 30    | 30   | 120   | off  | off   | off  |
 165 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 166 |           |           |  Slot 1  |  off  | 75    | 120   | off  | off   | off  | 20    | 20   |       |      |
 167 | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 168 |           |           |  Slot 2  |  off  | 75    | off   | off  | 20    | 20   | 120  *| off  |       |      |
 169 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 170 |           |           |  Slot 1  |  off  | 75    | 120  *| off  |       |      | off   | off  | 20    | 20   |
 171 |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 172 |           |           |  Slot 2  |  off  | 75    | 20    | 20   |       |      | 120   | off  | off   | off  |
 173 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 174 |           |           |  Slot 1  |  off  | 75    | 120  *| off  |       |      | 30    | 30   |       |      |
 175 |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 176 |           |           |  Slot 2  |  off  | 75    | 30    | 30   |       |      | 120  *| off  |       |      |
 177 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 178 | Dual Rank |   Empty   |  Slot 1  |  off  | 75    | 40    | off  | off   | off  |       |      |       |      |
 179 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 180 |   Empty   | Dual Rank |  Slot 2  |  off  | 75    |       |      |       |      | 40    | off  | off   | off  |
 181 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 182 |Single Rank|   Empty   |  Slot 1  |  off  | 75    | 40    | off  |       |      |       |      |       |      |
 183 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 184 |   Empty   |Single Rank|  Slot 2  |  off  | 75    |       |      |       |      | 40    | off  |       |      |
 185 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 186
 187 Single slot system
 188 +-------------+------------+---------------+-----------------------------+-----------------------------+
 189 |             |            |DRAM controller|     Rank 1   |    Rank 2    |    Rank 3    |    Rank 4    |
 190 |Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+
 191 |             |            | Write | Read  | Write | Read | Write | Read | Write | Read | Write | Read |
 192 +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 193 |             |   R1       | off   | 75    | 120  *| off  | off   | off  | 20    | 20   | off   | off  |
 194 |             |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 195 |             |   R2       | off   | 75    | off   | 20   | 120   | off  | 20    | 20   | off   | off  |
 196 |  Quad Rank  |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 197 |             |   R3       | off   | 75    | 20    | 20   | off   | off  | 120  *| off  | off   | off  |
 198 |             |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 199 |             |   R4       | off   | 75    | 20    | 20   | off   | off  | off   | 20   | 120   | off  |
 200 +-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 201 |             |   R1       | off   | 75    | 40    | off  | off   | off  |
 202 |  Dual Rank  |------------+-------+-------+-------+------+-------+------+
 203 |             |   R2       | off   | 75    | 40    | off  | off   | off  |
 204 +-------------+------------+-------+-------+-------+------+-------+------+
 205 | Single Rank |   R1       | off   | 75    | 40    | off  |
 206 +-------------+------------+-------+-------+-------+------+
 207
 208 Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf
 209           http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf
 210
 211
 212 Table for ODT for DDR2
 213 ======================
 214 Two slots system
 215 +-----------------------+----------+---------------+-----------------------------+-----------------------------+
 216 |     Configuration     |          |DRAM controller|           Slot 1            |            Slot 2           |
 217 +-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
 218 |           |           |          |       |       |     Rank 1   |     Rank 2   |   Rank 1     |    Rank 2    |
 219 +  Slot 1   |   Slot 2  |Write/Read| Write | Read  |-------+------+-------+------+-------+------+-------+------+
 220 |           |           |          |       |       | Write | Read | Write | Read | Write | Read | Write | Read |
 221 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 222 |           |           |  Slot 1  |  off  | 150   | off   | off  | off   | off  | 75    | 75   | off   | off  |
 223 | Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 224 |           |           |  Slot 2  |  off  | 150   | 75    | 75   | off   | off  | off   | off  | off   | off  |
 225 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 226 |           |           |  Slot 1  |  off  | 150   | off   | off  | off   | off  | 75    | 75   |       |      |
 227 | Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 228 |           |           |  Slot 2  |  off  | 150   | 75    | 75   | off   | off  | off   | off  |       |      |
 229 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 230 |           |           |  Slot 1  |  off  | 150   | off   | off  |       |      | 75    | 75   | off   | off  |
 231 |Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 232 |           |           |  Slot 2  |  off  | 150   | 75    | 75   |       |      | off   | off  | off   | off  |
 233 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 234 |           |           |  Slot 1  |  off  | 150   | off   | off  |       |      | 75    | 75   |       |      |
 235 |Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 236 |           |           |  Slot 2  |  off  | 150   | 75    | 75   |       |      | off   | off  |       |      |
 237 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 238 | Dual Rank |   Empty   |  Slot 1  |  off  | 75    | 150   | off  | off   | off  |       |      |       |      |
 239 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 240 |   Empty   | Dual Rank |  Slot 2  |  off  | 75    |       |      |       |      | 150   | off  | off   | off  |
 241 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 242 |Single Rank|   Empty   |  Slot 1  |  off  | 75    | 150   | off  |       |      |       |      |       |      |
 243 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 244 |   Empty   |Single Rank|  Slot 2  |  off  | 75    |       |      |       |      | 150   | off  |       |      |
 245 +-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
 246
 247 Single slot system
 248 +-------------+------------+---------------+-----------------------------+
 249 |             |            |DRAM controller|     Rank 1   |    Rank 2    |
 250 |Configuration| Write/Read |-------+-------+-------+------+-------+------+
 251 |             |            | Write | Read  | Write | Read | Write | Read |
 252 +-------------+------------+-------+-------+-------+------+-------+------+
 253 |             |   R1       | off   | 75    | 150   | off  | off   | off  |
 254 |  Dual Rank  |------------+-------+-------+-------+------+-------+------+
 255 |             |   R2       | off   | 75    | 150   | off  | off   | off  |
 256 +-------------+------------+-------+-------+-------+------+-------+------+
 257 | Single Rank |   R1       | off   | 75    | 150   | off  |
 258 +-------------+------------+-------+-------+-------+------+
 259
 260 Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf
 261
 262
 263 Interactive DDR debugging
 264 ===========================
 265
 266 For DDR parameter tuning up and debugging, the interactive DDR debugger can
 267 be activated by setting the environment variable "ddr_interactive" to any
 268 value.  (The value of ddr_interactive may have a meaning in the future, but,
 269 for now, the presence of the variable will cause the debugger to run.)  Once
 270 activated, U-boot will show the prompt "FSL DDR>" before enabling the DDR
 271 controller.  The available commands are printed by typing "help".
 272
 273 Another way to enter the interactive DDR debugger without setting the
 274 environment variable is to send the 'd' character early during the boot
 275 process.  To save booting time, no additional delay is added, so the window
 276 to send the key press is very short -- basically, it is the time before the
 277 memory controller code starts to run.  For example, when rebooting from
 278 within u-boot, the user must press 'd' IMMEDIATELY after hitting enter to
 279 initiate a 'reset' command.  In case of power on/reset, the user can hold
 280 down the 'd' key while applying power or hitting the board's reset button.
 281
 282 The example flow of using interactive debugging is
 283 type command "compute" to calculate the parameters from the default
 284 type command "print" with arguments to show SPD, options, registers
 285 type command "edit" with arguments to change any if desired
 286 type command "copy" with arguments to copy controller/dimm settings
 287 type command "go" to continue calculation and enable DDR controller
 288
 289 Additional commands to restart the debugging are:
 290 type command "reset" to reset the board
 291 type command "recompute" to reload SPD and start over
 292
 293 Note, check "next_step" to show the flow. For example, after edit opts, the
 294 next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is
 295 STEP_PROGRAM_REGS.  Upon issuing command "go", the debugger will program the
 296 DDR controller with the current setting without further calculation and then
 297 exit to resume the booting of the machine.
 298
 299 The detail syntax for each commands are
 300
 301 print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
 302         c<n>            - the controller number, eg. c0, c1
 303         d<n>            - the DIMM number, eg. d0, d1
 304         spd             - print SPD data
 305         dimmparms       - DIMM parameters, calculated from SPD
 306         commonparms     - lowest common parameters for all DIMMs
 307         opts            - options
 308         addresses       - address assignment (not implemented yet)
 309         regs            - controller registers
 310
 311 edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value>
 312         c<n>            - the controller number, eg. c0, c1
 313         d<n>            - the DIMM number, eg. d0, d1
 314         spd             - print SPD data
 315         dimmparms       - DIMM parameters, calculated from SPD
 316         commonparms     - lowest common parameters for all DIMMs
 317         opts            - options
 318         addresses       - address assignment (not implemented yet)
 319         regs            - controller registers
 320         <element>       - name of the modified element
 321                           byte number if the object is SPD
 322         <value>         - decimal or heximal (prefixed with 0x) numbers
 323
 324 copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>
 325         same as for "edit" command
 326         DIMM numbers ignored for commonparms, opts, and regs
 327
 328 reset
 329         no arguement    - reset the board
 330
 331 recompute
 332         no argument     - reload SPD and start over
 333
 334 compute
 335         no argument     - recompute from current next_step
 336
 337 next_step
 338         no argument     - show current next_step
 339
 340 help
 341         no argument     - print a list of all commands
 342
 343 go
 344         no argument     - program memory controller(s) and continue with U-boot
 345
 346 Examples of debugging flow
 347
 348         FSL DDR>compute
 349         Detected UDIMM UG51U6400N8SU-ACF
 350         FSL DDR>print
 351         print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
 352         FSL DDR>print dimmparms
 353         DIMM parameters:  Controller=0 DIMM=0
 354         DIMM organization parameters:
 355         module part name = UG51U6400N8SU-ACF
 356         rank_density = 2147483648 bytes (2048 megabytes)
 357         capacity = 4294967296 bytes (4096 megabytes)
 358         burst_lengths_bitmask = 0C
 359         base_addresss = 0 (00000000 00000000)
 360         n_ranks = 2
 361         data_width = 64
 362         primary_sdram_width = 64
 363         ec_sdram_width = 0
 364         registered_dimm = 0
 365         n_row_addr = 15
 366         n_col_addr = 10
 367         edc_config = 0
 368         n_banks_per_sdram_device = 8
 369         tCKmin_X_ps = 1500
 370         tCKmin_X_minus_1_ps = 0
 371         tCKmin_X_minus_2_ps = 0
 372         tCKmax_ps = 0
 373         caslat_X = 960
 374         tAA_ps = 13125
 375         caslat_X_minus_1 = 0
 376         caslat_X_minus_2 = 0
 377         caslat_lowest_derated = 0
 378         tRCD_ps = 13125
 379         tRP_ps = 13125
 380         tRAS_ps = 36000
 381         tWR_ps = 15000
 382         tWTR_ps = 7500
 383         tRFC_ps = 160000
 384         tRRD_ps = 6000
 385         tRC_ps = 49125
 386         refresh_rate_ps = 7800000
 387         tIS_ps = 0
 388         tIH_ps = 0
 389         tDS_ps = 0
 390         tDH_ps = 0
 391         tRTP_ps = 7500
 392         tDQSQ_max_ps = 0
 393         tQHS_ps = 0
 394         FSL DDR>edit c0 opts ECC_mode 0
 395         FSL DDR>edit c0 regs cs0_bnds 0x000000FF
 396         FSL DDR>go
 397         2 GiB left unmapped
 398         4 GiB (DDR3, 64-bit, CL=9, ECC off)
 399                DDR Chip-Select Interleaving Mode: CS0+CS1
 400         Testing 0x00000000 - 0x7fffffff
 401         Testing 0x80000000 - 0xffffffff
 402         Remap DDR 2 GiB left unmapped
 403
 404         POST memory PASSED
 405         Flash: 128 MiB
 406         L2:    128 KB enabled
 407         Corenet Platform Cache: 1024 KB enabled
 408         SERDES: timeout resetting bank 3
 409         SRIO1: disabled
 410         SRIO2: disabled
 411         MMC:  FSL_ESDHC: 0
 412         EEPROM: Invalid ID (ff ff ff ff)
 413         PCIe1: disabled
 414         PCIe2: Root Complex, x1, regs @ 0xfe201000
 415           01:00.0     - 8086:10d3 - Network controller
 416         PCIe2: Bus 00 - 01
 417         PCIe3: disabled
 418         In:    serial
 419         Out:   serial
 420         Err:   serial
 421         Net:   Initializing Fman
 422         Fman1: Uploading microcode version 101.8.0
 423         e1000: 00:1b:21:81:d2:e0
 424         FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME]
 425         Warning: e1000#0 MAC addresses don't match:
 426         Address in SROM is         00:1b:21:81:d2:e0
 427         Address in environment is  00:e0:0c:00:ea:05
 428
 429         Hit any key to stop autoboot:  0
 430         =>