doc/README.mpc85xxads

   1 Motorola MPC8540ADS and MPC8560ADS board
   2
   3 Created 10/15/03 Xianghua Xiao
   4 Updated 13-July-2004 Jon Loeliger
   5 -----------------------------------------
   6
   7 0. Toolchain
   8
   9     The Binutils in current ELDK toolchain will not support MPC85xx
  10     chip.  You need to use binutils-2.14.tar.bz2 (or newer) from
  11     http://ftp.gnu.org/gnu/binutils.
  12
  13     The 8540/8560 ADS code base is known to compile using:
  14         gcc (GCC) 3.2.2 20030217 (Yellow Dog Linux 3.0 3.2.2-2a)
  15
  16
  17 1. SWITCH SETTINGS & JUMPERS
  18
  19 1.0 Nomenclature
  20
  21     For some reason, the HW designers describe the switch settings
  22     in terms of 0 and 1, and then map that to physical switches where
  23     the label "On" refers to logic 0 and "Off" (unlabeled) is logic 1.
  24     Luckily, we're SW types and virtual settings are handled daily.
  25
  26     The switches for the Rev A board are numbered differently than
  27     for the Pilot board.  Oh yeah.
  28
  29     Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
  30     bits may contribute to signals that are numbered based at 0,
  31     and some of those signals may be high-bit-number-0 too.  Heed
  32     well the names and labels and do not get confused.
  33
  34     "Off" == 1
  35     "On"  == 0
  36
  37     SW18 is switch 18 as silk-screened onto the board.
  38     SW4[8] is the bit labeled 8 on Switch 4.
  39     SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2
  40     SW3[7:1] refers to bits labeled 7 through 1 in order on switch 3
  41
  42 1.1 For the MPC85xxADS Pilot Board
  43
  44     First, make sure the board default setting is consistent with the document
  45     shipped with your board. Then apply the following changes:
  46     SW3[1-6]="all OFF"  (boot from 32bit flash, no boot sequence is used)
  47     SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560)
  48     SW11[2]='OFF for 8560, ON for 8540' (toggle 8540.8560 mode)
  49     SW11[7]='ON' (rev2), 'OFF' (rev1)
  50     SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector)
  51     SW22[1-4]="OFF OFF ON OFF"
  52     SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF"
  53     J1 = "Enable Prog" (Make sure your flash is programmable for development)
  54
  55     If you want to test PCI functionality with a 33Mhz PCI card, you will
  56     have to change the system clock from the default 66Mhz to 33Mhz by
  57     setting SW15[1]="OFF" and SW17[8]="OFF". After that you may also need
  58     double your platform clock(SW6) because the system clock is now only
  59     half of its original value. For example, if at 66MHz your system
  60     clock showed SW6[0:1] = 01, then at 33MHz SW6[0:1] it should be 10.
  61
  62         SW17[8] ------+    SW6
  63         SW15[1] ----+ |   [0:1]
  64                     V V    V V
  65         33MHz       1 1    1 0
  66         66MHz       0 0    0 1
  67
  68     Hmmm... That SW6 setting description is incomplete but it works.
  69
  70
  71 1.3 For the MPC85xxADS Rev A Board
  72
  73     As shipped, the board should be a 33MHz PCI bus with a CPU Clock
  74     rate of 825 +/- fuzz:
  75
  76         Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC:  82 MHz
  77
  78     For 33MHz PCI, the switch settings should be like this:
  79
  80         SW18[7:1] = 0100001 = M==33 =>    33MHz
  81         SW18[8]   =       1         => PWD Divider == 16
  82         SW16[1:2] =      11         => N == 16 as PWD==1
  83
  84     Use the magical formula:
  85         Fout (MHz) = 16 * M / N = 16 * 33 / 16 = 33 MHz
  86
  87         SW7[1:4]  =    1010 = 10    => 10 x 33   = 330  CCB Sysclk
  88         SW7[5:6]  =      01         => 5:2 x 330 = 825  Core clock
  89
  90
  91     For 66MHz PCI, the switch settings should be like this:
  92
  93         SW18[7:1] = 0100001 = M==33 =>    33MHz
  94         SW18[8]   =       0         => PWD Divider == 1
  95         SW16[1:2] =      01         => N == 8 as PWD == 0
  96
  97     Use the magical formula:
  98         Fout (MHz) = 16 * M / N = 16 * 33 / 8 = 66 MHz
  99
 100         SW7[1:4]  =    0101 =  5    => 5 x 66    = 330  CCB Sysclk
 101         SW7[5:6]  =      01         => 5:2 x 330 = 825  Core clock
 102
 103     In order to use PCI-X (only in the first PCI slot.  The one with
 104     the RIO connector), you need to set SW1[4] (config) to 1 (off).
 105     Also, configure the board to run PCI at 66 MHz.
 106
 107 2. MEMORY MAP TO WORK WITH LINUX KERNEL
 108
 109 2.1. For the initial bringup, we adopted a consistent memory scheme
 110      between U-Boot and linux kernel, you can customize it based on your
 111      system requirements:
 112
 113      0x0000_0000     0x7fff_ffff     DDR                     2G
 114      0x8000_0000     0x9fff_ffff     PCI MEM                 512M
 115      0xc000_0000     0xdfff_ffff     Rapid IO                512M
 116      0xe000_0000     0xe00f_ffff     CCSR                    1M
 117      0xe200_0000     0xe2ff_ffff     PCI IO                  16M
 118      0xf000_0000     0xf7ff_ffff     SDRAM                   128M
 119      0xf800_0000     0xf80f_ffff     BCSR                    1M
 120      0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
 121
 122 2.2 We are submitting Linux kernel patches for MPC8540 and MPC8560. You
 123     can download them from linuxppc-2.4 public source. Please make sure the
 124     kernel's ppcboot.h is consistent with U-Boot's u-boot.h. You can use two
 125     default configuration files as your starting points to configure the
 126     kernel:
 127         arch/powerpc/configs/mpc8540_ads_defconfig
 128         arch/powerpc/configs/mpc8560_ads_defconfig
 129
 130 3. DEFINITIONS AND COMPILATION
 131
 132 3.1 Explanation on NEW definitions in:
 133         include/configs/MPC8540ADS.h
 134         include/configs/MPC8560ADS.h
 135
 136     CONFIG_BOOKE            BOOKE(e.g. Motorola MPC85xx, AMCC 440, etc)
 137     CONFIG_E500             BOOKE e500 family(Motorola)
 138     CONFIG_MPC85xx          MPC8540,MPC8560 and their derivatives
 139     CONFIG_ARCH_MPC8540     MPC8540 specific
 140     CONFIG_TSEC_ENET        Use on-chip 10/100/1000 ethernet for networking
 141     CONFIG_SPD_EEPROM       Use SPD EEPROM for DDR auto configuration, you can
 142                             also manual config the DDR after undef this
 143                             definition.
 144     CONFIG_DDR_ECC          only for ECC DDR module
 145     CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN     DLL fix on some ADS boards needed
 146                             for more stability.
 147     CONFIG_HAS_FEC          If an FEC is on chip, set to 1, else 0.
 148
 149 Other than the above definitions, the rest in the config files are
 150 straightforward.
 151
 152
 153 3.2 Compilation
 154
 155     Assuming you're using BASH shell:
 156
 157         export CROSS_COMPILE=your-cross-compile-prefix
 158         cd u-boot
 159         make distclean
 160         make MPC8560ADS_config (or make MPC8540ADS_config)
 161         make
 162
 163 4.  Notes:
 164
 165 4.1 When connecting with kermit, the following commands must be present.in
 166     your .kermrc file. These are especially important when booting as
 167     MPC8560, as the serial console will not work without them:
 168
 169         set speed 115200
 170         set carrier-watch off
 171         set handshake none
 172         set flow-control none
 173         robust
 174
 175
 176 4.2 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC
 177     ethernet. If that happens, you can try the following steps to make
 178     network work:
 179
 180         MPC8560ADS>tftp 1000000 pImage
 181         (if it hangs, use Ctrl-C to quit)
 182         MPC8560ADS>nm fdf24524
 183         >0
 184         >1
 185         >. (to quit this memory operation)
 186         MPC8560ADS>tftp 1000000 pImage
 187
 188 4.3 If you're one of the early developers using the Rev1 8540/8560 chips,
 189     please use U-Boot 1.0.0, as the newer silicon will only support Rev2
 190     and future revisions of 8540/8560.
 191
 192
 193 4.4 Reflash U-Boot Image using U-Boot
 194
 195     tftp 10000 u-boot.bin
 196     protect off fff80000 ffffffff
 197     erase fff80000 ffffffff
 198     cp.b 10000 fff80000 80000
 199
 200
 201 4.5 Reflash U-Boot with a BDI-2000
 202
 203     BDI> erase 0xFFF80000 0x4000 0x20
 204     BDI> prog 0xfff80000 u-boot.bin.8560ads
 205     BDI> verify
 206
 207
 208 5. Screen dump MPC8540ADS board
 209
 210 U-Boot 1.1.2(pq3-20040707-0) (Jul  6 2004 - 17:34:25)
 211
 212 Freescale PowerPC
 213     Core: E500, Version: 2.0, (0x80200020)
 214     System: 8540, Version: 2.0, (0x80300020)
 215     Clocks: CPU: 825 MHz, CCB: 330 MHz, DDR: 165 MHz, LBC:  82 MHz
 216     L1 D-cache 32KB, L1 I-cache 32KB enabled.
 217 Board: ADS
 218     PCI1: 32 bit, 66 MHz (compiled)
 219 I2C:   ready
 220 DRAM:  Initializing
 221     SDRAM: 64 MB
 222     DDR: 256 MB
 223 FLASH: 16 MB
 224 L2 cache enabled: 256KB
 225 *** Warning - bad CRC, using default environment
 226
 227 In:    serial
 228 Out:   serial
 229 Err:   serial
 230 Net:   MOTO ENET0: PHY is Marvell 88E1011S (1410c62)
 231 MOTO ENET1: PHY is Marvell 88E1011S (1410c62)
 232 MOTO ENET2: PHY is Davicom DM9161E (181b881)
 233 MOTO ENET0, MOTO ENET1, MOTO ENET2
 234 Hit any key to stop autoboot:  0
 235 =>
 236 => fli
 237
 238 Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
 239   Size: 16 MB in 64 Sectors
 240   Sector Start Addresses:
 241     FF000000      FF040000      FF080000      FF0C0000      FF100000
 242     FF140000      FF180000      FF1C0000      FF200000      FF240000
 243     FF280000      FF2C0000      FF300000      FF340000      FF380000
 244     FF3C0000      FF400000      FF440000      FF480000      FF4C0000
 245     FF500000      FF540000      FF580000      FF5C0000      FF600000
 246     FF640000      FF680000      FF6C0000      FF700000      FF740000
 247     FF780000      FF7C0000      FF800000      FF840000      FF880000
 248     FF8C0000      FF900000      FF940000      FF980000      FF9C0000
 249     FFA00000      FFA40000      FFA80000      FFAC0000      FFB00000
 250     FFB40000      FFB80000      FFBC0000      FFC00000      FFC40000
 251     FFC80000      FFCC0000      FFD00000      FFD40000      FFD80000
 252     FFDC0000      FFE00000      FFE40000      FFE80000      FFEC0000
 253     FFF00000      FFF40000      FFF80000 (RO) FFFC0000 (RO)
 254
 255 => bdinfo
 256 memstart    = 0x00000000
 257 memsize     = 0x10000000
 258 flashstart  = 0xFF000000
 259 flashsize   = 0x01000000
 260 flashoffset = 0x00000000
 261 sramstart   = 0x00000000
 262 sramsize    = 0x00000000
 263 immr_base   = 0xE0000000
 264 bootflags   = 0xE4013F80
 265 intfreq     =    825 MHz
 266 busfreq     =    330 MHz
 267 ethaddr     = 00:E0:0C:00:00:FD
 268 eth1addr    = 00:E0:0C:00:01:FD
 269 eth2addr    = 00:E0:0C:00:02:FD
 270 IP addr     = 192.168.1.253
 271 baudrate    = 115200 bps
 272
 273
 274 => printenv
 275 bootcmd=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
 276 ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;bootm $loadaddr $ramdiskaddr
 277 nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;bootm $loadaddr
 278 bootdelay=10
 279 baudrate=115200
 280 loads_echo=1
 281 ethaddr=00:E0:0C:00:00:FD
 282 eth1addr=00:E0:0C:00:01:FD
 283 eth2addr=00:E0:0C:00:02:FD
 284 ipaddr=192.168.1.253
 285 serverip=192.168.1.1
 286 rootpath=/nfsroot
 287 gatewayip=192.168.1.1
 288 netmask=255.255.255.0
 289 hostname=unknown
 290 bootfile=your.uImage
 291 loadaddr=200000
 292 netdev=eth0
 293 consoledev=ttyS0
 294 ramdiskaddr=400000
 295 ramdiskfile=your.ramdisk.u-boot
 296 stdin=serial
 297 stdout=serial
 298 stderr=serial
 299 ethact=MOTO ENET0
 300
 301 Environment size: 1020/8188 bytes