doc/README.nand

   1 NAND FLASH commands and notes
   2
   3 See NOTE below!!!
   4
   5 # (C) Copyright 2003
   6 # Dave Ellis, SIXNET, dge@sixnetio.com
   7 #
   8 # SPDX-License-Identifier:      GPL-2.0+
   9
  10 Commands:
  11
  12    nand bad
  13       Print a list of all of the bad blocks in the current device.
  14
  15    nand device
  16       Print information about the current NAND device.
  17
  18    nand device num
  19       Make device `num' the current device and print information about it.
  20
  21    nand erase off|partition size
  22    nand erase clean [off|partition size]
  23       Erase `size' bytes starting at offset `off'. Alternatively partition
  24       name can be specified, in this case size will be eventually limited
  25       to not exceed partition size (this behaviour applies also to read
  26       and write commands). Only complete erase blocks can be erased.
  27
  28       If `erase' is specified without an offset or size, the entire flash
  29       is erased. If `erase' is specified with partition but without an
  30       size, the entire partition is erased.
  31
  32       If `clean' is specified, a JFFS2-style clean marker is written to
  33       each block after it is erased.
  34
  35       This command will not erase blocks that are marked bad. There is
  36       a debug option in cmd_nand.c to allow bad blocks to be erased.
  37       Please read the warning there before using it, as blocks marked
  38       bad by the manufacturer must _NEVER_ be erased.
  39
  40    nand info
  41       Print information about all of the NAND devices found.
  42
  43    nand read addr ofs|partition size
  44       Read `size' bytes from `ofs' in NAND flash to `addr'.  Blocks that
  45       are marked bad are skipped.  If a page cannot be read because an
  46       uncorrectable data error is found, the command stops with an error.
  47
  48    nand read.oob addr ofs|partition size
  49       Read `size' bytes from the out-of-band data area corresponding to
  50       `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
  51       data for one 512-byte page or 2 256-byte pages. There is no check
  52       for bad blocks or ECC errors.
  53
  54    nand write addr ofs|partition size
  55       Write `size' bytes from `addr' to `ofs' in NAND flash.  Blocks that
  56       are marked bad are skipped.  If a page cannot be read because an
  57       uncorrectable data error is found, the command stops with an error.
  58
  59       As JFFS2 skips blocks similarly, this allows writing a JFFS2 image,
  60       as long as the image is short enough to fit even after skipping the
  61       bad blocks.  Compact images, such as those produced by mkfs.jffs2
  62       should work well, but loading an image copied from another flash is
  63       going to be trouble if there are any bad blocks.
  64
  65    nand write.trimffs addr ofs|partition size
  66       Enabled by the CONFIG_CMD_NAND_TRIMFFS macro. This command will write to
  67       the NAND flash in a manner identical to the 'nand write' command
  68       described above -- with the additional check that all pages at the end
  69       of eraseblocks which contain only 0xff data will not be written to the
  70       NAND flash. This behaviour is required when flashing UBI images
  71       containing UBIFS volumes as per the UBI FAQ[1].
  72
  73       [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo
  74
  75    nand write.oob addr ofs|partition size
  76       Write `size' bytes from `addr' to the out-of-band data area
  77       corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
  78       of data for one 512-byte page or 2 256-byte pages. There is no check
  79       for bad blocks.
  80
  81    nand read.raw addr ofs|partition [count]
  82    nand write.raw addr ofs|partition [count]
  83       Read or write one or more pages at "ofs" in NAND flash, from or to
  84       "addr" in memory.  This is a raw access, so ECC is avoided and the
  85       OOB area is transferred as well.  If count is absent, it is assumed
  86       to be one page.  As with .yaffs2 accesses, the data is formatted as
  87       a packed sequence of "data, oob, data, oob, ..." -- no alignment of
  88       individual pages is maintained.
  89
  90 Configuration Options:
  91
  92    CONFIG_SYS_NAND_U_BOOT_OFFS
  93         NAND Offset from where SPL will read u-boot image. This is the starting
  94         address of u-boot MTD partition in NAND.
  95
  96    CONFIG_CMD_NAND
  97       Enables NAND support and commands.
  98
  99    CONFIG_CMD_NAND_TORTURE
 100       Enables the torture command (see description of this command below).
 101
 102    CONFIG_SYS_MAX_NAND_DEVICE
 103       The maximum number of NAND devices you want to support.
 104
 105    CONFIG_SYS_NAND_MAX_ECCPOS
 106       If specified, overrides the maximum number of ECC bytes
 107       supported.  Useful for reducing image size, especially with SPL.
 108       This must be at least 48 if nand_base.c is used.
 109
 110    CONFIG_SYS_NAND_MAX_OOBFREE
 111       If specified, overrides the maximum number of free OOB regions
 112       supported.  Useful for reducing image size, especially with SPL.
 113       This must be at least 2 if nand_base.c is used.
 114
 115    CONFIG_SYS_NAND_MAX_CHIPS
 116       The maximum number of NAND chips per device to be supported.
 117
 118    CONFIG_SYS_NAND_SELF_INIT
 119       Traditionally, glue code in drivers/mtd/nand/nand.c has driven
 120       the initialization process -- it provides the mtd and nand
 121       structs, calls a board init function for a specific device,
 122       calls nand_scan(), and registers with mtd.
 123
 124       This arrangement does not provide drivers with the flexibility to
 125       run code between nand_scan_ident() and nand_scan_tail(), or other
 126       deviations from the "normal" flow.
 127
 128       If a board defines CONFIG_SYS_NAND_SELF_INIT, drivers/mtd/nand/nand.c
 129       will make one call to board_nand_init(), with no arguments.  That
 130       function is responsible for calling a driver init function for
 131       each NAND device on the board, that performs all initialization
 132       tasks except setting mtd->name, and registering with the rest of
 133       U-Boot.  Those last tasks are accomplished by calling  nand_register()
 134       on the new mtd device.
 135
 136       Example of new init to be added to the end of an existing driver
 137       init:
 138
 139         /* chip is struct nand_chip, and is now provided by the driver. */
 140         mtd = nand_to_mtd(&chip);
 141
 142         /*
 143          * Fill in appropriate values if this driver uses these fields,
 144          * or uses the standard read_byte/write_buf/etc. functions from
 145          * nand_base.c that use these fields.
 146          */
 147         chip.IO_ADDR_R = ...;
 148         chip.IO_ADDR_W = ...;
 149
 150         if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL))
 151                 error out
 152
 153         /*
 154          * Insert here any code you wish to run after the chip has been
 155          * identified, but before any other I/O is done.
 156          */
 157
 158         if (nand_scan_tail(mtd))
 159                 error out
 160
 161         /*
 162          * devnum is the device number to be used in nand commands
 163          * and in mtd->name.  Must be less than CONFIG_SYS_MAX_NAND_DEVICE.
 164          */
 165         if (nand_register(devnum, mtd))
 166                 error out
 167
 168       In addition to providing more flexibility to the driver, it reduces
 169       the difference between a U-Boot driver and its Linux counterpart.
 170       nand_init() is now reduced to calling board_nand_init() once, and
 171       printing a size summary.  This should also make it easier to
 172       transition to delayed NAND initialization.
 173
 174       Please convert your driver even if you don't need the extra
 175       flexibility, so that one day we can eliminate the old mechanism.
 176
 177
 178    CONFIG_SYS_NAND_ONFI_DETECTION
 179         Enables detection of ONFI compliant devices during probe.
 180         And fetching device parameters flashed on device, by parsing
 181         ONFI parameter page.
 182
 183 Platform specific options
 184 =========================
 185    CONFIG_NAND_OMAP_GPMC
 186         Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
 187         GPMC controller is used for parallel NAND flash devices, and can
 188         do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
 189         and BCH16 ECC algorithms.
 190
 191    CONFIG_NAND_OMAP_ELM
 192         Enables omap_elm.c driver for OMAPx and AMxxxx platforms.
 193         ELM controller is used for ECC error detection (not ECC calculation)
 194         of BCH4, BCH8 and BCH16 ECC algorithms.
 195         Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
 196         thus such SoC platforms need to depend on software library for ECC error
 197         detection. However ECC calculation on such plaforms would still be
 198         done by GPMC controller.
 199
 200    CONFIG_SPL_NAND_AM33XX_BCH
 201         Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
 202         hardware ECC correction. This is useful for platforms which have ELM
 203         hardware engine and use NAND boot mode.
 204         Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
 205         so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
 206         SPL-NAND driver with software ECC correction support.
 207
 208    CONFIG_NAND_OMAP_ECCSCHEME
 209         On OMAP platforms, this CONFIG specifies NAND ECC scheme.
 210         It can take following values:
 211         OMAP_ECC_HAM1_CODE_SW
 212                 1-bit Hamming code using software lib.
 213                 (for legacy devices only)
 214         OMAP_ECC_HAM1_CODE_HW
 215                 1-bit Hamming code using GPMC hardware.
 216                 (for legacy devices only)
 217         OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
 218                 4-bit BCH code (unsupported)
 219         OMAP_ECC_BCH4_CODE_HW
 220                 4-bit BCH code (unsupported)
 221         OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 222                 8-bit BCH code with
 223                 - ecc calculation using GPMC hardware engine,
 224                 - error detection using software library.
 225                 - requires CONFIG_BCH to enable software BCH library
 226                 (For legacy device which do not have ELM h/w engine)
 227         OMAP_ECC_BCH8_CODE_HW
 228                 8-bit BCH code with
 229                 - ecc calculation using GPMC hardware engine,
 230                 - error detection using ELM hardware engine.
 231         OMAP_ECC_BCH16_CODE_HW
 232                 16-bit BCH code with
 233                 - ecc calculation using GPMC hardware engine,
 234                 - error detection using ELM hardware engine.
 235
 236         How to select ECC scheme on OMAP and AMxx platforms ?
 237         -----------------------------------------------------
 238         Though higher ECC schemes have more capability to detect and correct
 239         bit-flips, but still selection of ECC scheme is dependent on following
 240         - hardware engines present in SoC.
 241                 Some legacy OMAP SoC do not have ELM h/w engine thus such
 242                 SoC cannot support BCHx_HW ECC schemes.
 243         - size of OOB/Spare region
 244                 With higher ECC schemes, more OOB/Spare area is required to
 245                 store ECC. So choice of ECC scheme is limited by NAND oobsize.
 246
 247         In general following expression can help:
 248                 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
 249         where
 250                 NAND_OOBSIZE    = number of bytes available in
 251                                 OOB/spare area per NAND page.
 252                 NAND_PAGESIZE   = bytes in main-area of NAND page.
 253                 ECC_BYTES       = number of ECC bytes generated to
 254                                 protect 512 bytes of data, which is:
 255                                 3 for HAM1_xx ecc schemes
 256                                 7 for BCH4_xx ecc schemes
 257                                 14 for BCH8_xx ecc schemes
 258                                 26 for BCH16_xx ecc schemes
 259
 260                 example to check for BCH16 on 2K page NAND
 261                 NAND_PAGESIZE = 2048
 262                 NAND_OOBSIZE = 64
 263                 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
 264                 Thus BCH16 cannot be supported on 2K page NAND.
 265
 266                 However, for 4K pagesize NAND
 267                 NAND_PAGESIZE = 4096
 268                 NAND_OOBSIZE = 224
 269                 ECC_BYTES = 26
 270                 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
 271                 Thus BCH16 can be supported on 4K page NAND.
 272
 273
 274     CONFIG_NAND_OMAP_GPMC_PREFETCH
 275         On OMAP platforms that use the GPMC controller
 276         (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
 277         uses the prefetch mode to speed up read operations.
 278
 279 NOTE:
 280 =====
 281
 282 The Disk On Chip driver is currently broken and has been for some time.
 283 There is a driver in drivers/mtd/nand, taken from Linux, that works with
 284 the current NAND system but has not yet been adapted to the u-boot
 285 environment.
 286
 287 Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
 288
 289 JFFS2 related commands:
 290
 291   implement "nand erase clean" and old "nand erase"
 292   using both the new code which is able to skip bad blocks
 293   "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.
 294
 295 Miscellaneous and testing commands:
 296   "markbad [offset]"
 297   create an artificial bad block (for testing bad block handling)
 298
 299   "scrub [offset length]"
 300   like "erase" but don't skip bad block. Instead erase them.
 301   DANGEROUS!!! Factory set bad blocks will be lost. Use only
 302   to remove artificial bad blocks created with the "markbad" command.
 303
 304   "torture offset [size]"
 305   Torture block to determine if it is still reliable.
 306   Enabled by the CONFIG_CMD_NAND_TORTURE configuration option.
 307   This command returns 0 if the block is still reliable, else 1.
 308   If the block is detected as unreliable, it is up to the user to decide to
 309   mark this block as bad.
 310   The analyzed block is put through 3 erase / write cycles (or less if the block
 311   is detected as unreliable earlier).
 312   This command can be used in scripts, e.g. together with the markbad command to
 313   automate retries and handling of possibly newly detected bad blocks if the
 314   nand write command fails.
 315   It can also be used manually by users having seen some NAND errors in logs to
 316   search the root cause of these errors.
 317   The underlying nand_torture() function is also useful for code willing to
 318   automate actions following a nand->write() error. This would e.g. be required
 319   in order to program or update safely firmware to NAND, especially for the UBI
 320   part of such firmware.
 321   Optionally, a second parameter size can be given to test multiple blocks with
 322   one call. If size is not a multiple of the NAND's erase size, then the block
 323   that contains offset + size will be tested in full. If used with size, this
 324   command returns 0 if all tested blocks have been found reliable, else 1.
 325
 326
 327 NAND locking command (for chips with active LOCKPRE pin)
 328
 329   "nand lock"
 330   set NAND chip to lock state (all pages locked)
 331
 332   "nand lock tight"
 333   set NAND chip to lock tight state (software can't change locking anymore)
 334
 335   "nand lock status"
 336   displays current locking status of all pages
 337
 338   "nand unlock [offset] [size]"
 339   unlock consecutive area (can be called multiple times for different areas)
 340
 341   "nand unlock.allexcept [offset] [size]"
 342   unlock all except specified consecutive area
 343
 344 I have tested the code with board containing 128MiB NAND large page chips
 345 and 32MiB small page chips.