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1 NAND FLASH commands and notes
2
3 See NOTE below!!!
4
5 # (C) Copyright 2003
6 # Dave Ellis, SIXNET, dge@sixnetio.com
7 #
8 # See file CREDITS for list of people who contributed to this
9 # project.
10 #
11 # This program is free software; you can redistribute it and/or
12 # modify it under the terms of the GNU General Public License as
13 # published by the Free Software Foundation; either version 2 of
14 # the License, or (at your option) any later version.
15 #
16 # This program is distributed in the hope that it will be useful,
17 # but WITHOUT ANY WARRANTY; without even the implied warranty of
18 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 # GNU General Public License for more details.
20 #
21 # You should have received a copy of the GNU General Public License
22 # along with this program; if not, write to the Free Software
23 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 # MA 02111-1307 USA
25
26 Commands:
27
28 nand bad
29 Print a list of all of the bad blocks in the current device.
30
31 nand device
32 Print information about the current NAND device.
33
34 nand device num
35 Make device `num' the current device and print information about it.
36
37 nand erase off|partition size
38 nand erase clean [off|partition size]
39 Erase `size' bytes starting at offset `off'. Alternatively partition
40 name can be specified, in this case size will be eventually limited
41 to not exceed partition size (this behaviour applies also to read
42 and write commands). Only complete erase blocks can be erased.
43
44 If `erase' is specified without an offset or size, the entire flash
45 is erased. If `erase' is specified with partition but without an
46 size, the entire partition is erased.
47
48 If `clean' is specified, a JFFS2-style clean marker is written to
49 each block after it is erased.
50
51 This command will not erase blocks that are marked bad. There is
52 a debug option in cmd_nand.c to allow bad blocks to be erased.
53 Please read the warning there before using it, as blocks marked
54 bad by the manufacturer must _NEVER_ be erased.
55
56 nand info
57 Print information about all of the NAND devices found.
58
59 nand read addr ofs|partition size
60 Read `size' bytes from `ofs' in NAND flash to `addr'. Blocks that
61 are marked bad are skipped. If a page cannot be read because an
62 uncorrectable data error is found, the command stops with an error.
63
64 nand read.oob addr ofs|partition size
65 Read `size' bytes from the out-of-band data area corresponding to
66 `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
67 data for one 512-byte page or 2 256-byte pages. There is no check
68 for bad blocks or ECC errors.
69
70 nand write addr ofs|partition size
71 Write `size' bytes from `addr' to `ofs' in NAND flash. Blocks that
72 are marked bad are skipped. If a page cannot be read because an
73 uncorrectable data error is found, the command stops with an error.
74
75 As JFFS2 skips blocks similarly, this allows writing a JFFS2 image,
76 as long as the image is short enough to fit even after skipping the
77 bad blocks. Compact images, such as those produced by mkfs.jffs2
78 should work well, but loading an image copied from another flash is
79 going to be trouble if there are any bad blocks.
80
81 nand write.oob addr ofs|partition size
82 Write `size' bytes from `addr' to the out-of-band data area
83 corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
84 of data for one 512-byte page or 2 256-byte pages. There is no check
85 for bad blocks.
86
87 Configuration Options:
88
89 CONFIG_CMD_NAND
90 Enables NAND support and commmands.
91
92 CONFIG_MTD_NAND_ECC_JFFS2
93 Define this if you want the Error Correction Code information in
94 the out-of-band data to be formatted to match the JFFS2 file system.
95 CONFIG_MTD_NAND_ECC_YAFFS would be another useful choice for
96 someone to implement.
97
98 CONFIG_SYS_MAX_NAND_DEVICE
99 The maximum number of NAND devices you want to support.
100
101 NAND Interface:
102
103 #define NAND_WAIT_READY(nand)
104 Wait until the NAND flash is ready. Typically this would be a
105 loop waiting for the READY/BUSY line from the flash to indicate it
106 it is ready.
107
108 #define WRITE_NAND_COMMAND(d, adr)
109 Write the command byte `d' to the flash at `adr' with the
110 CLE (command latch enable) line true. If your board uses writes to
111 different addresses to control CLE and ALE, you can modify `adr'
112 to be the appropriate address here. If your board uses I/O registers
113 to control them, it is probably better to let NAND_CTL_SETCLE()
114 and company do it.
115
116 #define WRITE_NAND_ADDRESS(d, adr)
117 Write the address byte `d' to the flash at `adr' with the
118 ALE (address latch enable) line true. If your board uses writes to
119 different addresses to control CLE and ALE, you can modify `adr'
120 to be the appropriate address here. If your board uses I/O registers
121 to control them, it is probably better to let NAND_CTL_SETALE()
122 and company do it.
123
124 #define WRITE_NAND(d, adr)
125 Write the data byte `d' to the flash at `adr' with the
126 ALE and CLE lines false. If your board uses writes to
127 different addresses to control CLE and ALE, you can modify `adr'
128 to be the appropriate address here. If your board uses I/O registers
129 to control them, it is probably better to let NAND_CTL_CLRALE()
130 and company do it.
131
132 #define READ_NAND(adr)
133 Read a data byte from the flash at `adr' with the
134 ALE and CLE lines false. If your board uses reads from
135 different addresses to control CLE and ALE, you can modify `adr'
136 to be the appropriate address here. If your board uses I/O registers
137 to control them, it is probably better to let NAND_CTL_CLRALE()
138 and company do it.
139
140 #define NAND_DISABLE_CE(nand)
141 Set CE (Chip Enable) low to enable the NAND flash.
142
143 #define NAND_ENABLE_CE(nand)
144 Set CE (Chip Enable) high to disable the NAND flash.
145
146 #define NAND_CTL_CLRALE(nandptr)
147 Set ALE (address latch enable) low. If ALE control is handled by
148 WRITE_NAND_ADDRESS() this can be empty.
149
150 #define NAND_CTL_SETALE(nandptr)
151 Set ALE (address latch enable) high. If ALE control is handled by
152 WRITE_NAND_ADDRESS() this can be empty.
153
154 #define NAND_CTL_CLRCLE(nandptr)
155 Set CLE (command latch enable) low. If CLE control is handled by
156 WRITE_NAND_ADDRESS() this can be empty.
157
158 #define NAND_CTL_SETCLE(nandptr)
159 Set CLE (command latch enable) high. If CLE control is handled by
160 WRITE_NAND_ADDRESS() this can be empty.
161
162 More Definitions:
163
164 These definitions are needed in the board configuration for now, but
165 may really belong in a header file.
166 TODO: Figure which ones are truly configuration settings and rename
167 them to CONFIG_SYS_NAND_... and move the rest somewhere appropriate.
168
169 #define SECTORSIZE 512
170 #define ADDR_COLUMN 1
171 #define ADDR_PAGE 2
172 #define ADDR_COLUMN_PAGE 3
173 #define NAND_ChipID_UNKNOWN 0x00
174 #define NAND_MAX_FLOORS 1
175 #define CONFIG_SYS_NAND_MAX_CHIPS 1
176
177 #define CONFIG_SYS_DAVINCI_BROKEN_ECC
178 Versions of U-Boot <= 1.3.3 and Montavista Linux kernels
179 generated bogus ECCs on large-page NAND. Both large and small page
180 NAND ECCs were incompatible with the Linux davinci git tree (since
181 NAND was integrated in 2.6.24).
182 Turn this ON if you want backwards compatibility.
183 Turn this OFF if you want U-Boot and the Linux davinci git kernel
184 to use the same ECC format.
185
186 NOTE:
187 =====
188
189 We now use a complete rewrite of the NAND code based on what is in
190 2.6.12 Linux kernel.
191
192 The old NAND handling code has been re-factored and is now confined
193 to only board-specific files and - unfortunately - to the DoC code
194 (see below). A new configuration variable has been introduced:
195 CONFIG_NAND_LEGACY, which has to be defined in the board config file if
196 that board uses legacy code.
197
198 The necessary changes have been made to all affected boards, and no
199 build breakage has been introduced, except for NETTA and NETTA_ISDN
200 targets from MAKEALL. This is due to the fact that these two boards
201 use JFFS, which has been adopted to use the new NAND, and at the same
202 time use NAND in legacy mode. The breakage will disappear when the
203 board-specific code is changed to the new NAND.
204
205 As mentioned above, the legacy code is still used by the DoC subsystem.
206 The consequence of this is that the legacy NAND can't be removed from
207 the tree until the DoC is ported to use the new NAND support (or boards
208 with DoC will break).
209
210
211 Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
212
213 JFFS2 related commands:
214
215 implement "nand erase clean" and old "nand erase"
216 using both the new code which is able to skip bad blocks
217 "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.
218
219 Miscellaneous and testing commands:
220 "markbad [offset]"
221 create an artificial bad block (for testing bad block handling)
222
223 "scrub [offset length]"
224 like "erase" but don't skip bad block. Instead erase them.
225 DANGEROUS!!! Factory set bad blocks will be lost. Use only
226 to remove artificial bad blocks created with the "markbad" command.
227
228
229 NAND locking command (for chips with active LOCKPRE pin)
230
231 "nand lock"
232 set NAND chip to lock state (all pages locked)
233
234 "nand lock tight"
235 set NAND chip to lock tight state (software can't change locking anymore)
236
237 "nand lock status"
238 displays current locking status of all pages
239
240 "nand unlock [offset] [size]"
241 unlock consecutive area (can be called multiple times for different areas)
242
243
244 I have tested the code with board containing 128MiB NAND large page chips
245 and 32MiB small page chips.