doc/README.p4080ds

   1 Overview
   2 --------
   3 The P4080DS is a Freescale reference board that hosts the eight-core P4080 SOC.
   4
   5 SerDes hwconfig configuration
   6 -----------------------------
   7 The P4080 RCW includes three sets of bits the specify which SerDes lanes
   8 should be powered down: SRDS_LPD_B1 (for bank one), SRDS_LPD_B2 (for bank two),
   9 and SRDS_LPD_B3 (for bank three).  Each of these contains four bits, one for
  10 each lane in the bank.  SerDes Erratum SERDES8 requires that SRDS_LPD_B2 and
  11 SRDS_LPD_B3 be set to 0b1111.  This forces banks two and three to be powered
  12 down at reset.
  13
  14 To re-enable these banks in U-Boot, two hwconfig are available:
  15 "fsl_srds_lpd_b2" and "fsl_srds_lpd_b3".  The value passed via fsl_srds_lpd_b2
  16 is written into SRDS_LPD_B2, and the value passed via fsl_srds_lpd_b3 is into
  17 SRDS_LPD_B3.  Each bit represents one of each bank, and a value of '1'
  18 indicates that the lane should be powered down.
  19
  20 For example, to indicate that both SerDes banks 2 and 3 are powered down, add
  21 the following to hwconfig:
  22
  23         serdes:fsl_srds_lpd_b2=0xf,fsl_srds_lpd_b3=0xf
  24
  25 The "0xf" is a mask that corresponds to the 4 lanes A-D. The most significant
  26 bit corresponds to lane A.  To indicate that just lane A of bank 3 is to be
  27 powered down, use:
  28
  29         serdes:fsl_srds_lpd_b3=8
  30
  31 These options should be specified only if U-Boot does not automatically power
  32 on the correct lanes.