doc/README.uniphier

   1 U-Boot for UniPhier SoC family
   2 ==============================
   3
   4
   5 Recommended toolchains
   6 ----------------------
   7
   8 The UniPhir platform is well tested with Linaro toolchanis.
   9 You can download pre-built toolchains from:
  10
  11     http://www.linaro.org/downloads/
  12
  13
  14 Compile the source
  15 ------------------
  16
  17 sLD3 reference board:
  18     $ make uniphier_sld3_defconfig
  19     $ make CROSS_COMPILE=arm-linux-gnueabihf-
  20
  21 LD4 reference board:
  22     $ make uniphier_ld4_sld8_defconfig
  23     $ make CROSS_COMPILE=arm-linux-gnueabihf-
  24
  25 sLD8 reference board:
  26     $ make uniphier_ld4_sld8_defconfig
  27     $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-sld8-ref
  28
  29 Pro4 reference board:
  30     $ make uniphier_pro4_defconfig
  31     $ make CROSS_COMPILE=arm-linux-gnueabihf-
  32
  33 Pro4 Ace board:
  34     $ make uniphier_pro4_defconfig
  35     $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-ace
  36
  37 Pro4 Sanji board:
  38     $ make uniphier_pro4_defconfig
  39     $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro4-sanji
  40
  41 Pro5 4KBOX Board:
  42     $ make uniphier_pxs2_ld6b_defconfig
  43     $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pro5-4kbox
  44
  45 PXs2 Gentil board:
  46     $ make uniphier_pxs2_ld6b_defconfig
  47     $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-pxs2-gentil
  48
  49 PXs2 Vodka board:
  50     $ make uniphier_pxs2_ld6b_defconfig
  51     $ make CROSS_COMPILE=arm-linux-gnueabihf-
  52
  53 LD6b reference board:
  54     $ make uniphier_pxs2_ld6b_defconfig
  55     $ make CROSS_COMPILE=arm-linux-gnueabihf- DEVICE_TREE=uniphier-ld6b-ref
  56
  57 LD11 reference board:
  58     $ make uniphier_ld11_defconfig
  59     $ make CROSS_COMPILE=aarch64-linux-gnu-
  60
  61 LD20 reference board:
  62     $ make uniphier_ld20_defconfig
  63     $ make CROSS_COMPILE=aarch64-linux-gnu-
  64
  65 PXs3 reference board:
  66     $ make uniphier_v8_defconfig
  67     $ make CROSS_COMPILE=aarch64-linux-gnu- DEVICE_TREE=uniphier-pxs3-ref
  68
  69 You may wish to change the "CROSS_COMPILE=..." to use your favorite compiler.
  70
  71
  72 Burn U-Boot images to NAND
  73 --------------------------
  74
  75 Write the following to the NAND device:
  76
  77  - spl/u-boot-spl.bin at the offset address 0x00000000
  78  - u-boot.bin         at the offset address 0x00020000
  79
  80 or
  81
  82  - u-boot-with-spl.bin at the offset address 0x00000000
  83
  84 If a TFTP server is available, the images can be easily updated.
  85 Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory,
  86 and then run the following command at the U-Boot command line:
  87
  88   => run nandupdate
  89
  90
  91 Burn U-Boot images to eMMC
  92 --------------------------
  93
  94 Write the following to the Boot partition 1 of the eMMC device:
  95
  96  - spl/u-boot-spl.bin at the offset address 0x00000000
  97  - u-boot.bin         at the offset address 0x00020000
  98
  99 or
 100
 101  - u-boot-with-spl.bin at the offset address 0x00000000
 102
 103 If a TFTP server is available, the images can be easily updated.
 104 Just copy the u-boot-spl.bin and u-boot.bin to the TFTP public directory,
 105 and then run the following command at the U-Boot command line:
 106
 107   => run emmcupdate
 108
 109
 110 UniPhier specific commands
 111 --------------------------
 112
 113  - pinmon (enabled by CONFIG_CMD_PINMON)
 114      shows the boot mode pins that has been latched at the power-on reset
 115
 116  - ddrphy (enabled by CONFIG_CMD_DDRPHY_DUMP)
 117      shows the DDR PHY parameters set by the PHY training
 118
 119  - ddrmphy (enabled by CONFIG_CMD_DDRMPHY_DUMP)
 120      shows the DDR Multi PHY parameters set by the PHY training
 121
 122
 123 Supported devices
 124 -----------------
 125
 126  - UART (on-chip)
 127  - NAND
 128  - SD/eMMC
 129  - USB 2.0 (EHCI)
 130  - USB 3.0 (xHCI)
 131  - GPIO
 132  - LAN (on-board SMSC9118)
 133  - I2C
 134  - EEPROM (connected to the on-board I2C bus)
 135  - Support card (SRAM, NOR flash, some peripherals)
 136
 137
 138 Micro Support Card
 139 ------------------
 140
 141 The recommended bit switch settings are as follows:
 142
 143  SW2    OFF(1)/ON(0)   Description
 144  ------------------------------------------
 145  bit 1   <----         BKSZ[0]
 146  bit 2   ---->         BKSZ[1]
 147  bit 3   <----         SoC Bus Width 16/32
 148  bit 4   <----         SERIAL_SEL[0]
 149  bit 5   ---->         SERIAL_SEL[1]
 150  bit 6   ---->         BOOTSWAP_EN
 151  bit 7   <----         CS1/CS5
 152  bit 8   <----         SOC_SERIAL_DISABLE
 153
 154  SW8    OFF(1)/ON(0)   Description
 155  ------------------------------------------
 156  bit 1    <----        CS1_SPLIT
 157  bit 2    <----        CASE9_ON
 158  bit 3    <----        CASE10_ON
 159  bit 4  Don't Care     Reserve
 160  bit 5  Don't Care     Reserve
 161  bit 6  Don't Care     Reserve
 162  bit 7    ---->        BURST_EN
 163  bit 8    ---->        FLASHBUS32_16
 164
 165 The BKSZ[1:0] specifies the address range of memory slot and peripherals
 166 as follows:
 167
 168  BKSZ    Description              RAM slot            Peripherals
 169  --------------------------------------------------------------------
 170  0b00   15MB RAM / 1MB Peri    00000000-00efffff    00f00000-00ffffff
 171  0b01   31MB RAM / 1MB Peri    00000000-01efffff    01f00000-01ffffff
 172  0b10   64MB RAM / 1MB Peri    00000000-03efffff    03f00000-03ffffff
 173  0b11  127MB RAM / 1MB Peri    00000000-07efffff    07f00000-07ffffff
 174
 175 Set BSKZ[1:0] to 0b01 for U-Boot.
 176 This mode is the most handy because EA[24] is always supported by the save pin
 177 mode of the system bus.  On the other hand, EA[25] is not supported for some
 178 newer SoCs.  Even if it is, EA[25] is not connected on most of the boards.
 179
 180 --
 181 Masahiro Yamada <yamada.masahiro@socionext.com>
 182 Jan. 2017