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dm: scsi: Add a device pointer to scan_exec(), scsi_bus_reset()
[people/ms/u-boot.git] / drivers / ata / ahci.c
1 /*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * with the reference on libata and ahci drvier in kernel
9 *
10 * This driver provides a SCSI interface to SATA.
11 */
12 #include <common.h>
13
14 #include <command.h>
15 #include <dm.h>
16 #include <pci.h>
17 #include <asm/processor.h>
18 #include <linux/errno.h>
19 #include <asm/io.h>
20 #include <malloc.h>
21 #include <memalign.h>
22 #include <scsi.h>
23 #include <libata.h>
24 #include <linux/ctype.h>
25 #include <ahci.h>
26
27 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
28
29 #ifndef CONFIG_DM_SCSI
30 struct ahci_uc_priv *probe_ent = NULL;
31 #endif
32
33 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
34
35 /*
36 * Some controllers limit number of blocks they can read/write at once.
37 * Contemporary SSD devices work much faster if the read/write size is aligned
38 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
39 * needed.
40 */
41 #ifndef MAX_SATA_BLOCKS_READ_WRITE
42 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
43 #endif
44
45 /* Maximum timeouts for each event */
46 #define WAIT_MS_SPINUP 20000
47 #define WAIT_MS_DATAIO 10000
48 #define WAIT_MS_FLUSH 5000
49 #define WAIT_MS_LINKUP 200
50
51 __weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
52 {
53 return base + 0x100 + (port * 0x80);
54 }
55
56
57 static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
58 unsigned int port_idx)
59 {
60 base = ahci_port_base(base, port_idx);
61
62 port->cmd_addr = base;
63 port->scr_addr = base + PORT_SCR;
64 }
65
66
67 #define msleep(a) udelay(a * 1000)
68
69 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
70 {
71 const unsigned long start = begin;
72 const unsigned long end = start + len;
73
74 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
75 flush_dcache_range(start, end);
76 }
77
78 /*
79 * SATA controller DMAs to physical RAM. Ensure data from the
80 * controller is invalidated from dcache; next access comes from
81 * physical RAM.
82 */
83 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
84 {
85 const unsigned long start = begin;
86 const unsigned long end = start + len;
87
88 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
89 invalidate_dcache_range(start, end);
90 }
91
92 /*
93 * Ensure data for SATA controller is flushed out of dcache and
94 * written to physical memory.
95 */
96 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
97 {
98 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
99 AHCI_PORT_PRIV_DMA_SZ);
100 }
101
102 static int waiting_for_cmd_completed(void __iomem *offset,
103 int timeout_msec,
104 u32 sign)
105 {
106 int i;
107 u32 status;
108
109 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
110 msleep(1);
111
112 return (i < timeout_msec) ? 0 : -1;
113 }
114
115 int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
116 {
117 u32 tmp;
118 int j = 0;
119 void __iomem *port_mmio = uc_priv->port[port].port_mmio;
120
121 /*
122 * Bring up SATA link.
123 * SATA link bringup time is usually less than 1 ms; only very
124 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
125 */
126 while (j < WAIT_MS_LINKUP) {
127 tmp = readl(port_mmio + PORT_SCR_STAT);
128 tmp &= PORT_SCR_STAT_DET_MASK;
129 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
130 return 0;
131 udelay(1000);
132 j++;
133 }
134 return 1;
135 }
136
137 #ifdef CONFIG_SUNXI_AHCI
138 /* The sunxi AHCI controller requires this undocumented setup */
139 static void sunxi_dma_init(void __iomem *port_mmio)
140 {
141 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
142 }
143 #endif
144
145 int ahci_reset(void __iomem *base)
146 {
147 int i = 1000;
148 u32 __iomem *host_ctl_reg = base + HOST_CTL;
149 u32 tmp = readl(host_ctl_reg); /* global controller reset */
150
151 if ((tmp & HOST_RESET) == 0)
152 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
153
154 /*
155 * reset must complete within 1 second, or
156 * the hardware should be considered fried.
157 */
158 do {
159 udelay(1000);
160 tmp = readl(host_ctl_reg);
161 i--;
162 } while ((i > 0) && (tmp & HOST_RESET));
163
164 if (i == 0) {
165 printf("controller reset failed (0x%x)\n", tmp);
166 return -1;
167 }
168
169 return 0;
170 }
171
172 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
173 {
174 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
175 # ifdef CONFIG_DM_PCI
176 struct udevice *dev = uc_priv->dev;
177 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
178 # else
179 pci_dev_t pdev = uc_priv->dev;
180 unsigned short vendor;
181 # endif
182 u16 tmp16;
183 #endif
184 void __iomem *mmio = uc_priv->mmio_base;
185 u32 tmp, cap_save, cmd;
186 int i, j, ret;
187 void __iomem *port_mmio;
188 u32 port_map;
189
190 debug("ahci_host_init: start\n");
191
192 cap_save = readl(mmio + HOST_CAP);
193 cap_save &= ((1 << 28) | (1 << 17));
194 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
195
196 ret = ahci_reset(uc_priv->mmio_base);
197 if (ret)
198 return ret;
199
200 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
201 writel(cap_save, mmio + HOST_CAP);
202 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
203
204 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
205 # ifdef CONFIG_DM_PCI
206 if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
207 u16 tmp16;
208
209 dm_pci_read_config16(dev, 0x92, &tmp16);
210 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
211 }
212 # else
213 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
214
215 if (vendor == PCI_VENDOR_ID_INTEL) {
216 u16 tmp16;
217 pci_read_config_word(pdev, 0x92, &tmp16);
218 tmp16 |= 0xf;
219 pci_write_config_word(pdev, 0x92, tmp16);
220 }
221 # endif
222 #endif
223 uc_priv->cap = readl(mmio + HOST_CAP);
224 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
225 port_map = uc_priv->port_map;
226 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
227
228 debug("cap 0x%x port_map 0x%x n_ports %d\n",
229 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
230
231 if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
232 uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
233
234 for (i = 0; i < uc_priv->n_ports; i++) {
235 if (!(port_map & (1 << i)))
236 continue;
237 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
238 port_mmio = (u8 *)uc_priv->port[i].port_mmio;
239 ahci_setup_port(&uc_priv->port[i], mmio, i);
240
241 /* make sure port is not active */
242 tmp = readl(port_mmio + PORT_CMD);
243 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
244 PORT_CMD_FIS_RX | PORT_CMD_START)) {
245 debug("Port %d is active. Deactivating.\n", i);
246 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
247 PORT_CMD_FIS_RX | PORT_CMD_START);
248 writel_with_flush(tmp, port_mmio + PORT_CMD);
249
250 /* spec says 500 msecs for each bit, so
251 * this is slightly incorrect.
252 */
253 msleep(500);
254 }
255
256 #ifdef CONFIG_SUNXI_AHCI
257 sunxi_dma_init(port_mmio);
258 #endif
259
260 /* Add the spinup command to whatever mode bits may
261 * already be on in the command register.
262 */
263 cmd = readl(port_mmio + PORT_CMD);
264 cmd |= PORT_CMD_SPIN_UP;
265 writel_with_flush(cmd, port_mmio + PORT_CMD);
266
267 /* Bring up SATA link. */
268 ret = ahci_link_up(uc_priv, i);
269 if (ret) {
270 printf("SATA link %d timeout.\n", i);
271 continue;
272 } else {
273 debug("SATA link ok.\n");
274 }
275
276 /* Clear error status */
277 tmp = readl(port_mmio + PORT_SCR_ERR);
278 if (tmp)
279 writel(tmp, port_mmio + PORT_SCR_ERR);
280
281 debug("Spinning up device on SATA port %d... ", i);
282
283 j = 0;
284 while (j < WAIT_MS_SPINUP) {
285 tmp = readl(port_mmio + PORT_TFDATA);
286 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
287 break;
288 udelay(1000);
289 tmp = readl(port_mmio + PORT_SCR_STAT);
290 tmp &= PORT_SCR_STAT_DET_MASK;
291 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
292 break;
293 j++;
294 }
295
296 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
297 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
298 debug("SATA link %d down (COMINIT received), retrying...\n", i);
299 i--;
300 continue;
301 }
302
303 printf("Target spinup took %d ms.\n", j);
304 if (j == WAIT_MS_SPINUP)
305 debug("timeout.\n");
306 else
307 debug("ok.\n");
308
309 tmp = readl(port_mmio + PORT_SCR_ERR);
310 debug("PORT_SCR_ERR 0x%x\n", tmp);
311 writel(tmp, port_mmio + PORT_SCR_ERR);
312
313 /* ack any pending irq events for this port */
314 tmp = readl(port_mmio + PORT_IRQ_STAT);
315 debug("PORT_IRQ_STAT 0x%x\n", tmp);
316 if (tmp)
317 writel(tmp, port_mmio + PORT_IRQ_STAT);
318
319 writel(1 << i, mmio + HOST_IRQ_STAT);
320
321 /* register linkup ports */
322 tmp = readl(port_mmio + PORT_SCR_STAT);
323 debug("SATA port %d status: 0x%x\n", i, tmp);
324 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
325 uc_priv->link_port_map |= (0x01 << i);
326 }
327
328 tmp = readl(mmio + HOST_CTL);
329 debug("HOST_CTL 0x%x\n", tmp);
330 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
331 tmp = readl(mmio + HOST_CTL);
332 debug("HOST_CTL 0x%x\n", tmp);
333 #if !defined(CONFIG_DM_SCSI)
334 #ifndef CONFIG_SCSI_AHCI_PLAT
335 # ifdef CONFIG_DM_PCI
336 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
337 tmp |= PCI_COMMAND_MASTER;
338 dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
339 # else
340 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
341 tmp |= PCI_COMMAND_MASTER;
342 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
343 # endif
344 #endif
345 #endif
346 return 0;
347 }
348
349
350 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
351 {
352 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
353 # if defined(CONFIG_DM_PCI)
354 struct udevice *dev = uc_priv->dev;
355 # else
356 pci_dev_t pdev = uc_priv->dev;
357 # endif
358 u16 cc;
359 #endif
360 void __iomem *mmio = uc_priv->mmio_base;
361 u32 vers, cap, cap2, impl, speed;
362 const char *speed_s;
363 const char *scc_s;
364
365 vers = readl(mmio + HOST_VERSION);
366 cap = uc_priv->cap;
367 cap2 = readl(mmio + HOST_CAP2);
368 impl = uc_priv->port_map;
369
370 speed = (cap >> 20) & 0xf;
371 if (speed == 1)
372 speed_s = "1.5";
373 else if (speed == 2)
374 speed_s = "3";
375 else if (speed == 3)
376 speed_s = "6";
377 else
378 speed_s = "?";
379
380 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
381 scc_s = "SATA";
382 #else
383 # ifdef CONFIG_DM_PCI
384 dm_pci_read_config16(dev, 0x0a, &cc);
385 # else
386 pci_read_config_word(pdev, 0x0a, &cc);
387 # endif
388 if (cc == 0x0101)
389 scc_s = "IDE";
390 else if (cc == 0x0106)
391 scc_s = "SATA";
392 else if (cc == 0x0104)
393 scc_s = "RAID";
394 else
395 scc_s = "unknown";
396 #endif
397 printf("AHCI %02x%02x.%02x%02x "
398 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
399 (vers >> 24) & 0xff,
400 (vers >> 16) & 0xff,
401 (vers >> 8) & 0xff,
402 vers & 0xff,
403 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
404
405 printf("flags: "
406 "%s%s%s%s%s%s%s"
407 "%s%s%s%s%s%s%s"
408 "%s%s%s%s%s%s\n",
409 cap & (1 << 31) ? "64bit " : "",
410 cap & (1 << 30) ? "ncq " : "",
411 cap & (1 << 28) ? "ilck " : "",
412 cap & (1 << 27) ? "stag " : "",
413 cap & (1 << 26) ? "pm " : "",
414 cap & (1 << 25) ? "led " : "",
415 cap & (1 << 24) ? "clo " : "",
416 cap & (1 << 19) ? "nz " : "",
417 cap & (1 << 18) ? "only " : "",
418 cap & (1 << 17) ? "pmp " : "",
419 cap & (1 << 16) ? "fbss " : "",
420 cap & (1 << 15) ? "pio " : "",
421 cap & (1 << 14) ? "slum " : "",
422 cap & (1 << 13) ? "part " : "",
423 cap & (1 << 7) ? "ccc " : "",
424 cap & (1 << 6) ? "ems " : "",
425 cap & (1 << 5) ? "sxs " : "",
426 cap2 & (1 << 2) ? "apst " : "",
427 cap2 & (1 << 1) ? "nvmp " : "",
428 cap2 & (1 << 0) ? "boh " : "");
429 }
430
431 #ifndef CONFIG_SCSI_AHCI_PLAT
432 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
433 static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
434 # else
435 static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
436 # endif
437 {
438 #if !defined(CONFIG_DM_SCSI)
439 u16 vendor;
440 #endif
441 int rc;
442
443 uc_priv->dev = dev;
444
445 uc_priv->host_flags = ATA_FLAG_SATA
446 | ATA_FLAG_NO_LEGACY
447 | ATA_FLAG_MMIO
448 | ATA_FLAG_PIO_DMA
449 | ATA_FLAG_NO_ATAPI;
450 uc_priv->pio_mask = 0x1f;
451 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
452
453 #if !defined(CONFIG_DM_SCSI)
454 #ifdef CONFIG_DM_PCI
455 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
456 PCI_REGION_MEM);
457
458 /* Take from kernel:
459 * JMicron-specific fixup:
460 * make sure we're in AHCI mode
461 */
462 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
463 if (vendor == 0x197b)
464 dm_pci_write_config8(dev, 0x41, 0xa1);
465 #else
466 uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
467 PCI_REGION_MEM);
468
469 /* Take from kernel:
470 * JMicron-specific fixup:
471 * make sure we're in AHCI mode
472 */
473 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
474 if (vendor == 0x197b)
475 pci_write_config_byte(dev, 0x41, 0xa1);
476 #endif
477 #else
478 struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
479 uc_priv->mmio_base = (void *)plat->base;
480 #endif
481
482 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
483 /* initialize adapter */
484 rc = ahci_host_init(uc_priv);
485 if (rc)
486 goto err_out;
487
488 ahci_print_info(uc_priv);
489
490 return 0;
491
492 err_out:
493 return rc;
494 }
495 #endif
496
497 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
498
499 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
500 unsigned char *buf, int buf_len)
501 {
502 struct ahci_ioports *pp = &(uc_priv->port[port]);
503 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
504 u32 sg_count;
505 int i;
506
507 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
508 if (sg_count > AHCI_MAX_SG) {
509 printf("Error:Too much sg!\n");
510 return -1;
511 }
512
513 for (i = 0; i < sg_count; i++) {
514 ahci_sg->addr =
515 cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT);
516 ahci_sg->addr_hi = 0;
517 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
518 (buf_len < MAX_DATA_BYTE_COUNT
519 ? (buf_len - 1)
520 : (MAX_DATA_BYTE_COUNT - 1)));
521 ahci_sg++;
522 buf_len -= MAX_DATA_BYTE_COUNT;
523 }
524
525 return sg_count;
526 }
527
528
529 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
530 {
531 pp->cmd_slot->opts = cpu_to_le32(opts);
532 pp->cmd_slot->status = 0;
533 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
534 #ifdef CONFIG_PHYS_64BIT
535 pp->cmd_slot->tbl_addr_hi =
536 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
537 #endif
538 }
539
540 static int wait_spinup(void __iomem *port_mmio)
541 {
542 ulong start;
543 u32 tf_data;
544
545 start = get_timer(0);
546 do {
547 tf_data = readl(port_mmio + PORT_TFDATA);
548 if (!(tf_data & ATA_BUSY))
549 return 0;
550 } while (get_timer(start) < WAIT_MS_SPINUP);
551
552 return -ETIMEDOUT;
553 }
554
555 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
556 {
557 struct ahci_ioports *pp = &(uc_priv->port[port]);
558 void __iomem *port_mmio = pp->port_mmio;
559 u32 port_status;
560 void __iomem *mem;
561
562 debug("Enter start port: %d\n", port);
563 port_status = readl(port_mmio + PORT_SCR_STAT);
564 debug("Port %d status: %x\n", port, port_status);
565 if ((port_status & 0xf) != 0x03) {
566 printf("No Link on this port!\n");
567 return -1;
568 }
569
570 mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
571 if (!mem) {
572 free(pp);
573 printf("%s: No mem for table!\n", __func__);
574 return -ENOMEM;
575 }
576
577 /* Aligned to 2048-bytes */
578 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
579 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
580
581 /*
582 * First item in chunk of DMA memory: 32-slot command table,
583 * 32 bytes each in size
584 */
585 pp->cmd_slot =
586 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
587 debug("cmd_slot = %p\n", pp->cmd_slot);
588 mem += (AHCI_CMD_SLOT_SZ + 224);
589
590 /*
591 * Second item: Received-FIS area
592 */
593 pp->rx_fis = virt_to_phys((void *)mem);
594 mem += AHCI_RX_FIS_SZ;
595
596 /*
597 * Third item: data area for storing a single command
598 * and its scatter-gather table
599 */
600 pp->cmd_tbl = virt_to_phys((void *)mem);
601 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
602
603 mem += AHCI_CMD_TBL_HDR;
604 pp->cmd_tbl_sg =
605 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
606
607 writel_with_flush((unsigned long)pp->cmd_slot,
608 port_mmio + PORT_LST_ADDR);
609
610 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
611
612 #ifdef CONFIG_SUNXI_AHCI
613 sunxi_dma_init(port_mmio);
614 #endif
615
616 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
617 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
618 PORT_CMD_START, port_mmio + PORT_CMD);
619
620 debug("Exit start port %d\n", port);
621
622 /*
623 * Make sure interface is not busy based on error and status
624 * information from task file data register before proceeding
625 */
626 return wait_spinup(port_mmio);
627 }
628
629
630 static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
631 int fis_len, u8 *buf, int buf_len, u8 is_write)
632 {
633
634 struct ahci_ioports *pp = &(uc_priv->port[port]);
635 void __iomem *port_mmio = pp->port_mmio;
636 u32 opts;
637 u32 port_status;
638 int sg_count;
639
640 debug("Enter %s: for port %d\n", __func__, port);
641
642 if (port > uc_priv->n_ports) {
643 printf("Invalid port number %d\n", port);
644 return -1;
645 }
646
647 port_status = readl(port_mmio + PORT_SCR_STAT);
648 if ((port_status & 0xf) != 0x03) {
649 debug("No Link on port %d!\n", port);
650 return -1;
651 }
652
653 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
654
655 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
656 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
657 ahci_fill_cmd_slot(pp, opts);
658
659 ahci_dcache_flush_sata_cmd(pp);
660 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
661
662 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
663
664 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
665 WAIT_MS_DATAIO, 0x1)) {
666 printf("timeout exit!\n");
667 return -1;
668 }
669
670 ahci_dcache_invalidate_range((unsigned long)buf,
671 (unsigned long)buf_len);
672 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
673
674 return 0;
675 }
676
677
678 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
679 {
680 int i;
681 for (i = 0; i < len / 2; i++)
682 target[i] = swab16(src[i]);
683 return (char *)target;
684 }
685
686 /*
687 * SCSI INQUIRY command operation.
688 */
689 static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
690 struct scsi_cmd *pccb)
691 {
692 static const u8 hdr[] = {
693 0,
694 0,
695 0x5, /* claim SPC-3 version compatibility */
696 2,
697 95 - 4,
698 };
699 u8 fis[20];
700 u16 *idbuf;
701 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
702 u8 port;
703
704 /* Clean ccb data buffer */
705 memset(pccb->pdata, 0, pccb->datalen);
706
707 memcpy(pccb->pdata, hdr, sizeof(hdr));
708
709 if (pccb->datalen <= 35)
710 return 0;
711
712 memset(fis, 0, sizeof(fis));
713 /* Construct the FIS */
714 fis[0] = 0x27; /* Host to device FIS. */
715 fis[1] = 1 << 7; /* Command FIS. */
716 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
717
718 /* Read id from sata */
719 port = pccb->target;
720
721 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
722 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
723 debug("scsi_ahci: SCSI inquiry command failure.\n");
724 return -EIO;
725 }
726
727 if (!uc_priv->ataid[port]) {
728 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
729 if (!uc_priv->ataid[port]) {
730 printf("%s: No memory for ataid[port]\n", __func__);
731 return -ENOMEM;
732 }
733 }
734
735 idbuf = uc_priv->ataid[port];
736
737 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
738 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
739
740 memcpy(&pccb->pdata[8], "ATA ", 8);
741 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
742 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
743
744 #ifdef DEBUG
745 ata_dump_id(idbuf);
746 #endif
747 return 0;
748 }
749
750
751 /*
752 * SCSI READ10/WRITE10 command operation.
753 */
754 static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
755 struct scsi_cmd *pccb, u8 is_write)
756 {
757 lbaint_t lba = 0;
758 u16 blocks = 0;
759 u8 fis[20];
760 u8 *user_buffer = pccb->pdata;
761 u32 user_buffer_size = pccb->datalen;
762
763 /* Retrieve the base LBA number from the ccb structure. */
764 if (pccb->cmd[0] == SCSI_READ16) {
765 memcpy(&lba, pccb->cmd + 2, 8);
766 lba = be64_to_cpu(lba);
767 } else {
768 u32 temp;
769 memcpy(&temp, pccb->cmd + 2, 4);
770 lba = be32_to_cpu(temp);
771 }
772
773 /*
774 * Retrieve the base LBA number and the block count from
775 * the ccb structure.
776 *
777 * For 10-byte and 16-byte SCSI R/W commands, transfer
778 * length 0 means transfer 0 block of data.
779 * However, for ATA R/W commands, sector count 0 means
780 * 256 or 65536 sectors, not 0 sectors as in SCSI.
781 *
782 * WARNING: one or two older ATA drives treat 0 as 0...
783 */
784 if (pccb->cmd[0] == SCSI_READ16)
785 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
786 else
787 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
788
789 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
790 is_write ? "write" : "read", blocks, lba);
791
792 /* Preset the FIS */
793 memset(fis, 0, sizeof(fis));
794 fis[0] = 0x27; /* Host to device FIS. */
795 fis[1] = 1 << 7; /* Command FIS. */
796 /* Command byte (read/write). */
797 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
798
799 while (blocks) {
800 u16 now_blocks; /* number of blocks per iteration */
801 u32 transfer_size; /* number of bytes per iteration */
802
803 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
804
805 transfer_size = ATA_SECT_SIZE * now_blocks;
806 if (transfer_size > user_buffer_size) {
807 printf("scsi_ahci: Error: buffer too small.\n");
808 return -EIO;
809 }
810
811 /*
812 * LBA48 SATA command but only use 32bit address range within
813 * that (unless we've enabled 64bit LBA support). The next
814 * smaller command range (28bit) is too small.
815 */
816 fis[4] = (lba >> 0) & 0xff;
817 fis[5] = (lba >> 8) & 0xff;
818 fis[6] = (lba >> 16) & 0xff;
819 fis[7] = 1 << 6; /* device reg: set LBA mode */
820 fis[8] = ((lba >> 24) & 0xff);
821 #ifdef CONFIG_SYS_64BIT_LBA
822 if (pccb->cmd[0] == SCSI_READ16) {
823 fis[9] = ((lba >> 32) & 0xff);
824 fis[10] = ((lba >> 40) & 0xff);
825 }
826 #endif
827
828 fis[3] = 0xe0; /* features */
829
830 /* Block (sector) count */
831 fis[12] = (now_blocks >> 0) & 0xff;
832 fis[13] = (now_blocks >> 8) & 0xff;
833
834 /* Read/Write from ahci */
835 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
836 sizeof(fis), user_buffer, transfer_size,
837 is_write)) {
838 debug("scsi_ahci: SCSI %s10 command failure.\n",
839 is_write ? "WRITE" : "READ");
840 return -EIO;
841 }
842
843 /* If this transaction is a write, do a following flush.
844 * Writes in u-boot are so rare, and the logic to know when is
845 * the last write and do a flush only there is sufficiently
846 * difficult. Just do a flush after every write. This incurs,
847 * usually, one extra flush when the rare writes do happen.
848 */
849 if (is_write) {
850 if (-EIO == ata_io_flush(uc_priv, pccb->target))
851 return -EIO;
852 }
853 user_buffer += transfer_size;
854 user_buffer_size -= transfer_size;
855 blocks -= now_blocks;
856 lba += now_blocks;
857 }
858
859 return 0;
860 }
861
862
863 /*
864 * SCSI READ CAPACITY10 command operation.
865 */
866 static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
867 struct scsi_cmd *pccb)
868 {
869 u32 cap;
870 u64 cap64;
871 u32 block_size;
872
873 if (!uc_priv->ataid[pccb->target]) {
874 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
875 "\tNo ATA info!\n"
876 "\tPlease run SCSI command INQUIRY first!\n");
877 return -EPERM;
878 }
879
880 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
881 if (cap64 > 0x100000000ULL)
882 cap64 = 0xffffffff;
883
884 cap = cpu_to_be32(cap64);
885 memcpy(pccb->pdata, &cap, sizeof(cap));
886
887 block_size = cpu_to_be32((u32)512);
888 memcpy(&pccb->pdata[4], &block_size, 4);
889
890 return 0;
891 }
892
893
894 /*
895 * SCSI READ CAPACITY16 command operation.
896 */
897 static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
898 struct scsi_cmd *pccb)
899 {
900 u64 cap;
901 u64 block_size;
902
903 if (!uc_priv->ataid[pccb->target]) {
904 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
905 "\tNo ATA info!\n"
906 "\tPlease run SCSI command INQUIRY first!\n");
907 return -EPERM;
908 }
909
910 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
911 cap = cpu_to_be64(cap);
912 memcpy(pccb->pdata, &cap, sizeof(cap));
913
914 block_size = cpu_to_be64((u64)512);
915 memcpy(&pccb->pdata[8], &block_size, 8);
916
917 return 0;
918 }
919
920
921 /*
922 * SCSI TEST UNIT READY command operation.
923 */
924 static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
925 struct scsi_cmd *pccb)
926 {
927 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
928 }
929
930
931 int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
932 {
933 struct ahci_uc_priv *uc_priv;
934 #ifdef CONFIG_DM_SCSI
935 uc_priv = dev_get_uclass_priv(dev);
936 #else
937 uc_priv = probe_ent;
938 #endif
939 int ret;
940
941 switch (pccb->cmd[0]) {
942 case SCSI_READ16:
943 case SCSI_READ10:
944 ret = ata_scsiop_read_write(uc_priv, pccb, 0);
945 break;
946 case SCSI_WRITE10:
947 ret = ata_scsiop_read_write(uc_priv, pccb, 1);
948 break;
949 case SCSI_RD_CAPAC10:
950 ret = ata_scsiop_read_capacity10(uc_priv, pccb);
951 break;
952 case SCSI_RD_CAPAC16:
953 ret = ata_scsiop_read_capacity16(uc_priv, pccb);
954 break;
955 case SCSI_TST_U_RDY:
956 ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
957 break;
958 case SCSI_INQUIRY:
959 ret = ata_scsiop_inquiry(uc_priv, pccb);
960 break;
961 default:
962 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
963 return false;
964 }
965
966 if (ret) {
967 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
968 return false;
969 }
970 return true;
971
972 }
973
974 static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
975 {
976 u32 linkmap;
977 int i;
978
979 linkmap = uc_priv->link_port_map;
980
981 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
982 if (((linkmap >> i) & 0x01)) {
983 if (ahci_port_start(uc_priv, (u8) i)) {
984 printf("Can not start port %d\n", i);
985 continue;
986 }
987 }
988 }
989
990 return 0;
991 }
992
993 #ifndef CONFIG_DM_SCSI
994 void scsi_low_level_init(int busdevfunc)
995 {
996 struct ahci_uc_priv *uc_priv;
997
998 #ifndef CONFIG_SCSI_AHCI_PLAT
999 probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
1000 if (!probe_ent) {
1001 printf("%s: No memory for uc_priv\n", __func__);
1002 return;
1003 }
1004 uc_priv = probe_ent;
1005 # if defined(CONFIG_DM_PCI)
1006 struct udevice *dev;
1007 int ret;
1008
1009 ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
1010 if (ret)
1011 return;
1012 ahci_init_one(uc_priv, dev);
1013 # else
1014 ahci_init_one(uc_priv, busdevfunc);
1015 # endif
1016 #else
1017 uc_priv = probe_ent;
1018 #endif
1019
1020 ahci_start_ports(uc_priv);
1021 }
1022 #endif
1023
1024 #ifndef CONFIG_SCSI_AHCI_PLAT
1025 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
1026 int achi_init_one_dm(struct udevice *dev)
1027 {
1028 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1029
1030 return ahci_init_one(uc_priv, dev);
1031 }
1032 #endif
1033 #endif
1034
1035 int achi_start_ports_dm(struct udevice *dev)
1036 {
1037 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1038
1039 return ahci_start_ports(uc_priv);
1040 }
1041
1042 #ifdef CONFIG_SCSI_AHCI_PLAT
1043 static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
1044 {
1045 int rc;
1046
1047 uc_priv->host_flags = ATA_FLAG_SATA
1048 | ATA_FLAG_NO_LEGACY
1049 | ATA_FLAG_MMIO
1050 | ATA_FLAG_PIO_DMA
1051 | ATA_FLAG_NO_ATAPI;
1052 uc_priv->pio_mask = 0x1f;
1053 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
1054
1055 uc_priv->mmio_base = base;
1056
1057 /* initialize adapter */
1058 rc = ahci_host_init(uc_priv);
1059 if (rc)
1060 goto err_out;
1061
1062 ahci_print_info(uc_priv);
1063
1064 rc = ahci_start_ports(uc_priv);
1065
1066 err_out:
1067 return rc;
1068 }
1069
1070 #ifndef CONFIG_DM_SCSI
1071 int ahci_init(void __iomem *base)
1072 {
1073 struct ahci_uc_priv *uc_priv;
1074
1075 probe_ent = malloc(sizeof(struct ahci_uc_priv));
1076 if (!probe_ent) {
1077 printf("%s: No memory for uc_priv\n", __func__);
1078 return -ENOMEM;
1079 }
1080
1081 uc_priv = probe_ent;
1082 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
1083
1084 return ahci_init_common(uc_priv, base);
1085 }
1086 #endif
1087
1088 int ahci_init_dm(struct udevice *dev, void __iomem *base)
1089 {
1090 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1091
1092 return ahci_init_common(uc_priv, base);
1093 }
1094
1095 void __weak scsi_init(void)
1096 {
1097 }
1098
1099 #endif /* CONFIG_SCSI_AHCI_PLAT */
1100
1101 /*
1102 * In the general case of generic rotating media it makes sense to have a
1103 * flush capability. It probably even makes sense in the case of SSDs because
1104 * one cannot always know for sure what kind of internal cache/flush mechanism
1105 * is embodied therein. At first it was planned to invoke this after the last
1106 * write to disk and before rebooting. In practice, knowing, a priori, which
1107 * is the last write is difficult. Because writing to the disk in u-boot is
1108 * very rare, this flush command will be invoked after every block write.
1109 */
1110 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
1111 {
1112 u8 fis[20];
1113 struct ahci_ioports *pp = &(uc_priv->port[port]);
1114 void __iomem *port_mmio = pp->port_mmio;
1115 u32 cmd_fis_len = 5; /* five dwords */
1116
1117 /* Preset the FIS */
1118 memset(fis, 0, 20);
1119 fis[0] = 0x27; /* Host to device FIS. */
1120 fis[1] = 1 << 7; /* Command FIS. */
1121 fis[2] = ATA_CMD_FLUSH_EXT;
1122
1123 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1124 ahci_fill_cmd_slot(pp, cmd_fis_len);
1125 ahci_dcache_flush_sata_cmd(pp);
1126 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1127
1128 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1129 WAIT_MS_FLUSH, 0x1)) {
1130 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1131 return -EIO;
1132 }
1133
1134 return 0;
1135 }
1136
1137
1138 __weak int scsi_bus_reset(struct udevice *dev)
1139 {
1140 /*Not implement*/
1141
1142 return 0;
1143 }
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