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dm: ahci: Unwind the confusing init code
[people/ms/u-boot.git] / drivers / ata / ahci.c
1 /*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * with the reference on libata and ahci drvier in kernel
9 *
10 * This driver provides a SCSI interface to SATA.
11 */
12 #include <common.h>
13
14 #include <command.h>
15 #include <dm.h>
16 #include <pci.h>
17 #include <asm/processor.h>
18 #include <linux/errno.h>
19 #include <asm/io.h>
20 #include <malloc.h>
21 #include <memalign.h>
22 #include <scsi.h>
23 #include <libata.h>
24 #include <linux/ctype.h>
25 #include <ahci.h>
26
27 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
28
29 struct ahci_uc_priv *probe_ent = NULL;
30
31 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
32
33 /*
34 * Some controllers limit number of blocks they can read/write at once.
35 * Contemporary SSD devices work much faster if the read/write size is aligned
36 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
37 * needed.
38 */
39 #ifndef MAX_SATA_BLOCKS_READ_WRITE
40 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
41 #endif
42
43 /* Maximum timeouts for each event */
44 #define WAIT_MS_SPINUP 20000
45 #define WAIT_MS_DATAIO 10000
46 #define WAIT_MS_FLUSH 5000
47 #define WAIT_MS_LINKUP 200
48
49 __weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
50 {
51 return base + 0x100 + (port * 0x80);
52 }
53
54
55 static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
56 unsigned int port_idx)
57 {
58 base = ahci_port_base(base, port_idx);
59
60 port->cmd_addr = base;
61 port->scr_addr = base + PORT_SCR;
62 }
63
64
65 #define msleep(a) udelay(a * 1000)
66
67 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
68 {
69 const unsigned long start = begin;
70 const unsigned long end = start + len;
71
72 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
73 flush_dcache_range(start, end);
74 }
75
76 /*
77 * SATA controller DMAs to physical RAM. Ensure data from the
78 * controller is invalidated from dcache; next access comes from
79 * physical RAM.
80 */
81 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
82 {
83 const unsigned long start = begin;
84 const unsigned long end = start + len;
85
86 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
87 invalidate_dcache_range(start, end);
88 }
89
90 /*
91 * Ensure data for SATA controller is flushed out of dcache and
92 * written to physical memory.
93 */
94 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
95 {
96 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
97 AHCI_PORT_PRIV_DMA_SZ);
98 }
99
100 static int waiting_for_cmd_completed(void __iomem *offset,
101 int timeout_msec,
102 u32 sign)
103 {
104 int i;
105 u32 status;
106
107 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
108 msleep(1);
109
110 return (i < timeout_msec) ? 0 : -1;
111 }
112
113 int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
114 {
115 u32 tmp;
116 int j = 0;
117 void __iomem *port_mmio = uc_priv->port[port].port_mmio;
118
119 /*
120 * Bring up SATA link.
121 * SATA link bringup time is usually less than 1 ms; only very
122 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
123 */
124 while (j < WAIT_MS_LINKUP) {
125 tmp = readl(port_mmio + PORT_SCR_STAT);
126 tmp &= PORT_SCR_STAT_DET_MASK;
127 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
128 return 0;
129 udelay(1000);
130 j++;
131 }
132 return 1;
133 }
134
135 #ifdef CONFIG_SUNXI_AHCI
136 /* The sunxi AHCI controller requires this undocumented setup */
137 static void sunxi_dma_init(void __iomem *port_mmio)
138 {
139 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
140 }
141 #endif
142
143 int ahci_reset(void __iomem *base)
144 {
145 int i = 1000;
146 u32 __iomem *host_ctl_reg = base + HOST_CTL;
147 u32 tmp = readl(host_ctl_reg); /* global controller reset */
148
149 if ((tmp & HOST_RESET) == 0)
150 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
151
152 /*
153 * reset must complete within 1 second, or
154 * the hardware should be considered fried.
155 */
156 do {
157 udelay(1000);
158 tmp = readl(host_ctl_reg);
159 i--;
160 } while ((i > 0) && (tmp & HOST_RESET));
161
162 if (i == 0) {
163 printf("controller reset failed (0x%x)\n", tmp);
164 return -1;
165 }
166
167 return 0;
168 }
169
170 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
171 {
172 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
173 # ifdef CONFIG_DM_PCI
174 struct udevice *dev = uc_priv->dev;
175 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
176 # else
177 pci_dev_t pdev = uc_priv->dev;
178 unsigned short vendor;
179 # endif
180 u16 tmp16;
181 #endif
182 void __iomem *mmio = uc_priv->mmio_base;
183 u32 tmp, cap_save, cmd;
184 int i, j, ret;
185 void __iomem *port_mmio;
186 u32 port_map;
187
188 debug("ahci_host_init: start\n");
189
190 cap_save = readl(mmio + HOST_CAP);
191 cap_save &= ((1 << 28) | (1 << 17));
192 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
193
194 ret = ahci_reset(uc_priv->mmio_base);
195 if (ret)
196 return ret;
197
198 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
199 writel(cap_save, mmio + HOST_CAP);
200 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
201
202 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
203 # ifdef CONFIG_DM_PCI
204 if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
205 u16 tmp16;
206
207 dm_pci_read_config16(dev, 0x92, &tmp16);
208 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
209 }
210 # else
211 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
212
213 if (vendor == PCI_VENDOR_ID_INTEL) {
214 u16 tmp16;
215 pci_read_config_word(pdev, 0x92, &tmp16);
216 tmp16 |= 0xf;
217 pci_write_config_word(pdev, 0x92, tmp16);
218 }
219 # endif
220 #endif
221 uc_priv->cap = readl(mmio + HOST_CAP);
222 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
223 port_map = uc_priv->port_map;
224 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
225
226 debug("cap 0x%x port_map 0x%x n_ports %d\n",
227 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
228
229 if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
230 uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
231
232 for (i = 0; i < uc_priv->n_ports; i++) {
233 if (!(port_map & (1 << i)))
234 continue;
235 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
236 port_mmio = (u8 *)uc_priv->port[i].port_mmio;
237 ahci_setup_port(&uc_priv->port[i], mmio, i);
238
239 /* make sure port is not active */
240 tmp = readl(port_mmio + PORT_CMD);
241 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
242 PORT_CMD_FIS_RX | PORT_CMD_START)) {
243 debug("Port %d is active. Deactivating.\n", i);
244 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
245 PORT_CMD_FIS_RX | PORT_CMD_START);
246 writel_with_flush(tmp, port_mmio + PORT_CMD);
247
248 /* spec says 500 msecs for each bit, so
249 * this is slightly incorrect.
250 */
251 msleep(500);
252 }
253
254 #ifdef CONFIG_SUNXI_AHCI
255 sunxi_dma_init(port_mmio);
256 #endif
257
258 /* Add the spinup command to whatever mode bits may
259 * already be on in the command register.
260 */
261 cmd = readl(port_mmio + PORT_CMD);
262 cmd |= PORT_CMD_SPIN_UP;
263 writel_with_flush(cmd, port_mmio + PORT_CMD);
264
265 /* Bring up SATA link. */
266 ret = ahci_link_up(uc_priv, i);
267 if (ret) {
268 printf("SATA link %d timeout.\n", i);
269 continue;
270 } else {
271 debug("SATA link ok.\n");
272 }
273
274 /* Clear error status */
275 tmp = readl(port_mmio + PORT_SCR_ERR);
276 if (tmp)
277 writel(tmp, port_mmio + PORT_SCR_ERR);
278
279 debug("Spinning up device on SATA port %d... ", i);
280
281 j = 0;
282 while (j < WAIT_MS_SPINUP) {
283 tmp = readl(port_mmio + PORT_TFDATA);
284 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
285 break;
286 udelay(1000);
287 tmp = readl(port_mmio + PORT_SCR_STAT);
288 tmp &= PORT_SCR_STAT_DET_MASK;
289 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
290 break;
291 j++;
292 }
293
294 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
295 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
296 debug("SATA link %d down (COMINIT received), retrying...\n", i);
297 i--;
298 continue;
299 }
300
301 printf("Target spinup took %d ms.\n", j);
302 if (j == WAIT_MS_SPINUP)
303 debug("timeout.\n");
304 else
305 debug("ok.\n");
306
307 tmp = readl(port_mmio + PORT_SCR_ERR);
308 debug("PORT_SCR_ERR 0x%x\n", tmp);
309 writel(tmp, port_mmio + PORT_SCR_ERR);
310
311 /* ack any pending irq events for this port */
312 tmp = readl(port_mmio + PORT_IRQ_STAT);
313 debug("PORT_IRQ_STAT 0x%x\n", tmp);
314 if (tmp)
315 writel(tmp, port_mmio + PORT_IRQ_STAT);
316
317 writel(1 << i, mmio + HOST_IRQ_STAT);
318
319 /* register linkup ports */
320 tmp = readl(port_mmio + PORT_SCR_STAT);
321 debug("SATA port %d status: 0x%x\n", i, tmp);
322 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
323 uc_priv->link_port_map |= (0x01 << i);
324 }
325
326 tmp = readl(mmio + HOST_CTL);
327 debug("HOST_CTL 0x%x\n", tmp);
328 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
329 tmp = readl(mmio + HOST_CTL);
330 debug("HOST_CTL 0x%x\n", tmp);
331 #if !defined(CONFIG_DM_SCSI)
332 #ifndef CONFIG_SCSI_AHCI_PLAT
333 # ifdef CONFIG_DM_PCI
334 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
335 tmp |= PCI_COMMAND_MASTER;
336 dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
337 # else
338 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
339 tmp |= PCI_COMMAND_MASTER;
340 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
341 # endif
342 #endif
343 #endif
344 return 0;
345 }
346
347
348 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
349 {
350 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
351 # if defined(CONFIG_DM_PCI)
352 struct udevice *dev = uc_priv->dev;
353 # else
354 pci_dev_t pdev = uc_priv->dev;
355 # endif
356 u16 cc;
357 #endif
358 void __iomem *mmio = uc_priv->mmio_base;
359 u32 vers, cap, cap2, impl, speed;
360 const char *speed_s;
361 const char *scc_s;
362
363 vers = readl(mmio + HOST_VERSION);
364 cap = uc_priv->cap;
365 cap2 = readl(mmio + HOST_CAP2);
366 impl = uc_priv->port_map;
367
368 speed = (cap >> 20) & 0xf;
369 if (speed == 1)
370 speed_s = "1.5";
371 else if (speed == 2)
372 speed_s = "3";
373 else if (speed == 3)
374 speed_s = "6";
375 else
376 speed_s = "?";
377
378 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
379 scc_s = "SATA";
380 #else
381 # ifdef CONFIG_DM_PCI
382 dm_pci_read_config16(dev, 0x0a, &cc);
383 # else
384 pci_read_config_word(pdev, 0x0a, &cc);
385 # endif
386 if (cc == 0x0101)
387 scc_s = "IDE";
388 else if (cc == 0x0106)
389 scc_s = "SATA";
390 else if (cc == 0x0104)
391 scc_s = "RAID";
392 else
393 scc_s = "unknown";
394 #endif
395 printf("AHCI %02x%02x.%02x%02x "
396 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
397 (vers >> 24) & 0xff,
398 (vers >> 16) & 0xff,
399 (vers >> 8) & 0xff,
400 vers & 0xff,
401 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
402
403 printf("flags: "
404 "%s%s%s%s%s%s%s"
405 "%s%s%s%s%s%s%s"
406 "%s%s%s%s%s%s\n",
407 cap & (1 << 31) ? "64bit " : "",
408 cap & (1 << 30) ? "ncq " : "",
409 cap & (1 << 28) ? "ilck " : "",
410 cap & (1 << 27) ? "stag " : "",
411 cap & (1 << 26) ? "pm " : "",
412 cap & (1 << 25) ? "led " : "",
413 cap & (1 << 24) ? "clo " : "",
414 cap & (1 << 19) ? "nz " : "",
415 cap & (1 << 18) ? "only " : "",
416 cap & (1 << 17) ? "pmp " : "",
417 cap & (1 << 16) ? "fbss " : "",
418 cap & (1 << 15) ? "pio " : "",
419 cap & (1 << 14) ? "slum " : "",
420 cap & (1 << 13) ? "part " : "",
421 cap & (1 << 7) ? "ccc " : "",
422 cap & (1 << 6) ? "ems " : "",
423 cap & (1 << 5) ? "sxs " : "",
424 cap2 & (1 << 2) ? "apst " : "",
425 cap2 & (1 << 1) ? "nvmp " : "",
426 cap2 & (1 << 0) ? "boh " : "");
427 }
428
429 #ifndef CONFIG_SCSI_AHCI_PLAT
430 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
431 static int ahci_init_one(struct udevice *dev)
432 # else
433 static int ahci_init_one(pci_dev_t dev)
434 # endif
435 {
436 struct ahci_uc_priv *uc_priv;
437 #if !defined(CONFIG_DM_SCSI)
438 u16 vendor;
439 #endif
440 int rc;
441
442 probe_ent = malloc(sizeof(struct ahci_uc_priv));
443 if (!probe_ent) {
444 printf("%s: No memory for uc_priv\n", __func__);
445 return -ENOMEM;
446 }
447
448 uc_priv = probe_ent;
449 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
450 uc_priv->dev = dev;
451
452 uc_priv->host_flags = ATA_FLAG_SATA
453 | ATA_FLAG_NO_LEGACY
454 | ATA_FLAG_MMIO
455 | ATA_FLAG_PIO_DMA
456 | ATA_FLAG_NO_ATAPI;
457 uc_priv->pio_mask = 0x1f;
458 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
459
460 #if !defined(CONFIG_DM_SCSI)
461 #ifdef CONFIG_DM_PCI
462 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
463 PCI_REGION_MEM);
464
465 /* Take from kernel:
466 * JMicron-specific fixup:
467 * make sure we're in AHCI mode
468 */
469 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
470 if (vendor == 0x197b)
471 dm_pci_write_config8(dev, 0x41, 0xa1);
472 #else
473 uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
474 PCI_REGION_MEM);
475
476 /* Take from kernel:
477 * JMicron-specific fixup:
478 * make sure we're in AHCI mode
479 */
480 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
481 if (vendor == 0x197b)
482 pci_write_config_byte(dev, 0x41, 0xa1);
483 #endif
484 #else
485 struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
486 uc_priv->mmio_base = (void *)plat->base;
487 #endif
488
489 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
490 /* initialize adapter */
491 rc = ahci_host_init(uc_priv);
492 if (rc)
493 goto err_out;
494
495 ahci_print_info(uc_priv);
496
497 return 0;
498
499 err_out:
500 return rc;
501 }
502 #endif
503
504 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
505
506 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
507 unsigned char *buf, int buf_len)
508 {
509 struct ahci_ioports *pp = &(uc_priv->port[port]);
510 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
511 u32 sg_count;
512 int i;
513
514 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
515 if (sg_count > AHCI_MAX_SG) {
516 printf("Error:Too much sg!\n");
517 return -1;
518 }
519
520 for (i = 0; i < sg_count; i++) {
521 ahci_sg->addr =
522 cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT);
523 ahci_sg->addr_hi = 0;
524 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
525 (buf_len < MAX_DATA_BYTE_COUNT
526 ? (buf_len - 1)
527 : (MAX_DATA_BYTE_COUNT - 1)));
528 ahci_sg++;
529 buf_len -= MAX_DATA_BYTE_COUNT;
530 }
531
532 return sg_count;
533 }
534
535
536 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
537 {
538 pp->cmd_slot->opts = cpu_to_le32(opts);
539 pp->cmd_slot->status = 0;
540 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
541 #ifdef CONFIG_PHYS_64BIT
542 pp->cmd_slot->tbl_addr_hi =
543 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
544 #endif
545 }
546
547 static int wait_spinup(void __iomem *port_mmio)
548 {
549 ulong start;
550 u32 tf_data;
551
552 start = get_timer(0);
553 do {
554 tf_data = readl(port_mmio + PORT_TFDATA);
555 if (!(tf_data & ATA_BUSY))
556 return 0;
557 } while (get_timer(start) < WAIT_MS_SPINUP);
558
559 return -ETIMEDOUT;
560 }
561
562 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
563 {
564 struct ahci_ioports *pp = &(uc_priv->port[port]);
565 void __iomem *port_mmio = pp->port_mmio;
566 u32 port_status;
567 void __iomem *mem;
568
569 debug("Enter start port: %d\n", port);
570 port_status = readl(port_mmio + PORT_SCR_STAT);
571 debug("Port %d status: %x\n", port, port_status);
572 if ((port_status & 0xf) != 0x03) {
573 printf("No Link on this port!\n");
574 return -1;
575 }
576
577 mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
578 if (!mem) {
579 free(pp);
580 printf("%s: No mem for table!\n", __func__);
581 return -ENOMEM;
582 }
583
584 /* Aligned to 2048-bytes */
585 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
586 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
587
588 /*
589 * First item in chunk of DMA memory: 32-slot command table,
590 * 32 bytes each in size
591 */
592 pp->cmd_slot =
593 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
594 debug("cmd_slot = %p\n", pp->cmd_slot);
595 mem += (AHCI_CMD_SLOT_SZ + 224);
596
597 /*
598 * Second item: Received-FIS area
599 */
600 pp->rx_fis = virt_to_phys((void *)mem);
601 mem += AHCI_RX_FIS_SZ;
602
603 /*
604 * Third item: data area for storing a single command
605 * and its scatter-gather table
606 */
607 pp->cmd_tbl = virt_to_phys((void *)mem);
608 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
609
610 mem += AHCI_CMD_TBL_HDR;
611 pp->cmd_tbl_sg =
612 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
613
614 writel_with_flush((unsigned long)pp->cmd_slot,
615 port_mmio + PORT_LST_ADDR);
616
617 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
618
619 #ifdef CONFIG_SUNXI_AHCI
620 sunxi_dma_init(port_mmio);
621 #endif
622
623 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
624 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
625 PORT_CMD_START, port_mmio + PORT_CMD);
626
627 debug("Exit start port %d\n", port);
628
629 /*
630 * Make sure interface is not busy based on error and status
631 * information from task file data register before proceeding
632 */
633 return wait_spinup(port_mmio);
634 }
635
636
637 static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
638 int fis_len, u8 *buf, int buf_len, u8 is_write)
639 {
640
641 struct ahci_ioports *pp = &(uc_priv->port[port]);
642 void __iomem *port_mmio = pp->port_mmio;
643 u32 opts;
644 u32 port_status;
645 int sg_count;
646
647 debug("Enter %s: for port %d\n", __func__, port);
648
649 if (port > uc_priv->n_ports) {
650 printf("Invalid port number %d\n", port);
651 return -1;
652 }
653
654 port_status = readl(port_mmio + PORT_SCR_STAT);
655 if ((port_status & 0xf) != 0x03) {
656 debug("No Link on port %d!\n", port);
657 return -1;
658 }
659
660 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
661
662 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
663 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
664 ahci_fill_cmd_slot(pp, opts);
665
666 ahci_dcache_flush_sata_cmd(pp);
667 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
668
669 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
670
671 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
672 WAIT_MS_DATAIO, 0x1)) {
673 printf("timeout exit!\n");
674 return -1;
675 }
676
677 ahci_dcache_invalidate_range((unsigned long)buf,
678 (unsigned long)buf_len);
679 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
680
681 return 0;
682 }
683
684
685 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
686 {
687 int i;
688 for (i = 0; i < len / 2; i++)
689 target[i] = swab16(src[i]);
690 return (char *)target;
691 }
692
693 /*
694 * SCSI INQUIRY command operation.
695 */
696 static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
697 struct scsi_cmd *pccb)
698 {
699 static const u8 hdr[] = {
700 0,
701 0,
702 0x5, /* claim SPC-3 version compatibility */
703 2,
704 95 - 4,
705 };
706 u8 fis[20];
707 u16 *idbuf;
708 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
709 u8 port;
710
711 /* Clean ccb data buffer */
712 memset(pccb->pdata, 0, pccb->datalen);
713
714 memcpy(pccb->pdata, hdr, sizeof(hdr));
715
716 if (pccb->datalen <= 35)
717 return 0;
718
719 memset(fis, 0, sizeof(fis));
720 /* Construct the FIS */
721 fis[0] = 0x27; /* Host to device FIS. */
722 fis[1] = 1 << 7; /* Command FIS. */
723 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
724
725 /* Read id from sata */
726 port = pccb->target;
727
728 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
729 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
730 debug("scsi_ahci: SCSI inquiry command failure.\n");
731 return -EIO;
732 }
733
734 if (!uc_priv->ataid[port]) {
735 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
736 if (!uc_priv->ataid[port]) {
737 printf("%s: No memory for ataid[port]\n", __func__);
738 return -ENOMEM;
739 }
740 }
741
742 idbuf = uc_priv->ataid[port];
743
744 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
745 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
746
747 memcpy(&pccb->pdata[8], "ATA ", 8);
748 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
749 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
750
751 #ifdef DEBUG
752 ata_dump_id(idbuf);
753 #endif
754 return 0;
755 }
756
757
758 /*
759 * SCSI READ10/WRITE10 command operation.
760 */
761 static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
762 struct scsi_cmd *pccb, u8 is_write)
763 {
764 lbaint_t lba = 0;
765 u16 blocks = 0;
766 u8 fis[20];
767 u8 *user_buffer = pccb->pdata;
768 u32 user_buffer_size = pccb->datalen;
769
770 /* Retrieve the base LBA number from the ccb structure. */
771 if (pccb->cmd[0] == SCSI_READ16) {
772 memcpy(&lba, pccb->cmd + 2, 8);
773 lba = be64_to_cpu(lba);
774 } else {
775 u32 temp;
776 memcpy(&temp, pccb->cmd + 2, 4);
777 lba = be32_to_cpu(temp);
778 }
779
780 /*
781 * Retrieve the base LBA number and the block count from
782 * the ccb structure.
783 *
784 * For 10-byte and 16-byte SCSI R/W commands, transfer
785 * length 0 means transfer 0 block of data.
786 * However, for ATA R/W commands, sector count 0 means
787 * 256 or 65536 sectors, not 0 sectors as in SCSI.
788 *
789 * WARNING: one or two older ATA drives treat 0 as 0...
790 */
791 if (pccb->cmd[0] == SCSI_READ16)
792 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
793 else
794 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
795
796 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
797 is_write ? "write" : "read", blocks, lba);
798
799 /* Preset the FIS */
800 memset(fis, 0, sizeof(fis));
801 fis[0] = 0x27; /* Host to device FIS. */
802 fis[1] = 1 << 7; /* Command FIS. */
803 /* Command byte (read/write). */
804 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
805
806 while (blocks) {
807 u16 now_blocks; /* number of blocks per iteration */
808 u32 transfer_size; /* number of bytes per iteration */
809
810 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
811
812 transfer_size = ATA_SECT_SIZE * now_blocks;
813 if (transfer_size > user_buffer_size) {
814 printf("scsi_ahci: Error: buffer too small.\n");
815 return -EIO;
816 }
817
818 /*
819 * LBA48 SATA command but only use 32bit address range within
820 * that (unless we've enabled 64bit LBA support). The next
821 * smaller command range (28bit) is too small.
822 */
823 fis[4] = (lba >> 0) & 0xff;
824 fis[5] = (lba >> 8) & 0xff;
825 fis[6] = (lba >> 16) & 0xff;
826 fis[7] = 1 << 6; /* device reg: set LBA mode */
827 fis[8] = ((lba >> 24) & 0xff);
828 #ifdef CONFIG_SYS_64BIT_LBA
829 if (pccb->cmd[0] == SCSI_READ16) {
830 fis[9] = ((lba >> 32) & 0xff);
831 fis[10] = ((lba >> 40) & 0xff);
832 }
833 #endif
834
835 fis[3] = 0xe0; /* features */
836
837 /* Block (sector) count */
838 fis[12] = (now_blocks >> 0) & 0xff;
839 fis[13] = (now_blocks >> 8) & 0xff;
840
841 /* Read/Write from ahci */
842 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
843 sizeof(fis), user_buffer, transfer_size,
844 is_write)) {
845 debug("scsi_ahci: SCSI %s10 command failure.\n",
846 is_write ? "WRITE" : "READ");
847 return -EIO;
848 }
849
850 /* If this transaction is a write, do a following flush.
851 * Writes in u-boot are so rare, and the logic to know when is
852 * the last write and do a flush only there is sufficiently
853 * difficult. Just do a flush after every write. This incurs,
854 * usually, one extra flush when the rare writes do happen.
855 */
856 if (is_write) {
857 if (-EIO == ata_io_flush(uc_priv, pccb->target))
858 return -EIO;
859 }
860 user_buffer += transfer_size;
861 user_buffer_size -= transfer_size;
862 blocks -= now_blocks;
863 lba += now_blocks;
864 }
865
866 return 0;
867 }
868
869
870 /*
871 * SCSI READ CAPACITY10 command operation.
872 */
873 static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
874 struct scsi_cmd *pccb)
875 {
876 u32 cap;
877 u64 cap64;
878 u32 block_size;
879
880 if (!uc_priv->ataid[pccb->target]) {
881 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
882 "\tNo ATA info!\n"
883 "\tPlease run SCSI command INQUIRY first!\n");
884 return -EPERM;
885 }
886
887 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
888 if (cap64 > 0x100000000ULL)
889 cap64 = 0xffffffff;
890
891 cap = cpu_to_be32(cap64);
892 memcpy(pccb->pdata, &cap, sizeof(cap));
893
894 block_size = cpu_to_be32((u32)512);
895 memcpy(&pccb->pdata[4], &block_size, 4);
896
897 return 0;
898 }
899
900
901 /*
902 * SCSI READ CAPACITY16 command operation.
903 */
904 static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
905 struct scsi_cmd *pccb)
906 {
907 u64 cap;
908 u64 block_size;
909
910 if (!uc_priv->ataid[pccb->target]) {
911 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
912 "\tNo ATA info!\n"
913 "\tPlease run SCSI command INQUIRY first!\n");
914 return -EPERM;
915 }
916
917 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
918 cap = cpu_to_be64(cap);
919 memcpy(pccb->pdata, &cap, sizeof(cap));
920
921 block_size = cpu_to_be64((u64)512);
922 memcpy(&pccb->pdata[8], &block_size, 8);
923
924 return 0;
925 }
926
927
928 /*
929 * SCSI TEST UNIT READY command operation.
930 */
931 static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
932 struct scsi_cmd *pccb)
933 {
934 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
935 }
936
937
938 int scsi_exec(struct scsi_cmd *pccb)
939 {
940 struct ahci_uc_priv *uc_priv = probe_ent;
941 int ret;
942
943 switch (pccb->cmd[0]) {
944 case SCSI_READ16:
945 case SCSI_READ10:
946 ret = ata_scsiop_read_write(uc_priv, pccb, 0);
947 break;
948 case SCSI_WRITE10:
949 ret = ata_scsiop_read_write(uc_priv, pccb, 1);
950 break;
951 case SCSI_RD_CAPAC10:
952 ret = ata_scsiop_read_capacity10(uc_priv, pccb);
953 break;
954 case SCSI_RD_CAPAC16:
955 ret = ata_scsiop_read_capacity16(uc_priv, pccb);
956 break;
957 case SCSI_TST_U_RDY:
958 ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
959 break;
960 case SCSI_INQUIRY:
961 ret = ata_scsiop_inquiry(uc_priv, pccb);
962 break;
963 default:
964 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
965 return false;
966 }
967
968 if (ret) {
969 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
970 return false;
971 }
972 return true;
973
974 }
975
976 static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
977 {
978 u32 linkmap;
979 int i;
980
981 linkmap = uc_priv->link_port_map;
982
983 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
984 if (((linkmap >> i) & 0x01)) {
985 if (ahci_port_start(uc_priv, (u8) i)) {
986 printf("Can not start port %d\n", i);
987 continue;
988 }
989 }
990 }
991
992 return 0;
993 }
994
995 #ifndef CONFIG_DM_SCSI
996 void scsi_low_level_init(int busdevfunc)
997 {
998 struct ahci_uc_priv *uc_priv;
999
1000 #ifndef CONFIG_SCSI_AHCI_PLAT
1001 # if defined(CONFIG_DM_PCI)
1002 struct udevice *dev;
1003 int ret;
1004
1005 ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
1006 if (ret)
1007 return;
1008 ahci_init_one(dev);
1009 # else
1010 ahci_init_one(busdevfunc);
1011 # endif
1012 #endif
1013 uc_priv = probe_ent;
1014
1015 ahci_start_ports(uc_priv);
1016 }
1017 #endif
1018
1019 #ifndef CONFIG_SCSI_AHCI_PLAT
1020 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
1021 int achi_init_one_dm(struct udevice *dev)
1022 {
1023 return ahci_init_one(dev);
1024 }
1025 #endif
1026 #endif
1027
1028 int achi_start_ports_dm(struct udevice *dev)
1029 {
1030 struct ahci_uc_priv *uc_priv = probe_ent;
1031
1032 return ahci_start_ports(uc_priv);
1033 }
1034
1035 #ifdef CONFIG_SCSI_AHCI_PLAT
1036 int ahci_init(void __iomem *base)
1037 {
1038 struct ahci_uc_priv *uc_priv;
1039 int rc = 0;
1040
1041 probe_ent = malloc(sizeof(struct ahci_uc_priv));
1042 if (!probe_ent) {
1043 printf("%s: No memory for uc_priv\n", __func__);
1044 return -ENOMEM;
1045 }
1046
1047 uc_priv = probe_ent;
1048 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
1049
1050 uc_priv->host_flags = ATA_FLAG_SATA
1051 | ATA_FLAG_NO_LEGACY
1052 | ATA_FLAG_MMIO
1053 | ATA_FLAG_PIO_DMA
1054 | ATA_FLAG_NO_ATAPI;
1055 uc_priv->pio_mask = 0x1f;
1056 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
1057
1058 uc_priv->mmio_base = base;
1059
1060 /* initialize adapter */
1061 rc = ahci_host_init(uc_priv);
1062 if (rc)
1063 goto err_out;
1064
1065 ahci_print_info(uc_priv);
1066
1067 rc = ahci_start_ports(uc_priv);
1068
1069 err_out:
1070 return rc;
1071 }
1072
1073 void __weak scsi_init(void)
1074 {
1075 }
1076
1077 #endif
1078
1079 /*
1080 * In the general case of generic rotating media it makes sense to have a
1081 * flush capability. It probably even makes sense in the case of SSDs because
1082 * one cannot always know for sure what kind of internal cache/flush mechanism
1083 * is embodied therein. At first it was planned to invoke this after the last
1084 * write to disk and before rebooting. In practice, knowing, a priori, which
1085 * is the last write is difficult. Because writing to the disk in u-boot is
1086 * very rare, this flush command will be invoked after every block write.
1087 */
1088 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
1089 {
1090 u8 fis[20];
1091 struct ahci_ioports *pp = &(uc_priv->port[port]);
1092 void __iomem *port_mmio = pp->port_mmio;
1093 u32 cmd_fis_len = 5; /* five dwords */
1094
1095 /* Preset the FIS */
1096 memset(fis, 0, 20);
1097 fis[0] = 0x27; /* Host to device FIS. */
1098 fis[1] = 1 << 7; /* Command FIS. */
1099 fis[2] = ATA_CMD_FLUSH_EXT;
1100
1101 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1102 ahci_fill_cmd_slot(pp, cmd_fis_len);
1103 ahci_dcache_flush_sata_cmd(pp);
1104 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1105
1106 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1107 WAIT_MS_FLUSH, 0x1)) {
1108 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1109 return -EIO;
1110 }
1111
1112 return 0;
1113 }
1114
1115
1116 __weak void scsi_bus_reset(void)
1117 {
1118 /*Not implement*/
1119 }
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