drivers/ata/dwc_ahsata.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  * Terry Lv <r65388@freescale.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <libata.h>
   9 #include <ahci.h>
  10 #include <fis.h>
  11 #include <sata.h>
  12
  13 #include <common.h>
  14 #include <malloc.h>
  15 #include <linux/ctype.h>
  16 #include <linux/errno.h>
  17 #include <asm/io.h>
  18 #include <linux/bitops.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include "dwc_ahsata.h"
  22
  23 struct sata_port_regs {
  24         u32 clb;
  25         u32 clbu;
  26         u32 fb;
  27         u32 fbu;
  28         u32 is;
  29         u32 ie;
  30         u32 cmd;
  31         u32 res1[1];
  32         u32 tfd;
  33         u32 sig;
  34         u32 ssts;
  35         u32 sctl;
  36         u32 serr;
  37         u32 sact;
  38         u32 ci;
  39         u32 sntf;
  40         u32 res2[1];
  41         u32 dmacr;
  42         u32 res3[1];
  43         u32 phycr;
  44         u32 physr;
  45 };
  46
  47 struct sata_host_regs {
  48         u32 cap;
  49         u32 ghc;
  50         u32 is;
  51         u32 pi;
  52         u32 vs;
  53         u32 ccc_ctl;
  54         u32 ccc_ports;
  55         u32 res1[2];
  56         u32 cap2;
  57         u32 res2[30];
  58         u32 bistafr;
  59         u32 bistcr;
  60         u32 bistfctr;
  61         u32 bistsr;
  62         u32 bistdecr;
  63         u32 res3[2];
  64         u32 oobr;
  65         u32 res4[8];
  66         u32 timer1ms;
  67         u32 res5[1];
  68         u32 gparam1r;
  69         u32 gparam2r;
  70         u32 pparamr;
  71         u32 testr;
  72         u32 versionr;
  73         u32 idr;
  74 };
  75
  76 #define MAX_DATA_BYTES_PER_SG  (4 * 1024 * 1024)
  77 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
  78
  79 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
  80
  81 static int is_ready;
  82
  83 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
  84 {
  85         return base + 0x100 + (port * 0x80);
  86 }
  87
  88 static int waiting_for_cmd_completed(u8 *offset,
  89                                         int timeout_msec,
  90                                         u32 sign)
  91 {
  92         int i;
  93         u32 status;
  94
  95         for (i = 0;
  96                 ((status = readl(offset)) & sign) && i < timeout_msec;
  97                 ++i)
  98                 mdelay(1);
  99
 100         return (i < timeout_msec) ? 0 : -1;
 101 }
 102
 103 static int ahci_setup_oobr(struct ahci_probe_ent *probe_ent,
 104                                                 int clk)
 105 {
 106         struct sata_host_regs *host_mmio =
 107                 (struct sata_host_regs *)probe_ent->mmio_base;
 108
 109         writel(SATA_HOST_OOBR_WE, &(host_mmio->oobr));
 110         writel(0x02060b14, &(host_mmio->oobr));
 111
 112         return 0;
 113 }
 114
 115 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
 116 {
 117         u32 tmp, cap_save, num_ports;
 118         int i, j, timeout = 1000;
 119         struct sata_port_regs *port_mmio = NULL;
 120         struct sata_host_regs *host_mmio =
 121                 (struct sata_host_regs *)probe_ent->mmio_base;
 122         int clk = mxc_get_clock(MXC_SATA_CLK);
 123
 124         cap_save = readl(&(host_mmio->cap));
 125         cap_save |= SATA_HOST_CAP_SSS;
 126
 127         /* global controller reset */
 128         tmp = readl(&(host_mmio->ghc));
 129         if ((tmp & SATA_HOST_GHC_HR) == 0)
 130                 writel_with_flush(tmp | SATA_HOST_GHC_HR, &(host_mmio->ghc));
 131
 132         while ((readl(&(host_mmio->ghc)) & SATA_HOST_GHC_HR)
 133                 && --timeout)
 134                 ;
 135
 136         if (timeout <= 0) {
 137                 debug("controller reset failed (0x%x)\n", tmp);
 138                 return -1;
 139         }
 140
 141         /* Set timer 1ms */
 142         writel(clk / 1000, &(host_mmio->timer1ms));
 143
 144         ahci_setup_oobr(probe_ent, 0);
 145
 146         writel_with_flush(SATA_HOST_GHC_AE, &(host_mmio->ghc));
 147         writel(cap_save, &(host_mmio->cap));
 148         num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
 149         writel_with_flush((1 << num_ports) - 1,
 150                                 &(host_mmio->pi));
 151
 152         /*
 153          * Determine which Ports are implemented by the DWC_ahsata,
 154          * by reading the PI register. This bit map value aids the
 155          * software to determine how many Ports are available and
 156          * which Port registers need to be initialized.
 157          */
 158         probe_ent->cap = readl(&(host_mmio->cap));
 159         probe_ent->port_map = readl(&(host_mmio->pi));
 160
 161         /* Determine how many command slots the HBA supports */
 162         probe_ent->n_ports =
 163                 (probe_ent->cap & SATA_HOST_CAP_NP_MASK) + 1;
 164
 165         debug("cap 0x%x  port_map 0x%x  n_ports %d\n",
 166                 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
 167
 168         for (i = 0; i < probe_ent->n_ports; i++) {
 169                 probe_ent->port[i].port_mmio =
 170                         ahci_port_base(host_mmio, i);
 171                 port_mmio =
 172                         (struct sata_port_regs *)probe_ent->port[i].port_mmio;
 173
 174                 /* Ensure that the DWC_ahsata is in idle state */
 175                 tmp = readl(&(port_mmio->cmd));
 176
 177                 /*
 178                  * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
 179                  * are all cleared, the Port is in an idle state.
 180                  */
 181                 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
 182                         SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
 183
 184                         /*
 185                          * System software places a Port into the idle state by
 186                          * clearing P#CMD.ST and waiting for P#CMD.CR to return
 187                          * 0 when read.
 188                          */
 189                         tmp &= ~SATA_PORT_CMD_ST;
 190                         writel_with_flush(tmp, &(port_mmio->cmd));
 191
 192                         /*
 193                          * spec says 500 msecs for each bit, so
 194                          * this is slightly incorrect.
 195                          */
 196                         mdelay(500);
 197
 198                         timeout = 1000;
 199                         while ((readl(&(port_mmio->cmd)) & SATA_PORT_CMD_CR)
 200                                 && --timeout)
 201                                 ;
 202
 203                         if (timeout <= 0) {
 204                                 debug("port reset failed (0x%x)\n", tmp);
 205                                 return -1;
 206                         }
 207                 }
 208
 209                 /* Spin-up device */
 210                 tmp = readl(&(port_mmio->cmd));
 211                 writel((tmp | SATA_PORT_CMD_SUD), &(port_mmio->cmd));
 212
 213                 /* Wait for spin-up to finish */
 214                 timeout = 1000;
 215                 while (!(readl(&(port_mmio->cmd)) | SATA_PORT_CMD_SUD)
 216                         && --timeout)
 217                         ;
 218                 if (timeout <= 0) {
 219                         debug("Spin-Up can't finish!\n");
 220                         return -1;
 221                 }
 222
 223                 for (j = 0; j < 100; ++j) {
 224                         mdelay(10);
 225                         tmp = readl(&(port_mmio->ssts));
 226                         if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
 227                                 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
 228                                 break;
 229                 }
 230
 231                 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
 232                 timeout = 1000;
 233                 while (!(readl(&(port_mmio->serr)) | SATA_PORT_SERR_DIAG_X)
 234                         && --timeout)
 235                         ;
 236                 if (timeout <= 0) {
 237                         debug("Can't find DIAG_X set!\n");
 238                         return -1;
 239                 }
 240
 241                 /*
 242                  * For each implemented Port, clear the P#SERR
 243                  * register, by writing ones to each implemented\
 244                  * bit location.
 245                  */
 246                 tmp = readl(&(port_mmio->serr));
 247                 debug("P#SERR 0x%x\n",
 248                                 tmp);
 249                 writel(tmp, &(port_mmio->serr));
 250
 251                 /* Ack any pending irq events for this port */
 252                 tmp = readl(&(host_mmio->is));
 253                 debug("IS 0x%x\n", tmp);
 254                 if (tmp)
 255                         writel(tmp, &(host_mmio->is));
 256
 257                 writel(1 << i, &(host_mmio->is));
 258
 259                 /* set irq mask (enables interrupts) */
 260                 writel(DEF_PORT_IRQ, &(port_mmio->ie));
 261
 262                 /* register linkup ports */
 263                 tmp = readl(&(port_mmio->ssts));
 264                 debug("Port %d status: 0x%x\n", i, tmp);
 265                 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
 266                         probe_ent->link_port_map |= (0x01 << i);
 267         }
 268
 269         tmp = readl(&(host_mmio->ghc));
 270         debug("GHC 0x%x\n", tmp);
 271         writel(tmp | SATA_HOST_GHC_IE, &(host_mmio->ghc));
 272         tmp = readl(&(host_mmio->ghc));
 273         debug("GHC 0x%x\n", tmp);
 274
 275         return 0;
 276 }
 277
 278 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
 279 {
 280         struct sata_host_regs *host_mmio =
 281                 (struct sata_host_regs *)probe_ent->mmio_base;
 282         u32 vers, cap, impl, speed;
 283         const char *speed_s;
 284         const char *scc_s;
 285
 286         vers = readl(&(host_mmio->vs));
 287         cap = probe_ent->cap;
 288         impl = probe_ent->port_map;
 289
 290         speed = (cap & SATA_HOST_CAP_ISS_MASK)
 291                 >> SATA_HOST_CAP_ISS_OFFSET;
 292         if (speed == 1)
 293                 speed_s = "1.5";
 294         else if (speed == 2)
 295                 speed_s = "3";
 296         else
 297                 speed_s = "?";
 298
 299         scc_s = "SATA";
 300
 301         printf("AHCI %02x%02x.%02x%02x "
 302                 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
 303                 (vers >> 24) & 0xff,
 304                 (vers >> 16) & 0xff,
 305                 (vers >> 8) & 0xff,
 306                 vers & 0xff,
 307                 ((cap >> 8) & 0x1f) + 1,
 308                 (cap & 0x1f) + 1,
 309                 speed_s,
 310                 impl,
 311                 scc_s);
 312
 313         printf("flags: "
 314                 "%s%s%s%s%s%s"
 315                 "%s%s%s%s%s%s%s\n",
 316                 cap & (1 << 31) ? "64bit " : "",
 317                 cap & (1 << 30) ? "ncq " : "",
 318                 cap & (1 << 28) ? "ilck " : "",
 319                 cap & (1 << 27) ? "stag " : "",
 320                 cap & (1 << 26) ? "pm " : "",
 321                 cap & (1 << 25) ? "led " : "",
 322                 cap & (1 << 24) ? "clo " : "",
 323                 cap & (1 << 19) ? "nz " : "",
 324                 cap & (1 << 18) ? "only " : "",
 325                 cap & (1 << 17) ? "pmp " : "",
 326                 cap & (1 << 15) ? "pio " : "",
 327                 cap & (1 << 14) ? "slum " : "",
 328                 cap & (1 << 13) ? "part " : "");
 329 }
 330
 331 static int ahci_init_one(int pdev)
 332 {
 333         int rc;
 334         struct ahci_probe_ent *probe_ent = NULL;
 335
 336         probe_ent = malloc(sizeof(struct ahci_probe_ent));
 337         memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
 338         probe_ent->dev = pdev;
 339
 340         probe_ent->host_flags = ATA_FLAG_SATA
 341                                 | ATA_FLAG_NO_LEGACY
 342                                 | ATA_FLAG_MMIO
 343                                 | ATA_FLAG_PIO_DMA
 344                                 | ATA_FLAG_NO_ATAPI;
 345
 346         probe_ent->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
 347
 348         /* initialize adapter */
 349         rc = ahci_host_init(probe_ent);
 350         if (rc)
 351                 goto err_out;
 352
 353         ahci_print_info(probe_ent);
 354
 355         /* Save the private struct to block device struct */
 356         sata_dev_desc[pdev].priv = (void *)probe_ent;
 357
 358         return 0;
 359
 360 err_out:
 361         return rc;
 362 }
 363
 364 static int ahci_fill_sg(struct ahci_probe_ent *probe_ent,
 365                         u8 port, unsigned char *buf, int buf_len)
 366 {
 367         struct ahci_ioports *pp = &(probe_ent->port[port]);
 368         struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
 369         u32 sg_count, max_bytes;
 370         int i;
 371
 372         max_bytes = MAX_DATA_BYTES_PER_SG;
 373         sg_count = ((buf_len - 1) / max_bytes) + 1;
 374         if (sg_count > AHCI_MAX_SG) {
 375                 printf("Error:Too much sg!\n");
 376                 return -1;
 377         }
 378
 379         for (i = 0; i < sg_count; i++) {
 380                 ahci_sg->addr =
 381                         cpu_to_le32((u32)buf + i * max_bytes);
 382                 ahci_sg->addr_hi = 0;
 383                 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
 384                                         (buf_len < max_bytes
 385                                         ? (buf_len - 1)
 386                                         : (max_bytes - 1)));
 387                 ahci_sg++;
 388                 buf_len -= max_bytes;
 389         }
 390
 391         return sg_count;
 392 }
 393
 394 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
 395 {
 396         struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
 397                                         AHCI_CMD_SLOT_SZ * cmd_slot);
 398
 399         memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
 400         cmd_hdr->opts = cpu_to_le32(opts);
 401         cmd_hdr->status = 0;
 402         pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
 403 #ifdef CONFIG_PHYS_64BIT
 404         pp->cmd_slot->tbl_addr_hi =
 405             cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
 406 #endif
 407 }
 408
 409 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
 410
 411 static int ahci_exec_ata_cmd(struct ahci_probe_ent *probe_ent,
 412                 u8 port, struct sata_fis_h2d *cfis,
 413                 u8 *buf, u32 buf_len, s32 is_write)
 414 {
 415         struct ahci_ioports *pp = &(probe_ent->port[port]);
 416         struct sata_port_regs *port_mmio =
 417                         (struct sata_port_regs *)pp->port_mmio;
 418         u32 opts;
 419         int sg_count = 0, cmd_slot = 0;
 420
 421         cmd_slot = AHCI_GET_CMD_SLOT(readl(&(port_mmio->ci)));
 422         if (32 == cmd_slot) {
 423                 printf("Can't find empty command slot!\n");
 424                 return 0;
 425         }
 426
 427         /* Check xfer length */
 428         if (buf_len > MAX_BYTES_PER_TRANS) {
 429                 printf("Max transfer length is %dB\n\r",
 430                         MAX_BYTES_PER_TRANS);
 431                 return 0;
 432         }
 433
 434         memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
 435         if (buf && buf_len)
 436                 sg_count = ahci_fill_sg(probe_ent, port, buf, buf_len);
 437         opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
 438         if (is_write) {
 439                 opts |= 0x40;
 440                 flush_cache((ulong)buf, buf_len);
 441         }
 442         ahci_fill_cmd_slot(pp, cmd_slot, opts);
 443
 444         flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
 445         writel_with_flush(1 << cmd_slot, &(port_mmio->ci));
 446
 447         if (waiting_for_cmd_completed((u8 *)&(port_mmio->ci),
 448                                 10000, 0x1 << cmd_slot)) {
 449                 printf("timeout exit!\n");
 450                 return -1;
 451         }
 452         invalidate_dcache_range((int)(pp->cmd_slot),
 453                                 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
 454         debug("ahci_exec_ata_cmd: %d byte transferred.\n",
 455               pp->cmd_slot->status);
 456         if (!is_write)
 457                 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
 458
 459         return buf_len;
 460 }
 461
 462 static void ahci_set_feature(u8 dev, u8 port)
 463 {
 464         struct ahci_probe_ent *probe_ent =
 465                 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 466         struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 467         struct sata_fis_h2d *cfis = &h2d;
 468
 469         memset(cfis, 0, sizeof(struct sata_fis_h2d));
 470         cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 471         cfis->pm_port_c = 1 << 7;
 472         cfis->command = ATA_CMD_SET_FEATURES;
 473         cfis->features = SETFEATURES_XFER;
 474         cfis->sector_count = ffs(probe_ent->udma_mask + 1) + 0x3e;
 475
 476         ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, READ_CMD);
 477 }
 478
 479 static int ahci_port_start(struct ahci_probe_ent *probe_ent,
 480                                         u8 port)
 481 {
 482         struct ahci_ioports *pp = &(probe_ent->port[port]);
 483         struct sata_port_regs *port_mmio =
 484                 (struct sata_port_regs *)pp->port_mmio;
 485         u32 port_status;
 486         u32 mem;
 487         int timeout = 10000000;
 488
 489         debug("Enter start port: %d\n", port);
 490         port_status = readl(&(port_mmio->ssts));
 491         debug("Port %d status: %x\n", port, port_status);
 492         if ((port_status & 0xf) != 0x03) {
 493                 printf("No Link on this port!\n");
 494                 return -1;
 495         }
 496
 497         mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
 498         if (!mem) {
 499                 free(pp);
 500                 printf("No mem for table!\n");
 501                 return -ENOMEM;
 502         }
 503
 504         mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
 505         memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
 506
 507         /*
 508          * First item in chunk of DMA memory: 32-slot command table,
 509          * 32 bytes each in size
 510          */
 511         pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
 512         debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
 513         mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
 514
 515         /*
 516          * Second item: Received-FIS area, 256-Byte aligned
 517          */
 518         pp->rx_fis = mem;
 519         mem += AHCI_RX_FIS_SZ;
 520
 521         /*
 522          * Third item: data area for storing a single command
 523          * and its scatter-gather table
 524          */
 525         pp->cmd_tbl = mem;
 526         debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
 527
 528         mem += AHCI_CMD_TBL_HDR;
 529
 530         writel_with_flush(0x00004444, &(port_mmio->dmacr));
 531         pp->cmd_tbl_sg = (struct ahci_sg *)mem;
 532         writel_with_flush((u32)pp->cmd_slot, &(port_mmio->clb));
 533         writel_with_flush(pp->rx_fis, &(port_mmio->fb));
 534
 535         /* Enable FRE */
 536         writel_with_flush((SATA_PORT_CMD_FRE | readl(&(port_mmio->cmd))),
 537                         &(port_mmio->cmd));
 538
 539         /* Wait device ready */
 540         while ((readl(&(port_mmio->tfd)) & (SATA_PORT_TFD_STS_ERR |
 541                 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
 542                 && --timeout)
 543                 ;
 544         if (timeout <= 0) {
 545                 debug("Device not ready for BSY, DRQ and"
 546                         "ERR in TFD!\n");
 547                 return -1;
 548         }
 549
 550         writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
 551                           PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
 552                           PORT_CMD_START, &(port_mmio->cmd));
 553
 554         debug("Exit start port %d\n", port);
 555
 556         return 0;
 557 }
 558
 559 int init_sata(int dev)
 560 {
 561         int i;
 562         u32 linkmap;
 563         struct ahci_probe_ent *probe_ent = NULL;
 564
 565 #if defined(CONFIG_MX6)
 566         if (!is_mx6dq() && !is_mx6dqp())
 567                 return 1;
 568 #endif
 569         if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
 570                 printf("The sata index %d is out of ranges\n\r", dev);
 571                 return -1;
 572         }
 573
 574         ahci_init_one(dev);
 575
 576         probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 577         linkmap = probe_ent->link_port_map;
 578
 579         if (0 == linkmap) {
 580                 printf("No port device detected!\n");
 581                 return 1;
 582         }
 583
 584         for (i = 0; i < probe_ent->n_ports; i++) {
 585                 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
 586                         if (ahci_port_start(probe_ent, (u8)i)) {
 587                                 printf("Can not start port %d\n", i);
 588                                 return 1;
 589                         }
 590                         probe_ent->hard_port_no = i;
 591                         break;
 592                 }
 593         }
 594
 595         return 0;
 596 }
 597
 598 int reset_sata(int dev)
 599 {
 600         struct ahci_probe_ent *probe_ent;
 601         struct sata_host_regs *host_mmio;
 602
 603         if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
 604                 printf("The sata index %d is out of ranges\n\r", dev);
 605                 return -1;
 606         }
 607
 608         probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 609         if (NULL == probe_ent)
 610                 /* not initialized, so nothing to reset */
 611                 return 0;
 612
 613         host_mmio = (struct sata_host_regs *)probe_ent->mmio_base;
 614         setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
 615         while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
 616                 udelay(100);
 617
 618         return 0;
 619 }
 620
 621 static void dwc_ahsata_print_info(int dev)
 622 {
 623         struct blk_desc *pdev = &(sata_dev_desc[dev]);
 624
 625         printf("SATA Device Info:\n\r");
 626 #ifdef CONFIG_SYS_64BIT_LBA
 627         printf("S/N: %s\n\rProduct model number: %s\n\r"
 628                 "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
 629                 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
 630 #else
 631         printf("S/N: %s\n\rProduct model number: %s\n\r"
 632                 "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
 633                 pdev->product, pdev->vendor, pdev->revision, pdev->lba);
 634 #endif
 635 }
 636
 637 static void dwc_ahsata_identify(int dev, u16 *id)
 638 {
 639         struct ahci_probe_ent *probe_ent =
 640                 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 641         struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 642         struct sata_fis_h2d *cfis = &h2d;
 643         u8 port = probe_ent->hard_port_no;
 644
 645         memset(cfis, 0, sizeof(struct sata_fis_h2d));
 646
 647         cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 648         cfis->pm_port_c = 0x80; /* is command */
 649         cfis->command = ATA_CMD_ID_ATA;
 650
 651         ahci_exec_ata_cmd(probe_ent, port, cfis,
 652                         (u8 *)id, ATA_ID_WORDS * 2, READ_CMD);
 653         ata_swap_buf_le16(id, ATA_ID_WORDS);
 654 }
 655
 656 static void dwc_ahsata_xfer_mode(int dev, u16 *id)
 657 {
 658         struct ahci_probe_ent *probe_ent =
 659                 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 660
 661         probe_ent->pio_mask = id[ATA_ID_PIO_MODES];
 662         probe_ent->udma_mask = id[ATA_ID_UDMA_MODES];
 663         debug("pio %04x, udma %04x\n\r",
 664                 probe_ent->pio_mask, probe_ent->udma_mask);
 665 }
 666
 667 static u32 dwc_ahsata_rw_cmd(int dev, u32 start, u32 blkcnt,
 668                                 u8 *buffer, int is_write)
 669 {
 670         struct ahci_probe_ent *probe_ent =
 671                 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 672         struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 673         struct sata_fis_h2d *cfis = &h2d;
 674         u8 port = probe_ent->hard_port_no;
 675         u32 block;
 676
 677         block = start;
 678
 679         memset(cfis, 0, sizeof(struct sata_fis_h2d));
 680
 681         cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 682         cfis->pm_port_c = 0x80; /* is command */
 683         cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
 684         cfis->device = ATA_LBA;
 685
 686         cfis->device |= (block >> 24) & 0xf;
 687         cfis->lba_high = (block >> 16) & 0xff;
 688         cfis->lba_mid = (block >> 8) & 0xff;
 689         cfis->lba_low = block & 0xff;
 690         cfis->sector_count = (u8)(blkcnt & 0xff);
 691
 692         if (ahci_exec_ata_cmd(probe_ent, port, cfis,
 693                         buffer, ATA_SECT_SIZE * blkcnt, is_write) > 0)
 694                 return blkcnt;
 695         else
 696                 return 0;
 697 }
 698
 699 void dwc_ahsata_flush_cache(int dev)
 700 {
 701         struct ahci_probe_ent *probe_ent =
 702                 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 703         struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 704         struct sata_fis_h2d *cfis = &h2d;
 705         u8 port = probe_ent->hard_port_no;
 706
 707         memset(cfis, 0, sizeof(struct sata_fis_h2d));
 708
 709         cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 710         cfis->pm_port_c = 0x80; /* is command */
 711         cfis->command = ATA_CMD_FLUSH;
 712
 713         ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
 714 }
 715
 716 static u32 dwc_ahsata_rw_cmd_ext(int dev, u32 start, lbaint_t blkcnt,
 717                                 u8 *buffer, int is_write)
 718 {
 719         struct ahci_probe_ent *probe_ent =
 720                 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 721         struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 722         struct sata_fis_h2d *cfis = &h2d;
 723         u8 port = probe_ent->hard_port_no;
 724         u64 block;
 725
 726         block = (u64)start;
 727
 728         memset(cfis, 0, sizeof(struct sata_fis_h2d));
 729
 730         cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 731         cfis->pm_port_c = 0x80; /* is command */
 732
 733         cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
 734                                  : ATA_CMD_READ_EXT;
 735
 736         cfis->lba_high_exp = (block >> 40) & 0xff;
 737         cfis->lba_mid_exp = (block >> 32) & 0xff;
 738         cfis->lba_low_exp = (block >> 24) & 0xff;
 739         cfis->lba_high = (block >> 16) & 0xff;
 740         cfis->lba_mid = (block >> 8) & 0xff;
 741         cfis->lba_low = block & 0xff;
 742         cfis->device = ATA_LBA;
 743         cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
 744         cfis->sector_count = blkcnt & 0xff;
 745
 746         if (ahci_exec_ata_cmd(probe_ent, port, cfis, buffer,
 747                         ATA_SECT_SIZE * blkcnt, is_write) > 0)
 748                 return blkcnt;
 749         else
 750                 return 0;
 751 }
 752
 753 u32 dwc_ahsata_rw_ncq_cmd(int dev, u32 start, lbaint_t blkcnt,
 754                                 u8 *buffer, int is_write)
 755 {
 756         struct ahci_probe_ent *probe_ent =
 757                 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 758         struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 759         struct sata_fis_h2d *cfis = &h2d;
 760         u8 port = probe_ent->hard_port_no;
 761         u64 block;
 762
 763         if (sata_dev_desc[dev].lba48 != 1) {
 764                 printf("execute FPDMA command on non-LBA48 hard disk\n\r");
 765                 return -1;
 766         }
 767
 768         block = (u64)start;
 769
 770         memset(cfis, 0, sizeof(struct sata_fis_h2d));
 771
 772         cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 773         cfis->pm_port_c = 0x80; /* is command */
 774
 775         cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
 776                                  : ATA_CMD_FPDMA_READ;
 777
 778         cfis->lba_high_exp = (block >> 40) & 0xff;
 779         cfis->lba_mid_exp = (block >> 32) & 0xff;
 780         cfis->lba_low_exp = (block >> 24) & 0xff;
 781         cfis->lba_high = (block >> 16) & 0xff;
 782         cfis->lba_mid = (block >> 8) & 0xff;
 783         cfis->lba_low = block & 0xff;
 784
 785         cfis->device = ATA_LBA;
 786         cfis->features_exp = (blkcnt >> 8) & 0xff;
 787         cfis->features = blkcnt & 0xff;
 788
 789         /* Use the latest queue */
 790         ahci_exec_ata_cmd(probe_ent, port, cfis,
 791                         buffer, ATA_SECT_SIZE * blkcnt, is_write);
 792
 793         return blkcnt;
 794 }
 795
 796 void dwc_ahsata_flush_cache_ext(int dev)
 797 {
 798         struct ahci_probe_ent *probe_ent =
 799                 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 800         struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 801         struct sata_fis_h2d *cfis = &h2d;
 802         u8 port = probe_ent->hard_port_no;
 803
 804         memset(cfis, 0, sizeof(struct sata_fis_h2d));
 805
 806         cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 807         cfis->pm_port_c = 0x80; /* is command */
 808         cfis->command = ATA_CMD_FLUSH_EXT;
 809
 810         ahci_exec_ata_cmd(probe_ent, port, cfis, NULL, 0, 0);
 811 }
 812
 813 static void dwc_ahsata_init_wcache(int dev, u16 *id)
 814 {
 815         struct ahci_probe_ent *probe_ent =
 816                 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 817
 818         if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
 819                 probe_ent->flags |= SATA_FLAG_WCACHE;
 820         if (ata_id_has_flush(id))
 821                 probe_ent->flags |= SATA_FLAG_FLUSH;
 822         if (ata_id_has_flush_ext(id))
 823                 probe_ent->flags |= SATA_FLAG_FLUSH_EXT;
 824 }
 825
 826 u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
 827                                 const void *buffer, int is_write)
 828 {
 829         u32 start, blks;
 830         u8 *addr;
 831         int max_blks;
 832
 833         start = blknr;
 834         blks = blkcnt;
 835         addr = (u8 *)buffer;
 836
 837         max_blks = ATA_MAX_SECTORS_LBA48;
 838
 839         do {
 840                 if (blks > max_blks) {
 841                         if (max_blks != dwc_ahsata_rw_cmd_ext(dev, start,
 842                                                 max_blks, addr, is_write))
 843                                 return 0;
 844                         start += max_blks;
 845                         blks -= max_blks;
 846                         addr += ATA_SECT_SIZE * max_blks;
 847                 } else {
 848                         if (blks != dwc_ahsata_rw_cmd_ext(dev, start,
 849                                                 blks, addr, is_write))
 850                                 return 0;
 851                         start += blks;
 852                         blks = 0;
 853                         addr += ATA_SECT_SIZE * blks;
 854                 }
 855         } while (blks != 0);
 856
 857         return blkcnt;
 858 }
 859
 860 u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
 861                                 const void *buffer, int is_write)
 862 {
 863         u32 start, blks;
 864         u8 *addr;
 865         int max_blks;
 866
 867         start = blknr;
 868         blks = blkcnt;
 869         addr = (u8 *)buffer;
 870
 871         max_blks = ATA_MAX_SECTORS;
 872         do {
 873                 if (blks > max_blks) {
 874                         if (max_blks != dwc_ahsata_rw_cmd(dev, start,
 875                                                 max_blks, addr, is_write))
 876                                 return 0;
 877                         start += max_blks;
 878                         blks -= max_blks;
 879                         addr += ATA_SECT_SIZE * max_blks;
 880                 } else {
 881                         if (blks != dwc_ahsata_rw_cmd(dev, start,
 882                                                 blks, addr, is_write))
 883                                 return 0;
 884                         start += blks;
 885                         blks = 0;
 886                         addr += ATA_SECT_SIZE * blks;
 887                 }
 888         } while (blks != 0);
 889
 890         return blkcnt;
 891 }
 892
 893 int sata_port_status(int dev, int port)
 894 {
 895         struct sata_port_regs *port_mmio;
 896         struct ahci_probe_ent *probe_ent = NULL;
 897
 898         if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
 899                 return -EINVAL;
 900
 901         if (sata_dev_desc[dev].priv == NULL)
 902                 return -ENODEV;
 903
 904         probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 905         port_mmio = (struct sata_port_regs *)probe_ent->port[port].port_mmio;
 906
 907         return readl(&(port_mmio->ssts)) & SATA_PORT_SSTS_DET_MASK;
 908 }
 909
 910 /*
 911  * SATA interface between low level driver and command layer
 912  */
 913 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
 914 {
 915         u32 rc;
 916
 917         if (sata_dev_desc[dev].lba48)
 918                 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
 919                                                 buffer, READ_CMD);
 920         else
 921                 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
 922                                                 buffer, READ_CMD);
 923         return rc;
 924 }
 925
 926 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
 927 {
 928         u32 rc;
 929         struct ahci_probe_ent *probe_ent =
 930                 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 931         u32 flags = probe_ent->flags;
 932
 933         if (sata_dev_desc[dev].lba48) {
 934                 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt,
 935                                                 buffer, WRITE_CMD);
 936                 if ((flags & SATA_FLAG_WCACHE) &&
 937                         (flags & SATA_FLAG_FLUSH_EXT))
 938                         dwc_ahsata_flush_cache_ext(dev);
 939         } else {
 940                 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt,
 941                                                 buffer, WRITE_CMD);
 942                 if ((flags & SATA_FLAG_WCACHE) &&
 943                         (flags & SATA_FLAG_FLUSH))
 944                         dwc_ahsata_flush_cache(dev);
 945         }
 946         return rc;
 947 }
 948
 949 int scan_sata(int dev)
 950 {
 951         u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
 952         u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
 953         u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
 954         u16 *id;
 955         u64 n_sectors;
 956         struct ahci_probe_ent *probe_ent =
 957                 (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
 958         u8 port = probe_ent->hard_port_no;
 959         struct blk_desc *pdev = &(sata_dev_desc[dev]);
 960
 961         id = (u16 *)memalign(ARCH_DMA_MINALIGN,
 962                                 roundup(ARCH_DMA_MINALIGN,
 963                                         (ATA_ID_WORDS * 2)));
 964         if (!id) {
 965                 printf("id malloc failed\n\r");
 966                 return -1;
 967         }
 968
 969         /* Identify device to get information */
 970         dwc_ahsata_identify(dev, id);
 971
 972         /* Serial number */
 973         ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
 974         memcpy(pdev->product, serial, sizeof(serial));
 975
 976         /* Firmware version */
 977         ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
 978         memcpy(pdev->revision, firmware, sizeof(firmware));
 979
 980         /* Product model */
 981         ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
 982         memcpy(pdev->vendor, product, sizeof(product));
 983
 984         /* Totoal sectors */
 985         n_sectors = ata_id_n_sectors(id);
 986         pdev->lba = (u32)n_sectors;
 987
 988         pdev->type = DEV_TYPE_HARDDISK;
 989         pdev->blksz = ATA_SECT_SIZE;
 990         pdev->lun = 0 ;
 991
 992         /* Check if support LBA48 */
 993         if (ata_id_has_lba48(id)) {
 994                 pdev->lba48 = 1;
 995                 debug("Device support LBA48\n\r");
 996         }
 997
 998         /* Get the NCQ queue depth from device */
 999         probe_ent->flags &= (~SATA_FLAG_Q_DEP_MASK);
1000         probe_ent->flags |= ata_id_queue_depth(id);
1001
1002         /* Get the xfer mode from device */
1003         dwc_ahsata_xfer_mode(dev, id);
1004
1005         /* Get the write cache status from device */
1006         dwc_ahsata_init_wcache(dev, id);
1007
1008         /* Set the xfer mode to highest speed */
1009         ahci_set_feature(dev, port);
1010
1011         free((void *)id);
1012
1013         dwc_ahsata_print_info(dev);
1014
1015         is_ready = 1;
1016
1017         return 0;
1018 }