2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 * with the reference on libata and ahci drvier in kernel
14 #include <asm/processor.h>
15 #include <asm/errno.h>
21 #include <linux/ctype.h>
24 static int ata_io_flush(u8 port
);
26 struct ahci_probe_ent
*probe_ent
= NULL
;
27 u16
*ataid
[AHCI_MAX_PORTS
];
29 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
32 * Some controllers limit number of blocks they can read/write at once.
33 * Contemporary SSD devices work much faster if the read/write size is aligned
34 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
37 #ifndef MAX_SATA_BLOCKS_READ_WRITE
38 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
41 /* Maximum timeouts for each event */
42 #define WAIT_MS_SPINUP 20000
43 #define WAIT_MS_DATAIO 10000
44 #define WAIT_MS_FLUSH 5000
45 #define WAIT_MS_LINKUP 200
47 static inline void __iomem
*ahci_port_base(void __iomem
*base
, u32 port
)
49 return base
+ 0x100 + (port
* 0x80);
53 static void ahci_setup_port(struct ahci_ioports
*port
, void __iomem
*base
,
54 unsigned int port_idx
)
56 base
= ahci_port_base(base
, port_idx
);
58 port
->cmd_addr
= base
;
59 port
->scr_addr
= base
+ PORT_SCR
;
63 #define msleep(a) udelay(a * 1000)
65 static void ahci_dcache_flush_range(unsigned long begin
, unsigned long len
)
67 const unsigned long start
= begin
;
68 const unsigned long end
= start
+ len
;
70 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__
, start
, end
);
71 flush_dcache_range(start
, end
);
75 * SATA controller DMAs to physical RAM. Ensure data from the
76 * controller is invalidated from dcache; next access comes from
79 static void ahci_dcache_invalidate_range(unsigned long begin
, unsigned long len
)
81 const unsigned long start
= begin
;
82 const unsigned long end
= start
+ len
;
84 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__
, start
, end
);
85 invalidate_dcache_range(start
, end
);
89 * Ensure data for SATA controller is flushed out of dcache and
90 * written to physical memory.
92 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports
*pp
)
94 ahci_dcache_flush_range((unsigned long)pp
->cmd_slot
,
95 AHCI_PORT_PRIV_DMA_SZ
);
98 static int waiting_for_cmd_completed(void __iomem
*offset
,
105 for (i
= 0; ((status
= readl(offset
)) & sign
) && i
< timeout_msec
; i
++)
108 return (i
< timeout_msec
) ? 0 : -1;
111 int __weak
ahci_link_up(struct ahci_probe_ent
*probe_ent
, u8 port
)
115 void __iomem
*port_mmio
= probe_ent
->port
[port
].port_mmio
;
118 * Bring up SATA link.
119 * SATA link bringup time is usually less than 1 ms; only very
120 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
122 while (j
< WAIT_MS_LINKUP
) {
123 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
124 tmp
&= PORT_SCR_STAT_DET_MASK
;
125 if (tmp
== PORT_SCR_STAT_DET_PHYRDY
)
133 #ifdef CONFIG_SUNXI_AHCI
134 /* The sunxi AHCI controller requires this undocumented setup */
135 static void sunxi_dma_init(void __iomem
*port_mmio
)
137 clrsetbits_le32(port_mmio
+ PORT_P0DMACR
, 0x0000ff00, 0x00004400);
141 int ahci_reset(void __iomem
*base
)
144 u32 __iomem
*host_ctl_reg
= base
+ HOST_CTL
;
145 u32 tmp
= readl(host_ctl_reg
); /* global controller reset */
147 if ((tmp
& HOST_RESET
) == 0)
148 writel_with_flush(tmp
| HOST_RESET
, host_ctl_reg
);
151 * reset must complete within 1 second, or
152 * the hardware should be considered fried.
156 tmp
= readl(host_ctl_reg
);
158 } while ((i
> 0) && (tmp
& HOST_RESET
));
161 printf("controller reset failed (0x%x)\n", tmp
);
168 static int ahci_host_init(struct ahci_probe_ent
*probe_ent
)
170 #ifndef CONFIG_SCSI_AHCI_PLAT
171 pci_dev_t pdev
= probe_ent
->dev
;
173 unsigned short vendor
;
175 void __iomem
*mmio
= probe_ent
->mmio_base
;
176 u32 tmp
, cap_save
, cmd
;
178 void __iomem
*port_mmio
;
181 debug("ahci_host_init: start\n");
183 cap_save
= readl(mmio
+ HOST_CAP
);
184 cap_save
&= ((1 << 28) | (1 << 17));
185 cap_save
|= (1 << 27); /* Staggered Spin-up. Not needed. */
187 ret
= ahci_reset(probe_ent
->mmio_base
);
191 writel_with_flush(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
192 writel(cap_save
, mmio
+ HOST_CAP
);
193 writel_with_flush(0xf, mmio
+ HOST_PORTS_IMPL
);
195 #ifndef CONFIG_SCSI_AHCI_PLAT
196 pci_read_config_word(pdev
, PCI_VENDOR_ID
, &vendor
);
198 if (vendor
== PCI_VENDOR_ID_INTEL
) {
200 pci_read_config_word(pdev
, 0x92, &tmp16
);
202 pci_write_config_word(pdev
, 0x92, tmp16
);
205 probe_ent
->cap
= readl(mmio
+ HOST_CAP
);
206 probe_ent
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
207 port_map
= probe_ent
->port_map
;
208 probe_ent
->n_ports
= (probe_ent
->cap
& 0x1f) + 1;
210 debug("cap 0x%x port_map 0x%x n_ports %d\n",
211 probe_ent
->cap
, probe_ent
->port_map
, probe_ent
->n_ports
);
213 if (probe_ent
->n_ports
> CONFIG_SYS_SCSI_MAX_SCSI_ID
)
214 probe_ent
->n_ports
= CONFIG_SYS_SCSI_MAX_SCSI_ID
;
216 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
217 if (!(port_map
& (1 << i
)))
219 probe_ent
->port
[i
].port_mmio
= ahci_port_base(mmio
, i
);
220 port_mmio
= (u8
*) probe_ent
->port
[i
].port_mmio
;
221 ahci_setup_port(&probe_ent
->port
[i
], mmio
, i
);
223 /* make sure port is not active */
224 tmp
= readl(port_mmio
+ PORT_CMD
);
225 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
226 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
227 debug("Port %d is active. Deactivating.\n", i
);
228 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
229 PORT_CMD_FIS_RX
| PORT_CMD_START
);
230 writel_with_flush(tmp
, port_mmio
+ PORT_CMD
);
232 /* spec says 500 msecs for each bit, so
233 * this is slightly incorrect.
238 #ifdef CONFIG_SUNXI_AHCI
239 sunxi_dma_init(port_mmio
);
242 /* Add the spinup command to whatever mode bits may
243 * already be on in the command register.
245 cmd
= readl(port_mmio
+ PORT_CMD
);
246 cmd
|= PORT_CMD_SPIN_UP
;
247 writel_with_flush(cmd
, port_mmio
+ PORT_CMD
);
249 /* Bring up SATA link. */
250 ret
= ahci_link_up(probe_ent
, i
);
252 printf("SATA link %d timeout.\n", i
);
255 debug("SATA link ok.\n");
258 /* Clear error status */
259 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
261 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
263 debug("Spinning up device on SATA port %d... ", i
);
266 while (j
< WAIT_MS_SPINUP
) {
267 tmp
= readl(port_mmio
+ PORT_TFDATA
);
268 if (!(tmp
& (ATA_BUSY
| ATA_DRQ
)))
271 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
272 tmp
&= PORT_SCR_STAT_DET_MASK
;
273 if (tmp
== PORT_SCR_STAT_DET_PHYRDY
)
278 tmp
= readl(port_mmio
+ PORT_SCR_STAT
) & PORT_SCR_STAT_DET_MASK
;
279 if (tmp
== PORT_SCR_STAT_DET_COMINIT
) {
280 debug("SATA link %d down (COMINIT received), retrying...\n", i
);
285 printf("Target spinup took %d ms.\n", j
);
286 if (j
== WAIT_MS_SPINUP
)
291 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
292 debug("PORT_SCR_ERR 0x%x\n", tmp
);
293 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
295 /* ack any pending irq events for this port */
296 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
297 debug("PORT_IRQ_STAT 0x%x\n", tmp
);
299 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
301 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
303 /* register linkup ports */
304 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
305 debug("SATA port %d status: 0x%x\n", i
, tmp
);
306 if ((tmp
& PORT_SCR_STAT_DET_MASK
) == PORT_SCR_STAT_DET_PHYRDY
)
307 probe_ent
->link_port_map
|= (0x01 << i
);
310 tmp
= readl(mmio
+ HOST_CTL
);
311 debug("HOST_CTL 0x%x\n", tmp
);
312 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
313 tmp
= readl(mmio
+ HOST_CTL
);
314 debug("HOST_CTL 0x%x\n", tmp
);
315 #ifndef CONFIG_SCSI_AHCI_PLAT
316 pci_read_config_word(pdev
, PCI_COMMAND
, &tmp16
);
317 tmp
|= PCI_COMMAND_MASTER
;
318 pci_write_config_word(pdev
, PCI_COMMAND
, tmp16
);
324 static void ahci_print_info(struct ahci_probe_ent
*probe_ent
)
326 #ifndef CONFIG_SCSI_AHCI_PLAT
327 pci_dev_t pdev
= probe_ent
->dev
;
330 void __iomem
*mmio
= probe_ent
->mmio_base
;
331 u32 vers
, cap
, cap2
, impl
, speed
;
335 vers
= readl(mmio
+ HOST_VERSION
);
336 cap
= probe_ent
->cap
;
337 cap2
= readl(mmio
+ HOST_CAP2
);
338 impl
= probe_ent
->port_map
;
340 speed
= (cap
>> 20) & 0xf;
350 #ifdef CONFIG_SCSI_AHCI_PLAT
353 pci_read_config_word(pdev
, 0x0a, &cc
);
356 else if (cc
== 0x0106)
358 else if (cc
== 0x0104)
363 printf("AHCI %02x%02x.%02x%02x "
364 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
369 ((cap
>> 8) & 0x1f) + 1, (cap
& 0x1f) + 1, speed_s
, impl
, scc_s
);
375 cap
& (1 << 31) ? "64bit " : "",
376 cap
& (1 << 30) ? "ncq " : "",
377 cap
& (1 << 28) ? "ilck " : "",
378 cap
& (1 << 27) ? "stag " : "",
379 cap
& (1 << 26) ? "pm " : "",
380 cap
& (1 << 25) ? "led " : "",
381 cap
& (1 << 24) ? "clo " : "",
382 cap
& (1 << 19) ? "nz " : "",
383 cap
& (1 << 18) ? "only " : "",
384 cap
& (1 << 17) ? "pmp " : "",
385 cap
& (1 << 16) ? "fbss " : "",
386 cap
& (1 << 15) ? "pio " : "",
387 cap
& (1 << 14) ? "slum " : "",
388 cap
& (1 << 13) ? "part " : "",
389 cap
& (1 << 7) ? "ccc " : "",
390 cap
& (1 << 6) ? "ems " : "",
391 cap
& (1 << 5) ? "sxs " : "",
392 cap2
& (1 << 2) ? "apst " : "",
393 cap2
& (1 << 1) ? "nvmp " : "",
394 cap2
& (1 << 0) ? "boh " : "");
397 #ifndef CONFIG_SCSI_AHCI_PLAT
398 static int ahci_init_one(pci_dev_t pdev
)
403 probe_ent
= malloc(sizeof(struct ahci_probe_ent
));
405 printf("%s: No memory for probe_ent\n", __func__
);
409 memset(probe_ent
, 0, sizeof(struct ahci_probe_ent
));
410 probe_ent
->dev
= pdev
;
412 probe_ent
->host_flags
= ATA_FLAG_SATA
417 probe_ent
->pio_mask
= 0x1f;
418 probe_ent
->udma_mask
= 0x7f; /*Fixme,assume to support UDMA6 */
420 probe_ent
->mmio_base
= pci_map_bar(pdev
, PCI_BASE_ADDRESS_5
,
422 debug("ahci mmio_base=0x%p\n", probe_ent
->mmio_base
);
425 * JMicron-specific fixup:
426 * make sure we're in AHCI mode
428 pci_read_config_word(pdev
, PCI_VENDOR_ID
, &vendor
);
429 if (vendor
== 0x197b)
430 pci_write_config_byte(pdev
, 0x41, 0xa1);
432 /* initialize adapter */
433 rc
= ahci_host_init(probe_ent
);
437 ahci_print_info(probe_ent
);
446 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
448 static int ahci_fill_sg(u8 port
, unsigned char *buf
, int buf_len
)
450 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
451 struct ahci_sg
*ahci_sg
= pp
->cmd_tbl_sg
;
455 sg_count
= ((buf_len
- 1) / MAX_DATA_BYTE_COUNT
) + 1;
456 if (sg_count
> AHCI_MAX_SG
) {
457 printf("Error:Too much sg!\n");
461 for (i
= 0; i
< sg_count
; i
++) {
463 cpu_to_le32((unsigned long) buf
+ i
* MAX_DATA_BYTE_COUNT
);
464 ahci_sg
->addr_hi
= 0;
465 ahci_sg
->flags_size
= cpu_to_le32(0x3fffff &
466 (buf_len
< MAX_DATA_BYTE_COUNT
468 : (MAX_DATA_BYTE_COUNT
- 1)));
470 buf_len
-= MAX_DATA_BYTE_COUNT
;
477 static void ahci_fill_cmd_slot(struct ahci_ioports
*pp
, u32 opts
)
479 pp
->cmd_slot
->opts
= cpu_to_le32(opts
);
480 pp
->cmd_slot
->status
= 0;
481 pp
->cmd_slot
->tbl_addr
= cpu_to_le32((u32
)pp
->cmd_tbl
& 0xffffffff);
482 #ifdef CONFIG_PHYS_64BIT
483 pp
->cmd_slot
->tbl_addr_hi
=
484 cpu_to_le32((u32
)(((pp
->cmd_tbl
) >> 16) >> 16));
488 static int wait_spinup(void __iomem
*port_mmio
)
493 start
= get_timer(0);
495 tf_data
= readl(port_mmio
+ PORT_TFDATA
);
496 if (!(tf_data
& ATA_BUSY
))
498 } while (get_timer(start
) < WAIT_MS_SPINUP
);
503 static int ahci_port_start(u8 port
)
505 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
506 void __iomem
*port_mmio
= pp
->port_mmio
;
510 debug("Enter start port: %d\n", port
);
511 port_status
= readl(port_mmio
+ PORT_SCR_STAT
);
512 debug("Port %d status: %x\n", port
, port_status
);
513 if ((port_status
& 0xf) != 0x03) {
514 printf("No Link on this port!\n");
518 mem
= malloc(AHCI_PORT_PRIV_DMA_SZ
+ 2048);
521 printf("%s: No mem for table!\n", __func__
);
525 /* Aligned to 2048-bytes */
526 mem
= memalign(2048, AHCI_PORT_PRIV_DMA_SZ
);
527 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
530 * First item in chunk of DMA memory: 32-slot command table,
531 * 32 bytes each in size
534 (struct ahci_cmd_hdr
*)(uintptr_t)virt_to_phys((void *)mem
);
535 debug("cmd_slot = %p\n", pp
->cmd_slot
);
536 mem
+= (AHCI_CMD_SLOT_SZ
+ 224);
539 * Second item: Received-FIS area
541 pp
->rx_fis
= virt_to_phys((void *)mem
);
542 mem
+= AHCI_RX_FIS_SZ
;
545 * Third item: data area for storing a single command
546 * and its scatter-gather table
548 pp
->cmd_tbl
= virt_to_phys((void *)mem
);
549 debug("cmd_tbl_dma = %lx\n", pp
->cmd_tbl
);
551 mem
+= AHCI_CMD_TBL_HDR
;
553 (struct ahci_sg
*)(uintptr_t)virt_to_phys((void *)mem
);
555 writel_with_flush((unsigned long)pp
->cmd_slot
,
556 port_mmio
+ PORT_LST_ADDR
);
558 writel_with_flush(pp
->rx_fis
, port_mmio
+ PORT_FIS_ADDR
);
560 #ifdef CONFIG_SUNXI_AHCI
561 sunxi_dma_init(port_mmio
);
564 writel_with_flush(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
565 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
566 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
568 debug("Exit start port %d\n", port
);
571 * Make sure interface is not busy based on error and status
572 * information from task file data register before proceeding
574 return wait_spinup(port_mmio
);
578 static int ahci_device_data_io(u8 port
, u8
*fis
, int fis_len
, u8
*buf
,
579 int buf_len
, u8 is_write
)
582 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
583 void __iomem
*port_mmio
= pp
->port_mmio
;
588 debug("Enter %s: for port %d\n", __func__
, port
);
590 if (port
> probe_ent
->n_ports
) {
591 printf("Invalid port number %d\n", port
);
595 port_status
= readl(port_mmio
+ PORT_SCR_STAT
);
596 if ((port_status
& 0xf) != 0x03) {
597 debug("No Link on port %d!\n", port
);
601 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, fis_len
);
603 sg_count
= ahci_fill_sg(port
, buf
, buf_len
);
604 opts
= (fis_len
>> 2) | (sg_count
<< 16) | (is_write
<< 6);
605 ahci_fill_cmd_slot(pp
, opts
);
607 ahci_dcache_flush_sata_cmd(pp
);
608 ahci_dcache_flush_range((unsigned long)buf
, (unsigned long)buf_len
);
610 writel_with_flush(1, port_mmio
+ PORT_CMD_ISSUE
);
612 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
613 WAIT_MS_DATAIO
, 0x1)) {
614 printf("timeout exit!\n");
618 ahci_dcache_invalidate_range((unsigned long)buf
,
619 (unsigned long)buf_len
);
620 debug("%s: %d byte transferred.\n", __func__
, pp
->cmd_slot
->status
);
626 static char *ata_id_strcpy(u16
*target
, u16
*src
, int len
)
629 for (i
= 0; i
< len
/ 2; i
++)
630 target
[i
] = swab16(src
[i
]);
631 return (char *)target
;
635 * SCSI INQUIRY command operation.
637 static int ata_scsiop_inquiry(ccb
*pccb
)
639 static const u8 hdr
[] = {
642 0x5, /* claim SPC-3 version compatibility */
648 ALLOC_CACHE_ALIGN_BUFFER(u16
, tmpid
, ATA_ID_WORDS
);
651 /* Clean ccb data buffer */
652 memset(pccb
->pdata
, 0, pccb
->datalen
);
654 memcpy(pccb
->pdata
, hdr
, sizeof(hdr
));
656 if (pccb
->datalen
<= 35)
659 memset(fis
, 0, sizeof(fis
));
660 /* Construct the FIS */
661 fis
[0] = 0x27; /* Host to device FIS. */
662 fis
[1] = 1 << 7; /* Command FIS. */
663 fis
[2] = ATA_CMD_ID_ATA
; /* Command byte. */
665 /* Read id from sata */
668 if (ahci_device_data_io(port
, (u8
*) &fis
, sizeof(fis
), (u8
*)tmpid
,
669 ATA_ID_WORDS
* 2, 0)) {
670 debug("scsi_ahci: SCSI inquiry command failure.\n");
675 ataid
[port
] = malloc(ATA_ID_WORDS
* 2);
677 printf("%s: No memory for ataid[port]\n", __func__
);
684 memcpy(idbuf
, tmpid
, ATA_ID_WORDS
* 2);
685 ata_swap_buf_le16(idbuf
, ATA_ID_WORDS
);
687 memcpy(&pccb
->pdata
[8], "ATA ", 8);
688 ata_id_strcpy((u16
*)&pccb
->pdata
[16], &idbuf
[ATA_ID_PROD
], 16);
689 ata_id_strcpy((u16
*)&pccb
->pdata
[32], &idbuf
[ATA_ID_FW_REV
], 4);
699 * SCSI READ10/WRITE10 command operation.
701 static int ata_scsiop_read_write(ccb
*pccb
, u8 is_write
)
706 u8
*user_buffer
= pccb
->pdata
;
707 u32 user_buffer_size
= pccb
->datalen
;
709 /* Retrieve the base LBA number from the ccb structure. */
710 if (pccb
->cmd
[0] == SCSI_READ16
) {
711 memcpy(&lba
, pccb
->cmd
+ 2, 8);
712 lba
= be64_to_cpu(lba
);
715 memcpy(&temp
, pccb
->cmd
+ 2, 4);
716 lba
= be32_to_cpu(temp
);
720 * Retrieve the base LBA number and the block count from
723 * For 10-byte and 16-byte SCSI R/W commands, transfer
724 * length 0 means transfer 0 block of data.
725 * However, for ATA R/W commands, sector count 0 means
726 * 256 or 65536 sectors, not 0 sectors as in SCSI.
728 * WARNING: one or two older ATA drives treat 0 as 0...
730 if (pccb
->cmd
[0] == SCSI_READ16
)
731 blocks
= (((u16
)pccb
->cmd
[13]) << 8) | ((u16
) pccb
->cmd
[14]);
733 blocks
= (((u16
)pccb
->cmd
[7]) << 8) | ((u16
) pccb
->cmd
[8]);
735 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU
"\n",
736 is_write
? "write" : "read", blocks
, lba
);
739 memset(fis
, 0, sizeof(fis
));
740 fis
[0] = 0x27; /* Host to device FIS. */
741 fis
[1] = 1 << 7; /* Command FIS. */
742 /* Command byte (read/write). */
743 fis
[2] = is_write
? ATA_CMD_WRITE_EXT
: ATA_CMD_READ_EXT
;
746 u16 now_blocks
; /* number of blocks per iteration */
747 u32 transfer_size
; /* number of bytes per iteration */
749 now_blocks
= min((u16
)MAX_SATA_BLOCKS_READ_WRITE
, blocks
);
751 transfer_size
= ATA_SECT_SIZE
* now_blocks
;
752 if (transfer_size
> user_buffer_size
) {
753 printf("scsi_ahci: Error: buffer too small.\n");
758 * LBA48 SATA command but only use 32bit address range within
759 * that (unless we've enabled 64bit LBA support). The next
760 * smaller command range (28bit) is too small.
762 fis
[4] = (lba
>> 0) & 0xff;
763 fis
[5] = (lba
>> 8) & 0xff;
764 fis
[6] = (lba
>> 16) & 0xff;
765 fis
[7] = 1 << 6; /* device reg: set LBA mode */
766 fis
[8] = ((lba
>> 24) & 0xff);
767 #ifdef CONFIG_SYS_64BIT_LBA
768 if (pccb
->cmd
[0] == SCSI_READ16
) {
769 fis
[9] = ((lba
>> 32) & 0xff);
770 fis
[10] = ((lba
>> 40) & 0xff);
774 fis
[3] = 0xe0; /* features */
776 /* Block (sector) count */
777 fis
[12] = (now_blocks
>> 0) & 0xff;
778 fis
[13] = (now_blocks
>> 8) & 0xff;
780 /* Read/Write from ahci */
781 if (ahci_device_data_io(pccb
->target
, (u8
*) &fis
, sizeof(fis
),
782 user_buffer
, transfer_size
,
784 debug("scsi_ahci: SCSI %s10 command failure.\n",
785 is_write
? "WRITE" : "READ");
789 /* If this transaction is a write, do a following flush.
790 * Writes in u-boot are so rare, and the logic to know when is
791 * the last write and do a flush only there is sufficiently
792 * difficult. Just do a flush after every write. This incurs,
793 * usually, one extra flush when the rare writes do happen.
796 if (-EIO
== ata_io_flush(pccb
->target
))
799 user_buffer
+= transfer_size
;
800 user_buffer_size
-= transfer_size
;
801 blocks
-= now_blocks
;
810 * SCSI READ CAPACITY10 command operation.
812 static int ata_scsiop_read_capacity10(ccb
*pccb
)
818 if (!ataid
[pccb
->target
]) {
819 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
821 "\tPlease run SCSI commmand INQUIRY firstly!\n");
825 cap64
= ata_id_n_sectors(ataid
[pccb
->target
]);
826 if (cap64
> 0x100000000ULL
)
829 cap
= cpu_to_be32(cap64
);
830 memcpy(pccb
->pdata
, &cap
, sizeof(cap
));
832 block_size
= cpu_to_be32((u32
)512);
833 memcpy(&pccb
->pdata
[4], &block_size
, 4);
840 * SCSI READ CAPACITY16 command operation.
842 static int ata_scsiop_read_capacity16(ccb
*pccb
)
847 if (!ataid
[pccb
->target
]) {
848 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
850 "\tPlease run SCSI commmand INQUIRY firstly!\n");
854 cap
= ata_id_n_sectors(ataid
[pccb
->target
]);
855 cap
= cpu_to_be64(cap
);
856 memcpy(pccb
->pdata
, &cap
, sizeof(cap
));
858 block_size
= cpu_to_be64((u64
)512);
859 memcpy(&pccb
->pdata
[8], &block_size
, 8);
866 * SCSI TEST UNIT READY command operation.
868 static int ata_scsiop_test_unit_ready(ccb
*pccb
)
870 return (ataid
[pccb
->target
]) ? 0 : -EPERM
;
874 int scsi_exec(ccb
*pccb
)
878 switch (pccb
->cmd
[0]) {
881 ret
= ata_scsiop_read_write(pccb
, 0);
884 ret
= ata_scsiop_read_write(pccb
, 1);
886 case SCSI_RD_CAPAC10
:
887 ret
= ata_scsiop_read_capacity10(pccb
);
889 case SCSI_RD_CAPAC16
:
890 ret
= ata_scsiop_read_capacity16(pccb
);
893 ret
= ata_scsiop_test_unit_ready(pccb
);
896 ret
= ata_scsiop_inquiry(pccb
);
899 printf("Unsupport SCSI command 0x%02x\n", pccb
->cmd
[0]);
904 debug("SCSI command 0x%02x ret errno %d\n", pccb
->cmd
[0], ret
);
912 void scsi_low_level_init(int busdevfunc
)
917 #ifndef CONFIG_SCSI_AHCI_PLAT
918 ahci_init_one(busdevfunc
);
921 linkmap
= probe_ent
->link_port_map
;
923 for (i
= 0; i
< CONFIG_SYS_SCSI_MAX_SCSI_ID
; i
++) {
924 if (((linkmap
>> i
) & 0x01)) {
925 if (ahci_port_start((u8
) i
)) {
926 printf("Can not start port %d\n", i
);
933 #ifdef CONFIG_SCSI_AHCI_PLAT
934 int ahci_init(void __iomem
*base
)
939 probe_ent
= malloc(sizeof(struct ahci_probe_ent
));
941 printf("%s: No memory for probe_ent\n", __func__
);
945 memset(probe_ent
, 0, sizeof(struct ahci_probe_ent
));
947 probe_ent
->host_flags
= ATA_FLAG_SATA
952 probe_ent
->pio_mask
= 0x1f;
953 probe_ent
->udma_mask
= 0x7f; /*Fixme,assume to support UDMA6 */
955 probe_ent
->mmio_base
= base
;
957 /* initialize adapter */
958 rc
= ahci_host_init(probe_ent
);
962 ahci_print_info(probe_ent
);
964 linkmap
= probe_ent
->link_port_map
;
966 for (i
= 0; i
< CONFIG_SYS_SCSI_MAX_SCSI_ID
; i
++) {
967 if (((linkmap
>> i
) & 0x01)) {
968 if (ahci_port_start((u8
) i
)) {
969 printf("Can not start port %d\n", i
);
978 void __weak
scsi_init(void)
985 * In the general case of generic rotating media it makes sense to have a
986 * flush capability. It probably even makes sense in the case of SSDs because
987 * one cannot always know for sure what kind of internal cache/flush mechanism
988 * is embodied therein. At first it was planned to invoke this after the last
989 * write to disk and before rebooting. In practice, knowing, a priori, which
990 * is the last write is difficult. Because writing to the disk in u-boot is
991 * very rare, this flush command will be invoked after every block write.
993 static int ata_io_flush(u8 port
)
996 struct ahci_ioports
*pp
= &(probe_ent
->port
[port
]);
997 void __iomem
*port_mmio
= pp
->port_mmio
;
998 u32 cmd_fis_len
= 5; /* five dwords */
1000 /* Preset the FIS */
1002 fis
[0] = 0x27; /* Host to device FIS. */
1003 fis
[1] = 1 << 7; /* Command FIS. */
1004 fis
[2] = ATA_CMD_FLUSH_EXT
;
1006 memcpy((unsigned char *)pp
->cmd_tbl
, fis
, 20);
1007 ahci_fill_cmd_slot(pp
, cmd_fis_len
);
1008 writel_with_flush(1, port_mmio
+ PORT_CMD_ISSUE
);
1010 if (waiting_for_cmd_completed(port_mmio
+ PORT_CMD_ISSUE
,
1011 WAIT_MS_FLUSH
, 0x1)) {
1012 debug("scsi_ahci: flush command timeout on port %d.\n", port
);
1020 __weak
void scsi_bus_reset(void)
1025 void scsi_print_error(ccb
* pccb
)
1027 /*The ahci error info can be read in the ahci driver*/