2 * Copyright (C) Procsys. All rights reserved.
3 * Author: Mushtaq Khan <mushtaq_k@procsys.com>
4 * <mushtaqk_921@yahoo.co.in>
6 * SPDX-License-Identifier: GPL-2.0+
8 * with the reference to ata_piix driver in kernel 2.4.32
12 * This file contains SATA controller and SATA drive initialization functions
20 #include <asm/byteorder.h>
26 #define DEBUG_SATA 0 /* For debug prints set DEBUG_SATA to 1 */
29 #define DRV_DECL /* For file specific declarations */
32 /* Macros realted to PCI */
33 #define PCI_SATA_BUS 0x00
34 #define PCI_SATA_DEV 0x1f
35 #define PCI_SATA_FUNC 0x02
37 #define PCI_SATA_BASE1 0x10
38 #define PCI_SATA_BASE2 0x14
39 #define PCI_SATA_BASE3 0x18
40 #define PCI_SATA_BASE4 0x1c
41 #define PCI_SATA_BASE5 0x20
45 #define PCI_DMA_CTL 0x48
47 #define PORT_PRESENT (1<<0)
48 #define PORT_ENABLED (1<<4)
51 u32 iobase1
; /* Primary cmd block */
52 u32 iobase2
; /* Primary ctl block */
53 u32 iobase3
; /* Sec cmd block */
54 u32 iobase4
; /* sec ctl block */
55 u32 iobase5
; /* BMDMA*/
57 int pci_sata_init(void)
59 u32 bus
= PCI_SATA_BUS
;
60 u32 dev
= PCI_SATA_DEV
;
61 u32 fun
= PCI_SATA_FUNC
;
63 u8 lat
= 0, pcibios_max_latency
= 0xff;
64 u8 pmr
; /* Port mapping reg */
65 u8 pi
; /* Prgming Interface reg */
67 bdf
= PCI_BDF(bus
, dev
, fun
);
68 pci_read_config_dword(bdf
, PCI_SATA_BASE1
, &iobase1
);
69 pci_read_config_dword(bdf
, PCI_SATA_BASE2
, &iobase2
);
70 pci_read_config_dword(bdf
, PCI_SATA_BASE3
, &iobase3
);
71 pci_read_config_dword(bdf
, PCI_SATA_BASE4
, &iobase4
);
72 pci_read_config_dword(bdf
, PCI_SATA_BASE5
, &iobase5
);
74 if ((iobase1
== 0xFFFFFFFF) || (iobase2
== 0xFFFFFFFF) ||
75 (iobase3
== 0xFFFFFFFF) || (iobase4
== 0xFFFFFFFF) ||
76 (iobase5
== 0xFFFFFFFF)) {
78 printf("error no base addr for SATA controller\n");
82 iobase1
&= 0xFFFFFFFE;
83 iobase2
&= 0xFFFFFFFE;
84 iobase3
&= 0xFFFFFFFE;
85 iobase4
&= 0xFFFFFFFE;
86 iobase5
&= 0xFFFFFFFE;
89 pci_read_config_byte(bdf
, PCI_PMR
, &pmr
);
91 puts("combined mode not supported\n");
95 pci_read_config_byte(bdf
, PCI_PI
, &pi
);
96 if ((pi
& 0x05) != 0x05) {
97 puts("Sata is in Legacy mode\n");
100 puts("sata is in Native mode\n");
102 /* MASTER CFG AND IO CFG */
103 pci_read_config_word(bdf
, PCI_COMMAND
, &cmd
);
104 cmd
|= PCI_COMMAND_MASTER
| PCI_COMMAND_IO
;
105 pci_write_config_word(bdf
, PCI_COMMAND
, cmd
);
106 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
109 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
110 else if (lat
> pcibios_max_latency
)
111 lat
= pcibios_max_latency
;
112 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
117 int sata_bus_probe(int port_no
)
122 mask
= (PORT_PRESENT
<< port_no
);
123 pci_read_config_word(bdf
, PCI_PCS
, &pcs
);
124 orig_mask
= (int) pcs
& 0xff;
125 if ((orig_mask
& mask
) != mask
)
131 int init_sata(int dev
)
141 rv
= pci_sata_init();
143 puts("pci initialization failed\n");
148 port
[0].ioaddr
.cmd_addr
= iobase1
;
149 port
[0].ioaddr
.altstatus_addr
= port
[0].ioaddr
.ctl_addr
=
150 iobase2
| ATA_PCI_CTL_OFS
;
151 port
[0].ioaddr
.bmdma_addr
= iobase5
;
154 port
[1].ioaddr
.cmd_addr
= iobase3
;
155 port
[1].ioaddr
.altstatus_addr
= port
[1].ioaddr
.ctl_addr
=
156 iobase4
| ATA_PCI_CTL_OFS
;
157 port
[1].ioaddr
.bmdma_addr
= iobase5
+ 0x8;
159 for (i
= 0; i
< CONFIG_SYS_SATA_MAXBUS
; i
++)
160 sata_port(&port
[i
].ioaddr
);
162 for (i
= 0; i
< CONFIG_SYS_SATA_MAXBUS
; i
++) {
163 if (!(sata_bus_probe(i
))) {
164 port
[i
].port_state
= 0;
165 printf("SATA#%d port is not present\n", i
);
167 printf("SATA#%d port is present\n", i
);
168 if (sata_bus_softreset(i
))
169 port
[i
].port_state
= 0;
171 port
[i
].port_state
= 1;
175 for (i
= 0; i
< CONFIG_SYS_SATA_MAXBUS
; i
++) {
178 if (port
[i
].port_state
== 0)
180 for (j
= 0; j
< CONFIG_SYS_SATA_DEVS_PER_BUS
; j
++) {
182 set_Feature_cmd(i
, j
);
183 devno
= i
* CONFIG_SYS_SATA_DEVS_PER_BUS
+ j
;
184 if ((sata_dev_desc
[devno
].lba
> 0) &&
185 (sata_dev_desc
[devno
].blksz
> 0)) {
186 dev_print(&sata_dev_desc
[devno
]);
187 /* initialize partition type */
188 init_part(&sata_dev_desc
[devno
]);
195 static inline u8
sata_inb(unsigned long ioaddr
)
200 static inline void sata_outb(unsigned char val
, unsigned long ioaddr
)
205 static void output_data(struct sata_ioports
*ioaddr
, ulong
* sect_buf
,
208 outsw(ioaddr
->data_addr
, sect_buf
, words
<< 1);
211 static int input_data(struct sata_ioports
*ioaddr
, ulong
* sect_buf
, int words
)
213 insw(ioaddr
->data_addr
, sect_buf
, words
<< 1);
217 static void sata_cpy(unsigned char *dst
, unsigned char *src
, unsigned int len
)
219 unsigned char *end
, *last
;
224 /* reserve space for '\0' */
228 /* skip leading white space */
229 while ((*src
) && (src
< end
) && (*src
== ' '))
232 /* copy string, omitting trailing white space */
233 while ((*src
) && (src
< end
)) {
242 int sata_bus_softreset(int num
)
244 u8 dev
= 0, status
= 0, i
;
246 port
[num
].dev_mask
= 0;
248 for (i
= 0; i
< CONFIG_SYS_SATA_DEVS_PER_BUS
; i
++) {
249 if (!(sata_devchk(&port
[num
].ioaddr
, i
))) {
250 debug("dev_chk failed for dev#%d\n", i
);
252 port
[num
].dev_mask
|= (1 << i
);
253 debug("dev_chk passed for dev#%d\n", i
);
257 if (!(port
[num
].dev_mask
)) {
258 printf("no devices on port%d\n", num
);
262 dev_select(&port
[num
].ioaddr
, dev
);
264 port
[num
].ctl_reg
= 0x08; /* Default value of control reg */
265 sata_outb(port
[num
].ctl_reg
, port
[num
].ioaddr
.ctl_addr
);
267 sata_outb(port
[num
].ctl_reg
| ATA_SRST
, port
[num
].ioaddr
.ctl_addr
);
269 sata_outb(port
[num
].ctl_reg
, port
[num
].ioaddr
.ctl_addr
);
272 * spec mandates ">= 2ms" before checking status.
273 * We wait 150ms, because that was the magic delay used for
274 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
275 * between when the ATA command register is written, and then
276 * status is checked. Because waiting for "a while" before
277 * checking status is fine, post SRST, we perform this magic
278 * delay here as well.
281 status
= sata_busy_wait(&port
[num
].ioaddr
, ATA_BUSY
, 300);
282 while ((status
& ATA_BUSY
)) {
284 status
= sata_busy_wait(&port
[num
].ioaddr
, ATA_BUSY
, 3);
287 if (status
& ATA_BUSY
)
288 printf("ata%u is slow to respond,plz be patient\n", num
);
290 while ((status
& ATA_BUSY
)) {
292 status
= sata_chk_status(&port
[num
].ioaddr
);
295 if (status
& ATA_BUSY
) {
296 printf("ata%u failed to respond : bus reset failed\n", num
);
302 void sata_identify(int num
, int dev
)
304 u8 cmd
= 0, status
= 0;
305 u8 devno
= num
* CONFIG_SYS_SATA_DEVS_PER_BUS
+ dev
;
306 u16 iobuf
[ATA_SECT_SIZE
];
310 memset(iobuf
, 0, sizeof(iobuf
));
311 hd_driveid_t
*iop
= (hd_driveid_t
*) iobuf
;
318 if (!(port
[num
].dev_mask
& mask
)) {
319 printf("dev%d is not present on port#%d\n", dev
, num
);
323 printf("port=%d dev=%d\n", num
, dev
);
325 dev_select(&port
[num
].ioaddr
, dev
);
328 cmd
= ATA_CMD_IDENT
; /* Device Identify Command */
329 sata_outb(cmd
, port
[num
].ioaddr
.command_addr
);
330 sata_inb(port
[num
].ioaddr
.altstatus_addr
);
333 status
= sata_busy_wait(&port
[num
].ioaddr
, ATA_BUSY
, 1000);
334 if (status
& ATA_ERR
) {
335 puts("\ndevice not responding\n");
336 port
[num
].dev_mask
&= ~mask
;
340 input_data(&port
[num
].ioaddr
, (ulong
*) iobuf
, ATA_SECTORWORDS
);
342 debug("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
343 "86:%04x" "87:%04x 88:%04x\n", num
, dev
, iobuf
[49],
344 iobuf
[82], iobuf
[83], iobuf
[84], iobuf
[85], iobuf
[86],
345 iobuf
[87], iobuf
[88]);
347 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
348 if (!ata_id_has_dma(iobuf
) || !ata_id_has_lba(iobuf
))
349 debug("ata%u: no dma/lba\n", num
);
352 if (ata_id_has_lba48(iobuf
))
353 n_sectors
= ata_id_u64(iobuf
, 100);
355 n_sectors
= ata_id_u32(iobuf
, 60);
356 debug("no. of sectors %u\n", ata_id_u64(iobuf
, 100));
357 debug("no. of sectors %u\n", ata_id_u32(iobuf
, 60));
359 if (n_sectors
== 0) {
360 port
[num
].dev_mask
&= ~mask
;
364 sata_cpy((unsigned char *)sata_dev_desc
[devno
].revision
, iop
->fw_rev
,
365 sizeof(sata_dev_desc
[devno
].revision
));
366 sata_cpy((unsigned char *)sata_dev_desc
[devno
].vendor
, iop
->model
,
367 sizeof(sata_dev_desc
[devno
].vendor
));
368 sata_cpy((unsigned char *)sata_dev_desc
[devno
].product
, iop
->serial_no
,
369 sizeof(sata_dev_desc
[devno
].product
));
370 strswab(sata_dev_desc
[devno
].revision
);
371 strswab(sata_dev_desc
[devno
].vendor
);
373 if ((iop
->config
& 0x0080) == 0x0080)
374 sata_dev_desc
[devno
].removable
= 1;
376 sata_dev_desc
[devno
].removable
= 0;
378 sata_dev_desc
[devno
].lba
= iop
->lba_capacity
;
379 debug("lba=0x%x", sata_dev_desc
[devno
].lba
);
382 if (iop
->command_set_2
& 0x0400) {
383 sata_dev_desc
[devno
].lba48
= 1;
384 lba
= (unsigned long long) iop
->lba48_capacity
[0] |
385 ((unsigned long long) iop
->lba48_capacity
[1] << 16) |
386 ((unsigned long long) iop
->lba48_capacity
[2] << 32) |
387 ((unsigned long long) iop
->lba48_capacity
[3] << 48);
389 sata_dev_desc
[devno
].lba48
= 0;
394 sata_dev_desc
[devno
].type
= DEV_TYPE_HARDDISK
;
395 sata_dev_desc
[devno
].blksz
= ATA_BLOCKSIZE
;
396 sata_dev_desc
[devno
].log2blksz
= LOG2(sata_dev_desc
[devno
].blksz
);
397 sata_dev_desc
[devno
].lun
= 0; /* just to fill something in... */
400 void set_Feature_cmd(int num
, int dev
)
402 u8 mask
= 0x00, status
= 0;
409 if (!(port
[num
].dev_mask
& mask
)) {
410 debug("dev%d is not present on port#%d\n", dev
, num
);
414 dev_select(&port
[num
].ioaddr
, dev
);
416 sata_outb(SETFEATURES_XFER
, port
[num
].ioaddr
.feature_addr
);
417 sata_outb(XFER_PIO_4
, port
[num
].ioaddr
.nsect_addr
);
418 sata_outb(0, port
[num
].ioaddr
.lbal_addr
);
419 sata_outb(0, port
[num
].ioaddr
.lbam_addr
);
420 sata_outb(0, port
[num
].ioaddr
.lbah_addr
);
422 sata_outb(ATA_DEVICE_OBS
, port
[num
].ioaddr
.device_addr
);
423 sata_outb(ATA_CMD_SETF
, port
[num
].ioaddr
.command_addr
);
428 status
= sata_busy_wait(&port
[num
].ioaddr
, ATA_BUSY
, 5000);
429 if ((status
& (ATA_STAT_BUSY
| ATA_STAT_ERR
))) {
430 printf("Error : status 0x%02x\n", status
);
431 port
[num
].dev_mask
&= ~mask
;
435 void sata_port(struct sata_ioports
*ioport
)
437 ioport
->data_addr
= ioport
->cmd_addr
+ ATA_REG_DATA
;
438 ioport
->error_addr
= ioport
->cmd_addr
+ ATA_REG_ERR
;
439 ioport
->feature_addr
= ioport
->cmd_addr
+ ATA_REG_FEATURE
;
440 ioport
->nsect_addr
= ioport
->cmd_addr
+ ATA_REG_NSECT
;
441 ioport
->lbal_addr
= ioport
->cmd_addr
+ ATA_REG_LBAL
;
442 ioport
->lbam_addr
= ioport
->cmd_addr
+ ATA_REG_LBAM
;
443 ioport
->lbah_addr
= ioport
->cmd_addr
+ ATA_REG_LBAH
;
444 ioport
->device_addr
= ioport
->cmd_addr
+ ATA_REG_DEVICE
;
445 ioport
->status_addr
= ioport
->cmd_addr
+ ATA_REG_STATUS
;
446 ioport
->command_addr
= ioport
->cmd_addr
+ ATA_REG_CMD
;
449 int sata_devchk(struct sata_ioports
*ioaddr
, int dev
)
453 dev_select(ioaddr
, dev
);
455 sata_outb(0x55, ioaddr
->nsect_addr
);
456 sata_outb(0xaa, ioaddr
->lbal_addr
);
458 sata_outb(0xaa, ioaddr
->nsect_addr
);
459 sata_outb(0x55, ioaddr
->lbal_addr
);
461 sata_outb(0x55, ioaddr
->nsect_addr
);
462 sata_outb(0xaa, ioaddr
->lbal_addr
);
464 nsect
= sata_inb(ioaddr
->nsect_addr
);
465 lbal
= sata_inb(ioaddr
->lbal_addr
);
467 if ((nsect
== 0x55) && (lbal
== 0xaa))
468 return 1; /* we found a device */
470 return 0; /* nothing found */
473 void dev_select(struct sata_ioports
*ioaddr
, int dev
)
478 tmp
= ATA_DEVICE_OBS
;
480 tmp
= ATA_DEVICE_OBS
| ATA_DEV1
;
482 sata_outb(tmp
, ioaddr
->device_addr
);
483 sata_inb(ioaddr
->altstatus_addr
);
487 u8
sata_busy_wait(struct sata_ioports
*ioaddr
, int bits
, unsigned int max
)
493 status
= sata_chk_status(ioaddr
);
495 } while ((status
& bits
) && (max
> 0));
500 u8
sata_chk_status(struct sata_ioports
*ioaddr
)
502 return sata_inb(ioaddr
->status_addr
);
506 ulong
sata_read(int device
, ulong blknr
, lbaint_t blkcnt
, void *buff
)
508 ulong n
= 0, *buffer
= (ulong
*)buff
;
509 u8 dev
= 0, num
= 0, mask
= 0, status
= 0;
512 unsigned char lba48
= 0;
514 if (blknr
& 0x0000fffff0000000) {
515 if (!sata_dev_desc
[devno
].lba48
) {
516 printf("Drive doesn't support 48-bit addressing\n");
519 /* more than 28 bits used, use 48bit mode */
524 num
= device
/ CONFIG_SYS_SATA_DEVS_PER_BUS
;
525 /* dev on the port */
526 if (device
>= CONFIG_SYS_SATA_DEVS_PER_BUS
)
527 dev
= device
- CONFIG_SYS_SATA_DEVS_PER_BUS
;
536 if (!(port
[num
].dev_mask
& mask
)) {
537 printf("dev%d is not present on port#%d\n", dev
, num
);
542 dev_select(&port
[num
].ioaddr
, dev
);
544 status
= sata_busy_wait(&port
[num
].ioaddr
, ATA_BUSY
, 500);
545 if (status
& ATA_BUSY
) {
546 printf("ata%u failed to respond\n", port
[num
].port_no
);
549 while (blkcnt
-- > 0) {
550 status
= sata_busy_wait(&port
[num
].ioaddr
, ATA_BUSY
, 500);
551 if (status
& ATA_BUSY
) {
552 printf("ata%u failed to respond\n", 0);
557 /* write high bits */
558 sata_outb(0, port
[num
].ioaddr
.nsect_addr
);
559 sata_outb((blknr
>> 24) & 0xFF,
560 port
[num
].ioaddr
.lbal_addr
);
561 sata_outb((blknr
>> 32) & 0xFF,
562 port
[num
].ioaddr
.lbam_addr
);
563 sata_outb((blknr
>> 40) & 0xFF,
564 port
[num
].ioaddr
.lbah_addr
);
567 sata_outb(1, port
[num
].ioaddr
.nsect_addr
);
568 sata_outb(((blknr
) >> 0) & 0xFF,
569 port
[num
].ioaddr
.lbal_addr
);
570 sata_outb((blknr
>> 8) & 0xFF, port
[num
].ioaddr
.lbam_addr
);
571 sata_outb((blknr
>> 16) & 0xFF, port
[num
].ioaddr
.lbah_addr
);
575 sata_outb(ATA_LBA
, port
[num
].ioaddr
.device_addr
);
576 sata_outb(ATA_CMD_READ_EXT
,
577 port
[num
].ioaddr
.command_addr
);
581 sata_outb(ATA_LBA
| ((blknr
>> 24) & 0xF),
582 port
[num
].ioaddr
.device_addr
);
583 sata_outb(ATA_CMD_READ
,
584 port
[num
].ioaddr
.command_addr
);
588 /* may take up to 4 sec */
589 status
= sata_busy_wait(&port
[num
].ioaddr
, ATA_BUSY
, 4000);
591 if ((status
& (ATA_STAT_DRQ
| ATA_STAT_BUSY
| ATA_STAT_ERR
))
595 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
596 device
, (ulong
) blknr
, status
);
597 err
= sata_inb(port
[num
].ioaddr
.error_addr
);
598 printf("Error reg = 0x%x\n", err
);
601 input_data(&port
[num
].ioaddr
, buffer
, ATA_SECTORWORDS
);
602 sata_inb(port
[num
].ioaddr
.altstatus_addr
);
607 buffer
+= ATA_SECTORWORDS
;
612 ulong
sata_write(int device
, ulong blknr
, lbaint_t blkcnt
, const void *buff
)
614 ulong n
= 0, *buffer
= (ulong
*)buff
;
615 unsigned char status
= 0, num
= 0, dev
= 0, mask
= 0;
618 unsigned char lba48
= 0;
620 if (blknr
& 0x0000fffff0000000) {
621 if (!sata_dev_desc
[devno
].lba48
) {
622 printf("Drive doesn't support 48-bit addressing\n");
625 /* more than 28 bits used, use 48bit mode */
630 num
= device
/ CONFIG_SYS_SATA_DEVS_PER_BUS
;
631 /* dev on the Port */
632 if (device
>= CONFIG_SYS_SATA_DEVS_PER_BUS
)
633 dev
= device
- CONFIG_SYS_SATA_DEVS_PER_BUS
;
643 dev_select(&port
[num
].ioaddr
, dev
);
645 status
= sata_busy_wait(&port
[num
].ioaddr
, ATA_BUSY
, 500);
646 if (status
& ATA_BUSY
) {
647 printf("ata%u failed to respond\n", port
[num
].port_no
);
651 while (blkcnt
-- > 0) {
652 status
= sata_busy_wait(&port
[num
].ioaddr
, ATA_BUSY
, 500);
653 if (status
& ATA_BUSY
) {
654 printf("ata%u failed to respond\n",
660 /* write high bits */
661 sata_outb(0, port
[num
].ioaddr
.nsect_addr
);
662 sata_outb((blknr
>> 24) & 0xFF,
663 port
[num
].ioaddr
.lbal_addr
);
664 sata_outb((blknr
>> 32) & 0xFF,
665 port
[num
].ioaddr
.lbam_addr
);
666 sata_outb((blknr
>> 40) & 0xFF,
667 port
[num
].ioaddr
.lbah_addr
);
670 sata_outb(1, port
[num
].ioaddr
.nsect_addr
);
671 sata_outb((blknr
>> 0) & 0xFF, port
[num
].ioaddr
.lbal_addr
);
672 sata_outb((blknr
>> 8) & 0xFF, port
[num
].ioaddr
.lbam_addr
);
673 sata_outb((blknr
>> 16) & 0xFF, port
[num
].ioaddr
.lbah_addr
);
676 sata_outb(ATA_LBA
, port
[num
].ioaddr
.device_addr
);
677 sata_outb(ATA_CMD_WRITE_EXT
,
678 port
[num
].ioaddr
.command_addr
);
682 sata_outb(ATA_LBA
| ((blknr
>> 24) & 0xF),
683 port
[num
].ioaddr
.device_addr
);
684 sata_outb(ATA_CMD_WRITE
,
685 port
[num
].ioaddr
.command_addr
);
689 /* may take up to 4 sec */
690 status
= sata_busy_wait(&port
[num
].ioaddr
, ATA_BUSY
, 4000);
691 if ((status
& (ATA_STAT_DRQ
| ATA_STAT_BUSY
| ATA_STAT_ERR
))
693 printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
694 device
, (ulong
) blknr
, status
);
698 output_data(&port
[num
].ioaddr
, buffer
, ATA_SECTORWORDS
);
699 sata_inb(port
[num
].ioaddr
.altstatus_addr
);
704 buffer
+= ATA_SECTORWORDS
;
709 int scan_sata(int dev
)