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[people/ms/u-boot.git] / drivers / block / fsl_sata.c
1 /*
2 * Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <command.h>
10 #include <asm/io.h>
11 #include <asm/processor.h>
12 #include <asm/fsl_serdes.h>
13 #include <malloc.h>
14 #include <libata.h>
15 #include <fis.h>
16 #include <sata.h>
17 #include "fsl_sata.h"
18
19 #ifndef CONFIG_SYS_SATA1_FLAGS
20 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
21 #endif
22 #ifndef CONFIG_SYS_SATA2_FLAGS
23 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
24 #endif
25
26 static struct fsl_sata_info fsl_sata_info[] = {
27 #ifdef CONFIG_SATA1
28 {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS},
29 #else
30 {0, 0},
31 #endif
32 #ifdef CONFIG_SATA2
33 {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS},
34 #else
35 {0, 0},
36 #endif
37 };
38
39 static inline void sdelay(unsigned long sec)
40 {
41 unsigned long i;
42 for (i = 0; i < sec; i++)
43 mdelay(1000);
44 }
45
46 static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
47 {
48 printf("Status FIS dump:\n\r");
49 printf("fis_type: %02x\n\r", s->fis_type);
50 printf("pm_port_i: %02x\n\r", s->pm_port_i);
51 printf("status: %02x\n\r", s->status);
52 printf("error: %02x\n\r", s->error);
53 printf("lba_low: %02x\n\r", s->lba_low);
54 printf("lba_mid: %02x\n\r", s->lba_mid);
55 printf("lba_high: %02x\n\r", s->lba_high);
56 printf("device: %02x\n\r", s->device);
57 printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
58 printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
59 printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
60 printf("res1: %02x\n\r", s->res1);
61 printf("sector_count: %02x\n\r", s->sector_count);
62 printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
63 }
64
65 static int ata_wait_register(unsigned __iomem *addr, u32 mask,
66 u32 val, u32 timeout_msec)
67 {
68 int i;
69 u32 temp;
70
71 for (i = 0; (((temp = in_le32(addr)) & mask) != val)
72 && i < timeout_msec; i++)
73 mdelay(1);
74 return (i < timeout_msec) ? 0 : -1;
75 }
76
77 int init_sata(int dev)
78 {
79 u32 length, align;
80 cmd_hdr_tbl_t *cmd_hdr;
81 u32 cda;
82 u32 val32;
83 fsl_sata_reg_t __iomem *reg;
84 u32 sig;
85 int i;
86 fsl_sata_t *sata;
87
88 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
89 printf("the sata index %d is out of ranges\n\r", dev);
90 return -1;
91 }
92
93 #ifdef CONFIG_MPC85xx
94 if ((dev == 0) && (!is_serdes_configured(SATA1))) {
95 printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
96 return -1;
97 }
98 if ((dev == 1) && (!is_serdes_configured(SATA2))) {
99 printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
100 return -1;
101 }
102 #endif
103
104 /* Allocate SATA device driver struct */
105 sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
106 if (!sata) {
107 printf("alloc the sata device struct failed\n\r");
108 return -1;
109 }
110 /* Zero all of the device driver struct */
111 memset((void *)sata, 0, sizeof(fsl_sata_t));
112
113 /* Save the private struct to block device struct */
114 sata_dev_desc[dev].priv = (void *)sata;
115
116 sprintf(sata->name, "SATA%d", dev);
117
118 /* Set the controller register base address to device struct */
119 reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
120 sata->reg_base = reg;
121
122 /* Allocate the command header table, 4 bytes aligned */
123 length = sizeof(struct cmd_hdr_tbl);
124 align = SATA_HC_CMD_HDR_TBL_ALIGN;
125 sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
126 if (!sata) {
127 printf("alloc the command header failed\n\r");
128 return -1;
129 }
130
131 cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
132 & ~(align - 1));
133 sata->cmd_hdr = cmd_hdr;
134
135 /* Zero all of the command header table */
136 memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
137
138 /* Allocate command descriptor for all command */
139 length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
140 align = SATA_HC_CMD_DESC_ALIGN;
141 sata->cmd_desc_offset = (void *)malloc(length + align);
142 if (!sata->cmd_desc_offset) {
143 printf("alloc the command descriptor failed\n\r");
144 return -1;
145 }
146 sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
147 & ~(align - 1));
148 /* Zero all of command descriptor */
149 memset((void *)sata->cmd_desc_offset, 0, length + align);
150
151 /* Link the command descriptor to command header */
152 for (i = 0; i < SATA_HC_MAX_CMD; i++) {
153 cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
154 & ~(CMD_HDR_CDA_ALIGN - 1);
155 cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
156 }
157
158 /* To have safe state, force the controller offline */
159 val32 = in_le32(&reg->hcontrol);
160 val32 &= ~HCONTROL_ONOFF;
161 val32 |= HCONTROL_FORCE_OFFLINE;
162 out_le32(&reg->hcontrol, val32);
163
164 /* Wait the controller offline */
165 ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
166
167 /* Set the command header base address to CHBA register to tell DMA */
168 out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);
169
170 /* Snoop for the command header */
171 val32 = in_le32(&reg->hcontrol);
172 val32 |= HCONTROL_HDR_SNOOP;
173 out_le32(&reg->hcontrol, val32);
174
175 /* Disable all of interrupts */
176 val32 = in_le32(&reg->hcontrol);
177 val32 &= ~HCONTROL_INT_EN_ALL;
178 out_le32(&reg->hcontrol, val32);
179
180 /* Clear all of interrupts */
181 val32 = in_le32(&reg->hstatus);
182 out_le32(&reg->hstatus, val32);
183
184 /* Set the ICC, no interrupt coalescing */
185 out_le32(&reg->icc, 0x01000000);
186
187 /* No PM attatched, the SATA device direct connect */
188 out_le32(&reg->cqpmp, 0);
189
190 /* Clear SError register */
191 val32 = in_le32(&reg->serror);
192 out_le32(&reg->serror, val32);
193
194 /* Clear CER register */
195 val32 = in_le32(&reg->cer);
196 out_le32(&reg->cer, val32);
197
198 /* Clear DER register */
199 val32 = in_le32(&reg->der);
200 out_le32(&reg->der, val32);
201
202 /* No device detection or initialization action requested */
203 out_le32(&reg->scontrol, 0x00000300);
204
205 /* Configure the transport layer, default value */
206 out_le32(&reg->transcfg, 0x08000016);
207
208 /* Configure the link layer, default value */
209 out_le32(&reg->linkcfg, 0x0000ff34);
210
211 /* Bring the controller online */
212 val32 = in_le32(&reg->hcontrol);
213 val32 |= HCONTROL_ONOFF;
214 out_le32(&reg->hcontrol, val32);
215
216 mdelay(100);
217
218 /* print sata device name */
219 if (!dev)
220 printf("%s ", sata->name);
221 else
222 printf(" %s ", sata->name);
223
224 /* Wait PHY RDY signal changed for 500ms */
225 ata_wait_register(&reg->hstatus, HSTATUS_PHY_RDY,
226 HSTATUS_PHY_RDY, 500);
227
228 /* Check PHYRDY */
229 val32 = in_le32(&reg->hstatus);
230 if (val32 & HSTATUS_PHY_RDY) {
231 sata->link = 1;
232 } else {
233 sata->link = 0;
234 printf("(No RDY)\n\r");
235 return -1;
236 }
237
238 /* Wait for signature updated, which is 1st D2H */
239 ata_wait_register(&reg->hstatus, HSTATUS_SIGNATURE,
240 HSTATUS_SIGNATURE, 10000);
241
242 if (val32 & HSTATUS_SIGNATURE) {
243 sig = in_le32(&reg->sig);
244 debug("Signature updated, the sig =%08x\n\r", sig);
245 sata->ata_device_type = ata_dev_classify(sig);
246 }
247
248 /* Check the speed */
249 val32 = in_le32(&reg->sstatus);
250 if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
251 printf("(1.5 Gbps)\n\r");
252 else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
253 printf("(3 Gbps)\n\r");
254
255 return 0;
256 }
257
258 static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
259 {
260 printf("\n\rSATA: %08x\n\r", (u32)reg);
261 printf("CQR: %08x\n\r", in_le32(&reg->cqr));
262 printf("CAR: %08x\n\r", in_le32(&reg->car));
263 printf("CCR: %08x\n\r", in_le32(&reg->ccr));
264 printf("CER: %08x\n\r", in_le32(&reg->cer));
265 printf("CQR: %08x\n\r", in_le32(&reg->cqr));
266 printf("DER: %08x\n\r", in_le32(&reg->der));
267 printf("CHBA: %08x\n\r", in_le32(&reg->chba));
268 printf("HStatus: %08x\n\r", in_le32(&reg->hstatus));
269 printf("HControl: %08x\n\r", in_le32(&reg->hcontrol));
270 printf("CQPMP: %08x\n\r", in_le32(&reg->cqpmp));
271 printf("SIG: %08x\n\r", in_le32(&reg->sig));
272 printf("ICC: %08x\n\r", in_le32(&reg->icc));
273 printf("SStatus: %08x\n\r", in_le32(&reg->sstatus));
274 printf("SError: %08x\n\r", in_le32(&reg->serror));
275 printf("SControl: %08x\n\r", in_le32(&reg->scontrol));
276 printf("SNotification: %08x\n\r", in_le32(&reg->snotification));
277 printf("TransCfg: %08x\n\r", in_le32(&reg->transcfg));
278 printf("TransStatus: %08x\n\r", in_le32(&reg->transstatus));
279 printf("LinkCfg: %08x\n\r", in_le32(&reg->linkcfg));
280 printf("LinkCfg1: %08x\n\r", in_le32(&reg->linkcfg1));
281 printf("LinkCfg2: %08x\n\r", in_le32(&reg->linkcfg2));
282 printf("LinkStatus: %08x\n\r", in_le32(&reg->linkstatus));
283 printf("LinkStatus1: %08x\n\r", in_le32(&reg->linkstatus1));
284 printf("PhyCtrlCfg: %08x\n\r", in_le32(&reg->phyctrlcfg));
285 printf("SYSPR: %08x\n\r", in_be32(&reg->syspr));
286 }
287
288 static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
289 int is_ncq, int tag, u8 *buffer, u32 len)
290 {
291 cmd_hdr_entry_t *cmd_hdr;
292 cmd_desc_t *cmd_desc;
293 sata_fis_h2d_t *h2d;
294 prd_entry_t *prde;
295 u32 ext_c_ddc;
296 u32 prde_count;
297 u32 val32;
298 u32 ttl;
299 fsl_sata_reg_t __iomem *reg = sata->reg_base;
300 int i;
301
302 /* Check xfer length */
303 if (len > SATA_HC_MAX_XFER_LEN) {
304 printf("max transfer length is 64MB\n\r");
305 return 0;
306 }
307
308 /* Setup the command descriptor */
309 cmd_desc = sata->cmd_desc + tag;
310
311 /* Get the pointer cfis of command descriptor */
312 h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
313
314 /* Zero the cfis of command descriptor */
315 memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
316
317 /* Copy the cfis from user to command descriptor */
318 h2d->fis_type = cfis->fis_type;
319 h2d->pm_port_c = cfis->pm_port_c;
320 h2d->command = cfis->command;
321
322 h2d->features = cfis->features;
323 h2d->features_exp = cfis->features_exp;
324
325 h2d->lba_low = cfis->lba_low;
326 h2d->lba_mid = cfis->lba_mid;
327 h2d->lba_high = cfis->lba_high;
328 h2d->lba_low_exp = cfis->lba_low_exp;
329 h2d->lba_mid_exp = cfis->lba_mid_exp;
330 h2d->lba_high_exp = cfis->lba_high_exp;
331
332 if (!is_ncq) {
333 h2d->sector_count = cfis->sector_count;
334 h2d->sector_count_exp = cfis->sector_count_exp;
335 } else { /* NCQ */
336 h2d->sector_count = (u8)(tag << 3);
337 }
338
339 h2d->device = cfis->device;
340 h2d->control = cfis->control;
341
342 /* Setup the PRD table */
343 prde = (prd_entry_t *)cmd_desc->prdt;
344 memset((void *)prde, 0, sizeof(struct prdt));
345
346 prde_count = 0;
347 ttl = len;
348 for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
349 if (!len)
350 break;
351 prde->dba = cpu_to_le32((u32)buffer & ~0x3);
352 debug("dba = %08x\n\r", (u32)buffer);
353
354 if (len < PRD_ENTRY_MAX_XFER_SZ) {
355 ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
356 debug("ext_c_ddc1 = %08x, len = %08x\n\r", ext_c_ddc, len);
357 prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
358 prde_count++;
359 prde++;
360 break;
361 } else {
362 ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
363 debug("ext_c_ddc2 = %08x, len = %08x\n\r", ext_c_ddc, len);
364 prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
365 buffer += PRD_ENTRY_MAX_XFER_SZ;
366 len -= PRD_ENTRY_MAX_XFER_SZ;
367 prde_count++;
368 prde++;
369 }
370 }
371
372 /* Setup the command slot of cmd hdr */
373 cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
374
375 cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
376
377 val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
378 val32 |= sizeof(sata_fis_h2d_t);
379 cmd_hdr->prde_fis_len = cpu_to_le32(val32);
380
381 cmd_hdr->ttl = cpu_to_le32(ttl);
382
383 if (!is_ncq) {
384 val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
385 } else {
386 val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP | CMD_HDR_ATTR_FPDMA;
387 }
388
389 tag &= CMD_HDR_ATTR_TAG;
390 val32 |= tag;
391
392 debug("attribute = %08x\n\r", val32);
393 cmd_hdr->attribute = cpu_to_le32(val32);
394
395 /* Make sure cmd desc and cmd slot valid before commmand issue */
396 sync();
397
398 /* PMP*/
399 val32 = (u32)(h2d->pm_port_c & 0x0f);
400 out_le32(&reg->cqpmp, val32);
401
402 /* Wait no active */
403 if (ata_wait_register(&reg->car, (1 << tag), 0, 10000))
404 printf("Wait no active time out\n\r");
405
406 /* Issue command */
407 if (!(in_le32(&reg->cqr) & (1 << tag))) {
408 val32 = 1 << tag;
409 out_le32(&reg->cqr, val32);
410 }
411
412 /* Wait command completed for 10s */
413 if (ata_wait_register(&reg->ccr, (1 << tag), (1 << tag), 10000)) {
414 if (!is_ncq)
415 printf("Non-NCQ command time out\n\r");
416 else
417 printf("NCQ command time out\n\r");
418 }
419
420 val32 = in_le32(&reg->cer);
421
422 if (val32) {
423 u32 der;
424 fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
425 printf("CE at device\n\r");
426 fsl_sata_dump_regs(reg);
427 der = in_le32(&reg->der);
428 out_le32(&reg->cer, val32);
429 out_le32(&reg->der, der);
430 }
431
432 /* Clear complete flags */
433 val32 = in_le32(&reg->ccr);
434 out_le32(&reg->ccr, val32);
435
436 return len;
437 }
438
439 static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
440 int tag, u8 *buffer, u32 len)
441 {
442 return 0;
443 }
444
445 static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
446 enum cmd_type command_type, int tag, u8 *buffer, u32 len)
447 {
448 int rc;
449
450 if (tag > SATA_HC_MAX_CMD || tag < 0) {
451 printf("tag is out of range, tag=%d\n\r", tag);
452 return -1;
453 }
454
455 switch (command_type) {
456 case CMD_ATA:
457 rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
458 return rc;
459 case CMD_RESET:
460 rc = fsl_ata_exec_reset_cmd(sata, cfis, tag, buffer, len);
461 return rc;
462 case CMD_NCQ:
463 rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
464 return rc;
465 case CMD_ATAPI:
466 case CMD_VENDOR_BIST:
467 case CMD_BIST:
468 printf("not support now\n\r");
469 return -1;
470 default:
471 break;
472 }
473
474 return -1;
475 }
476
477 static void fsl_sata_identify(int dev, u16 *id)
478 {
479 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
480 struct sata_fis_h2d h2d, *cfis = &h2d;
481
482 memset(cfis, 0, sizeof(struct sata_fis_h2d));
483
484 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
485 cfis->pm_port_c = 0x80; /* is command */
486 cfis->command = ATA_CMD_ID_ATA;
487
488 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
489 ata_swap_buf_le16(id, ATA_ID_WORDS);
490 }
491
492 static void fsl_sata_xfer_mode(int dev, u16 *id)
493 {
494 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
495
496 sata->pio = id[ATA_ID_PIO_MODES];
497 sata->mwdma = id[ATA_ID_MWDMA_MODES];
498 sata->udma = id[ATA_ID_UDMA_MODES];
499 debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma);
500 }
501
502 static void fsl_sata_set_features(int dev)
503 {
504 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
505 struct sata_fis_h2d h2d, *cfis = &h2d;
506 u8 udma_cap;
507
508 memset(cfis, 0, sizeof(struct sata_fis_h2d));
509
510 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
511 cfis->pm_port_c = 0x80; /* is command */
512 cfis->command = ATA_CMD_SET_FEATURES;
513 cfis->features = SETFEATURES_XFER;
514
515 /* First check the device capablity */
516 udma_cap = (u8)(sata->udma & 0xff);
517 debug("udma_cap %02x\n\r", udma_cap);
518
519 if (udma_cap == ATA_UDMA6)
520 cfis->sector_count = XFER_UDMA_6;
521 if (udma_cap == ATA_UDMA5)
522 cfis->sector_count = XFER_UDMA_5;
523 if (udma_cap == ATA_UDMA4)
524 cfis->sector_count = XFER_UDMA_4;
525 if (udma_cap == ATA_UDMA3)
526 cfis->sector_count = XFER_UDMA_3;
527
528 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
529 }
530
531 static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
532 {
533 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
534 struct sata_fis_h2d h2d, *cfis = &h2d;
535 u32 block;
536
537 block = start;
538
539 memset(cfis, 0, sizeof(struct sata_fis_h2d));
540
541 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
542 cfis->pm_port_c = 0x80; /* is command */
543 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
544 cfis->device = ATA_LBA;
545
546 cfis->device |= (block >> 24) & 0xf;
547 cfis->lba_high = (block >> 16) & 0xff;
548 cfis->lba_mid = (block >> 8) & 0xff;
549 cfis->lba_low = block & 0xff;
550 cfis->sector_count = (u8)(blkcnt & 0xff);
551
552 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
553 return blkcnt;
554 }
555
556 static void fsl_sata_flush_cache(int dev)
557 {
558 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
559 struct sata_fis_h2d h2d, *cfis = &h2d;
560
561 memset(cfis, 0, sizeof(struct sata_fis_h2d));
562
563 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
564 cfis->pm_port_c = 0x80; /* is command */
565 cfis->command = ATA_CMD_FLUSH;
566
567 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
568 }
569
570 static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
571 {
572 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
573 struct sata_fis_h2d h2d, *cfis = &h2d;
574 u64 block;
575
576 block = (u64)start;
577
578 memset(cfis, 0, sizeof(struct sata_fis_h2d));
579
580 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
581 cfis->pm_port_c = 0x80; /* is command */
582
583 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
584 : ATA_CMD_READ_EXT;
585
586 cfis->lba_high_exp = (block >> 40) & 0xff;
587 cfis->lba_mid_exp = (block >> 32) & 0xff;
588 cfis->lba_low_exp = (block >> 24) & 0xff;
589 cfis->lba_high = (block >> 16) & 0xff;
590 cfis->lba_mid = (block >> 8) & 0xff;
591 cfis->lba_low = block & 0xff;
592 cfis->device = ATA_LBA;
593 cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
594 cfis->sector_count = blkcnt & 0xff;
595
596 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
597 return blkcnt;
598 }
599
600 static u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer,
601 int is_write)
602 {
603 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
604 struct sata_fis_h2d h2d, *cfis = &h2d;
605 int ncq_channel;
606 u64 block;
607
608 if (sata->lba48 != 1) {
609 printf("execute FPDMA command on non-LBA48 hard disk\n\r");
610 return -1;
611 }
612
613 block = (u64)start;
614
615 memset(cfis, 0, sizeof(struct sata_fis_h2d));
616
617 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
618 cfis->pm_port_c = 0x80; /* is command */
619
620 cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
621 : ATA_CMD_FPDMA_READ;
622
623 cfis->lba_high_exp = (block >> 40) & 0xff;
624 cfis->lba_mid_exp = (block >> 32) & 0xff;
625 cfis->lba_low_exp = (block >> 24) & 0xff;
626 cfis->lba_high = (block >> 16) & 0xff;
627 cfis->lba_mid = (block >> 8) & 0xff;
628 cfis->lba_low = block & 0xff;
629
630 cfis->device = ATA_LBA;
631 cfis->features_exp = (blkcnt >> 8) & 0xff;
632 cfis->features = blkcnt & 0xff;
633
634 if (sata->queue_depth >= SATA_HC_MAX_CMD)
635 ncq_channel = SATA_HC_MAX_CMD - 1;
636 else
637 ncq_channel = sata->queue_depth - 1;
638
639 /* Use the latest queue */
640 fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer, ATA_SECT_SIZE * blkcnt);
641 return blkcnt;
642 }
643
644 static void fsl_sata_flush_cache_ext(int dev)
645 {
646 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
647 struct sata_fis_h2d h2d, *cfis = &h2d;
648
649 memset(cfis, 0, sizeof(struct sata_fis_h2d));
650
651 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
652 cfis->pm_port_c = 0x80; /* is command */
653 cfis->command = ATA_CMD_FLUSH_EXT;
654
655 fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
656 }
657
658 static void fsl_sata_init_wcache(int dev, u16 *id)
659 {
660 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
661
662 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
663 sata->wcache = 1;
664 if (ata_id_has_flush(id))
665 sata->flush = 1;
666 if (ata_id_has_flush_ext(id))
667 sata->flush_ext = 1;
668 }
669
670 static int fsl_sata_get_wcache(int dev)
671 {
672 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
673 return sata->wcache;
674 }
675
676 static int fsl_sata_get_flush(int dev)
677 {
678 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
679 return sata->flush;
680 }
681
682 static int fsl_sata_get_flush_ext(int dev)
683 {
684 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
685 return sata->flush_ext;
686 }
687
688 static u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
689 const void *buffer, int is_write)
690 {
691 u32 start, blks;
692 u8 *addr;
693 int max_blks;
694
695 start = blknr;
696 blks = blkcnt;
697 addr = (u8 *)buffer;
698
699 max_blks = ATA_MAX_SECTORS_LBA48;
700 do {
701 if (blks > max_blks) {
702 if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
703 fsl_sata_rw_cmd_ext(dev, start, max_blks, addr, is_write);
704 else
705 fsl_sata_rw_ncq_cmd(dev, start, max_blks, addr, is_write);
706 start += max_blks;
707 blks -= max_blks;
708 addr += ATA_SECT_SIZE * max_blks;
709 } else {
710 if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
711 fsl_sata_rw_cmd_ext(dev, start, blks, addr, is_write);
712 else
713 fsl_sata_rw_ncq_cmd(dev, start, blks, addr, is_write);
714 start += blks;
715 blks = 0;
716 addr += ATA_SECT_SIZE * blks;
717 }
718 } while (blks != 0);
719
720 return blkcnt;
721 }
722
723 static u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt,
724 const void *buffer, int is_write)
725 {
726 u32 start, blks;
727 u8 *addr;
728 int max_blks;
729
730 start = blknr;
731 blks = blkcnt;
732 addr = (u8 *)buffer;
733
734 max_blks = ATA_MAX_SECTORS;
735 do {
736 if (blks > max_blks) {
737 fsl_sata_rw_cmd(dev, start, max_blks, addr, is_write);
738 start += max_blks;
739 blks -= max_blks;
740 addr += ATA_SECT_SIZE * max_blks;
741 } else {
742 fsl_sata_rw_cmd(dev, start, blks, addr, is_write);
743 start += blks;
744 blks = 0;
745 addr += ATA_SECT_SIZE * blks;
746 }
747 } while (blks != 0);
748
749 return blkcnt;
750 }
751
752 /*
753 * SATA interface between low level driver and command layer
754 */
755 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
756 {
757 u32 rc;
758 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
759
760 if (sata->lba48)
761 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
762 else
763 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
764 return rc;
765 }
766
767 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
768 {
769 u32 rc;
770 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
771
772 if (sata->lba48) {
773 rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
774 if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush_ext(dev))
775 fsl_sata_flush_cache_ext(dev);
776 } else {
777 rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
778 if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush(dev))
779 fsl_sata_flush_cache(dev);
780 }
781 return rc;
782 }
783
784 int scan_sata(int dev)
785 {
786 fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
787 unsigned char serial[ATA_ID_SERNO_LEN + 1];
788 unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
789 unsigned char product[ATA_ID_PROD_LEN + 1];
790 u16 *id;
791 u64 n_sectors;
792
793 /* if no detected link */
794 if (!sata->link)
795 return -1;
796
797 id = (u16 *)malloc(ATA_ID_WORDS * 2);
798 if (!id) {
799 printf("id malloc failed\n\r");
800 return -1;
801 }
802
803 /* Identify device to get information */
804 fsl_sata_identify(dev, id);
805
806 /* Serial number */
807 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
808 memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
809
810 /* Firmware version */
811 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
812 memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
813
814 /* Product model */
815 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
816 memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
817
818 /* Totoal sectors */
819 n_sectors = ata_id_n_sectors(id);
820 sata_dev_desc[dev].lba = (u32)n_sectors;
821
822 #ifdef CONFIG_LBA48
823 /* Check if support LBA48 */
824 if (ata_id_has_lba48(id)) {
825 sata->lba48 = 1;
826 debug("Device support LBA48\n\r");
827 } else
828 debug("Device supports LBA28\n\r");
829 #endif
830
831 /* Get the NCQ queue depth from device */
832 sata->queue_depth = ata_id_queue_depth(id);
833
834 /* Get the xfer mode from device */
835 fsl_sata_xfer_mode(dev, id);
836
837 /* Get the write cache status from device */
838 fsl_sata_init_wcache(dev, id);
839
840 /* Set the xfer mode to highest speed */
841 fsl_sata_set_features(dev);
842 #ifdef DEBUG
843 fsl_sata_identify(dev, id);
844 ata_dump_id(id);
845 #endif
846 free((void *)id);
847 return 0;
848 }
"Das U-Boot" Source Tree