drivers/block/sata_ceva.c

   1 /*
   2  * (C) Copyright 2015 - 2016 Xilinx, Inc.
   3  * Michal Simek <michal.simek@xilinx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <netdev.h>
   9 #include <ahci.h>
  10 #include <scsi.h>
  11 #include <asm/arch/hardware.h>
  12
  13 #include <asm/io.h>
  14
  15 /* Vendor Specific Register Offsets */
  16 #define AHCI_VEND_PCFG  0xA4
  17 #define AHCI_VEND_PPCFG 0xA8
  18 #define AHCI_VEND_PP2C  0xAC
  19 #define AHCI_VEND_PP3C  0xB0
  20 #define AHCI_VEND_PP4C  0xB4
  21 #define AHCI_VEND_PP5C  0xB8
  22 #define AHCI_VEND_PAXIC 0xC0
  23 #define AHCI_VEND_PTC   0xC8
  24
  25 /* Vendor Specific Register bit definitions */
  26 #define PAXIC_ADBW_BW64 0x1
  27 #define PAXIC_MAWIDD    (1 << 8)
  28 #define PAXIC_MARIDD    (1 << 16)
  29 #define PAXIC_OTL       (0x4 << 20)
  30
  31 #define PCFG_TPSS_VAL   (0x32 << 16)
  32 #define PCFG_TPRS_VAL   (0x2 << 12)
  33 #define PCFG_PAD_VAL    0x2
  34
  35 #define PPCFG_TTA       0x1FFFE
  36 #define PPCFG_PSSO_EN   (1 << 28)
  37 #define PPCFG_PSS_EN    (1 << 29)
  38 #define PPCFG_ESDF_EN   (1 << 31)
  39
  40 #define PP2C_CIBGMN     0x0F
  41 #define PP2C_CIBGMX     (0x25 << 8)
  42 #define PP2C_CIBGN      (0x18 << 16)
  43 #define PP2C_CINMP      (0x29 << 24)
  44
  45 #define PP3C_CWBGMN     0x04
  46 #define PP3C_CWBGMX     (0x0B << 8)
  47 #define PP3C_CWBGN      (0x08 << 16)
  48 #define PP3C_CWNMP      (0x0F << 24)
  49
  50 #define PP4C_BMX        0x0a
  51 #define PP4C_BNM        (0x08 << 8)
  52 #define PP4C_SFD        (0x4a << 16)
  53 #define PP4C_PTST       (0x06 << 24)
  54
  55 #define PP5C_RIT        0x60216
  56 #define PP5C_RCT        (0x7f0 << 20)
  57
  58 #define PTC_RX_WM_VAL   0x40
  59 #define PTC_RSVD        (1 << 27)
  60
  61 #define PORT0_BASE      0x100
  62 #define PORT1_BASE      0x180
  63
  64 /* Port Control Register Bit Definitions */
  65 #define PORT_SCTL_SPD_GEN3      (0x3 << 4)
  66 #define PORT_SCTL_SPD_GEN2      (0x2 << 4)
  67 #define PORT_SCTL_SPD_GEN1      (0x1 << 4)
  68 #define PORT_SCTL_IPM           (0x3 << 8)
  69
  70 #define PORT_BASE       0x100
  71 #define PORT_OFFSET     0x80
  72 #define NR_PORTS        2
  73 #define DRV_NAME        "ahci-ceva"
  74 #define CEVA_FLAG_BROKEN_GEN2   1
  75
  76 int init_sata(int dev)
  77 {
  78         ulong tmp;
  79         ulong mmio = ZYNQMP_SATA_BASEADDR;
  80         int i;
  81
  82         /*
  83          * AXI Data bus width to 64
  84          * Set Mem Addr Read, Write ID for data transfers
  85          * Transfer limit to 72 DWord
  86          */
  87         tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
  88         writel(tmp, mmio + AHCI_VEND_PAXIC);
  89
  90         /* Set AHCI Enable */
  91         tmp = readl(mmio + HOST_CTL);
  92         tmp |= HOST_AHCI_EN;
  93         writel(tmp, mmio + HOST_CTL);
  94
  95         for (i = 0; i < NR_PORTS; i++) {
  96                 /* TPSS TPRS scalars, CISE and Port Addr */
  97                 tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
  98                 writel(tmp, mmio + AHCI_VEND_PCFG);
  99
 100                 /* Port Phy Cfg register enables */
 101                 tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
 102                 writel(tmp, mmio + AHCI_VEND_PPCFG);
 103
 104                 /* Rx Watermark setting  */
 105                 tmp = PTC_RX_WM_VAL | PTC_RSVD;
 106                 writel(tmp, mmio + AHCI_VEND_PTC);
 107
 108                 /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
 109                 tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
 110                 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
 111         }
 112         return 0;
 113 }