drivers/block/sata_sil.c

   1 /*
   2  * Copyright (C) 2011 Freescale Semiconductor, Inc.
   3  * Author: Tang Yuantian <b29983@freescale.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <pci.h>
  10 #include <command.h>
  11 #include <asm/byteorder.h>
  12 #include <malloc.h>
  13 #include <asm/io.h>
  14 #include <fis.h>
  15 #include <sata.h>
  16 #include <libata.h>
  17 #include <sata.h>
  18 #include "sata_sil.h"
  19
  20 /* Convert sectorsize to wordsize */
  21 #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
  22 #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
  23
  24 static struct sata_info sata_info;
  25
  26 static struct pci_device_id supported[] = {
  27         {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131},
  28         {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132},
  29         {PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124},
  30         {}
  31 };
  32
  33 static void sil_sata_dump_fis(struct sata_fis_d2h *s)
  34 {
  35         printf("Status FIS dump:\n");
  36         printf("fis_type:               %02x\n", s->fis_type);
  37         printf("pm_port_i:              %02x\n", s->pm_port_i);
  38         printf("status:                 %02x\n", s->status);
  39         printf("error:                  %02x\n", s->error);
  40         printf("lba_low:                %02x\n", s->lba_low);
  41         printf("lba_mid:                %02x\n", s->lba_mid);
  42         printf("lba_high:               %02x\n", s->lba_high);
  43         printf("device:                 %02x\n", s->device);
  44         printf("lba_low_exp:            %02x\n", s->lba_low_exp);
  45         printf("lba_mid_exp:            %02x\n", s->lba_mid_exp);
  46         printf("lba_high_exp:           %02x\n", s->lba_high_exp);
  47         printf("res1:                   %02x\n", s->res1);
  48         printf("sector_count:           %02x\n", s->sector_count);
  49         printf("sector_count_exp:       %02x\n", s->sector_count_exp);
  50 }
  51
  52 static const char *sata_spd_string(unsigned int speed)
  53 {
  54         static const char * const spd_str[] = {
  55                 "1.5 Gbps",
  56                 "3.0 Gbps",
  57                 "6.0 Gbps",
  58         };
  59
  60         if ((speed - 1) > 2)
  61                 return "<unknown>";
  62
  63         return spd_str[speed - 1];
  64 }
  65
  66 static u32 ata_wait_register(void *reg, u32 mask,
  67                          u32 val, int timeout_msec)
  68 {
  69         u32 tmp;
  70
  71         tmp = readl(reg);
  72         while ((tmp & mask) == val && timeout_msec > 0) {
  73                 mdelay(1);
  74                 timeout_msec--;
  75                 tmp = readl(reg);
  76         }
  77
  78         return tmp;
  79 }
  80
  81 static void sil_config_port(void *port)
  82 {
  83         /* configure IRQ WoC */
  84         writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
  85
  86         /* zero error counters. */
  87         writew(0x8000, port + PORT_DECODE_ERR_THRESH);
  88         writew(0x8000, port + PORT_CRC_ERR_THRESH);
  89         writew(0x8000, port + PORT_HSHK_ERR_THRESH);
  90         writew(0x0000, port + PORT_DECODE_ERR_CNT);
  91         writew(0x0000, port + PORT_CRC_ERR_CNT);
  92         writew(0x0000, port + PORT_HSHK_ERR_CNT);
  93
  94         /* always use 64bit activation */
  95         writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
  96
  97         /* clear port multiplier enable and resume bits */
  98         writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
  99 }
 100
 101 static int sil_init_port(void *port)
 102 {
 103         u32 tmp;
 104
 105         writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
 106         ata_wait_register(port + PORT_CTRL_STAT,
 107                           PORT_CS_INIT, PORT_CS_INIT, 100);
 108         tmp = ata_wait_register(port + PORT_CTRL_STAT,
 109                                 PORT_CS_RDY, 0, 100);
 110
 111         if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
 112                 return 1;
 113
 114         return 0;
 115 }
 116
 117 static void sil_read_fis(int dev, int tag, struct sata_fis_d2h *fis)
 118 {
 119         struct sil_sata *sata = sata_dev_desc[dev].priv;
 120         void *port = sata->port;
 121         struct sil_prb *prb;
 122         int i;
 123         u32 *src, *dst;
 124
 125         prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
 126         src = (u32 *)&prb->fis;
 127         dst = (u32 *)fis;
 128         for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
 129                 *dst++ = readl(src++);
 130 }
 131
 132 static int sil_exec_cmd(int dev, struct sil_cmd_block *pcmd, int tag)
 133 {
 134         struct sil_sata *sata = sata_dev_desc[dev].priv;
 135         void *port = sata->port;
 136         u64 paddr = virt_to_bus(sata->devno, pcmd);
 137         u32 irq_mask, irq_stat;
 138         int rc;
 139
 140         writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
 141
 142         /* better to add momery barrior here */
 143         writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
 144         writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
 145
 146         irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
 147         irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
 148                         0, 10000);
 149
 150         /* clear IRQs */
 151         writel(irq_mask, port + PORT_IRQ_STAT);
 152         irq_stat >>= PORT_IRQ_RAW_SHIFT;
 153
 154         if (irq_stat & PORT_IRQ_COMPLETE)
 155                 rc = 0;
 156         else {
 157                 /* force port into known state */
 158                 sil_init_port(port);
 159                 if (irq_stat & PORT_IRQ_ERROR)
 160                         rc = 1; /* error */
 161                 else
 162                         rc = 2; /* busy */
 163         }
 164
 165         return rc;
 166 }
 167
 168 static int sil_cmd_set_feature(int dev)
 169 {
 170         struct sil_sata *sata = sata_dev_desc[dev].priv;
 171         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 172         struct sata_fis_d2h fis;
 173         u8 udma_cap;
 174         int ret;
 175
 176         memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
 177         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 178         pcmd->prb.fis.pm_port_c = (1 << 7);
 179         pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
 180         pcmd->prb.fis.features = SETFEATURES_XFER;
 181
 182         /* First check the device capablity */
 183         udma_cap = (u8)(sata->udma & 0xff);
 184         debug("udma_cap %02x\n", udma_cap);
 185
 186         if (udma_cap == ATA_UDMA6)
 187                 pcmd->prb.fis.sector_count = XFER_UDMA_6;
 188         if (udma_cap == ATA_UDMA5)
 189                 pcmd->prb.fis.sector_count = XFER_UDMA_5;
 190         if (udma_cap == ATA_UDMA4)
 191                 pcmd->prb.fis.sector_count = XFER_UDMA_4;
 192         if (udma_cap == ATA_UDMA3)
 193                 pcmd->prb.fis.sector_count = XFER_UDMA_3;
 194
 195         ret = sil_exec_cmd(dev, pcmd, 0);
 196         if (ret) {
 197                 sil_read_fis(dev, 0, &fis);
 198                 printf("Err: exe cmd(0x%x).\n",
 199                                 readl(sata->port + PORT_SERROR));
 200                 sil_sata_dump_fis(&fis);
 201                 return 1;
 202         }
 203
 204         return 0;
 205 }
 206
 207 static int sil_cmd_identify_device(int dev, u16 *id)
 208 {
 209         struct sil_sata *sata = sata_dev_desc[dev].priv;
 210         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 211         struct sata_fis_d2h fis;
 212         int ret;
 213
 214         memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
 215         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
 216         pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
 217         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 218         pcmd->prb.fis.pm_port_c = (1 << 7);
 219         pcmd->prb.fis.command = ATA_CMD_ID_ATA;
 220         pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
 221         pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
 222         pcmd->sge.flags = cpu_to_le32(SGE_TRM);
 223
 224         ret = sil_exec_cmd(dev, pcmd, 0);
 225         if (ret) {
 226                 sil_read_fis(dev, 0, &fis);
 227                 printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
 228                 sil_sata_dump_fis(&fis);
 229                 return 1;
 230         }
 231         ata_swap_buf_le16(id, ATA_ID_WORDS);
 232
 233         return 0;
 234 }
 235
 236 static int sil_cmd_soft_reset(int dev)
 237 {
 238         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 239         struct sil_sata *sata = sata_dev_desc[dev].priv;
 240         struct sata_fis_d2h fis;
 241         void *port = sata->port;
 242         int ret;
 243
 244         /* put the port into known state */
 245         if (sil_init_port(port)) {
 246                 printf("SRST: port %d not ready\n", dev);
 247                 return 1;
 248         }
 249
 250         memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
 251
 252         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
 253         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 254         pcmd->prb.fis.pm_port_c = 0xf;
 255
 256         ret = sil_exec_cmd(dev, &cmdb, 0);
 257         if (ret) {
 258                 sil_read_fis(dev, 0, &fis);
 259                 printf("SRST cmd error.\n");
 260                 sil_sata_dump_fis(&fis);
 261                 return 1;
 262         }
 263
 264         return 0;
 265 }
 266
 267 static ulong sil_sata_rw_cmd(int dev, ulong start, ulong blkcnt,
 268                 u8 *buffer, int is_write)
 269 {
 270         struct sil_sata *sata = sata_dev_desc[dev].priv;
 271         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 272         struct sata_fis_d2h fis;
 273         u64 block;
 274         int ret;
 275
 276         block = (u64)start;
 277         memset(pcmd, 0, sizeof(struct sil_cmd_block));
 278         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
 279         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 280         pcmd->prb.fis.pm_port_c = (1 << 7);
 281         if (is_write) {
 282                 pcmd->prb.fis.command = ATA_CMD_WRITE;
 283                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
 284         } else {
 285                 pcmd->prb.fis.command = ATA_CMD_READ;
 286                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
 287         }
 288
 289         pcmd->prb.fis.device = ATA_LBA;
 290         pcmd->prb.fis.device |= (block >> 24) & 0xf;
 291         pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
 292         pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
 293         pcmd->prb.fis.lba_low = block & 0xff;
 294         pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
 295
 296         pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
 297         pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
 298         pcmd->sge.flags = cpu_to_le32(SGE_TRM);
 299
 300         ret = sil_exec_cmd(dev, pcmd, 0);
 301         if (ret) {
 302                 sil_read_fis(dev, 0, &fis);
 303                 printf("Err: rw cmd(0x%08x).\n",
 304                                 readl(sata->port + PORT_SERROR));
 305                 sil_sata_dump_fis(&fis);
 306                 return 1;
 307         }
 308
 309         return blkcnt;
 310 }
 311
 312 static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt,
 313                 u8 *buffer, int is_write)
 314 {
 315         struct sil_sata *sata = sata_dev_desc[dev].priv;
 316         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 317         struct sata_fis_d2h fis;
 318         u64 block;
 319         int ret;
 320
 321         block = (u64)start;
 322         memset(pcmd, 0, sizeof(struct sil_cmd_block));
 323         pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
 324         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 325         pcmd->prb.fis.pm_port_c = (1 << 7);
 326         if (is_write) {
 327                 pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
 328                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
 329         } else {
 330                 pcmd->prb.fis.command = ATA_CMD_READ_EXT;
 331                 pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
 332         }
 333
 334         pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
 335         pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
 336         pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
 337         pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
 338         pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
 339         pcmd->prb.fis.lba_low = block & 0xff;
 340         pcmd->prb.fis.device = ATA_LBA;
 341         pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
 342         pcmd->prb.fis.sector_count = blkcnt & 0xff;
 343
 344         pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
 345         pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
 346         pcmd->sge.flags = cpu_to_le32(SGE_TRM);
 347
 348         ret = sil_exec_cmd(dev, pcmd, 0);
 349         if (ret) {
 350                 sil_read_fis(dev, 0, &fis);
 351                 printf("Err: rw ext cmd(0x%08x).\n",
 352                                 readl(sata->port + PORT_SERROR));
 353                 sil_sata_dump_fis(&fis);
 354                 return 1;
 355         }
 356
 357         return blkcnt;
 358 }
 359
 360 static ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
 361                                const void *buffer, int is_write)
 362 {
 363         ulong start, blks, max_blks;
 364         u8 *addr;
 365
 366         start = blknr;
 367         blks = blkcnt;
 368         addr = (u8 *)buffer;
 369
 370         max_blks = ATA_MAX_SECTORS;
 371         do {
 372                 if (blks > max_blks) {
 373                         sil_sata_rw_cmd(dev, start, max_blks, addr, is_write);
 374                         start += max_blks;
 375                         blks -= max_blks;
 376                         addr += ATA_SECT_SIZE * max_blks;
 377                 } else {
 378                         sil_sata_rw_cmd(dev, start, blks, addr, is_write);
 379                         start += blks;
 380                         blks = 0;
 381                         addr += ATA_SECT_SIZE * blks;
 382                 }
 383         } while (blks != 0);
 384
 385         return blkcnt;
 386 }
 387
 388 static ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
 389                                const void *buffer, int is_write)
 390 {
 391         ulong start, blks, max_blks;
 392         u8 *addr;
 393
 394         start = blknr;
 395         blks = blkcnt;
 396         addr = (u8 *)buffer;
 397
 398         max_blks = ATA_MAX_SECTORS_LBA48;
 399         do {
 400                 if (blks > max_blks) {
 401                         sil_sata_rw_cmd_ext(dev, start, max_blks,
 402                                         addr, is_write);
 403                         start += max_blks;
 404                         blks -= max_blks;
 405                         addr += ATA_SECT_SIZE * max_blks;
 406                 } else {
 407                         sil_sata_rw_cmd_ext(dev, start, blks,
 408                                         addr, is_write);
 409                         start += blks;
 410                         blks = 0;
 411                         addr += ATA_SECT_SIZE * blks;
 412                 }
 413         } while (blks != 0);
 414
 415         return blkcnt;
 416 }
 417
 418 static void sil_sata_cmd_flush_cache(int dev)
 419 {
 420         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 421
 422         memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
 423         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 424         pcmd->prb.fis.pm_port_c = (1 << 7);
 425         pcmd->prb.fis.command = ATA_CMD_FLUSH;
 426
 427         sil_exec_cmd(dev, pcmd, 0);
 428 }
 429
 430 static void sil_sata_cmd_flush_cache_ext(int dev)
 431 {
 432         struct sil_cmd_block cmdb, *pcmd = &cmdb;
 433
 434         memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
 435         pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 436         pcmd->prb.fis.pm_port_c = (1 << 7);
 437         pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
 438
 439         sil_exec_cmd(dev, pcmd, 0);
 440 }
 441
 442 static void sil_sata_init_wcache(int dev, u16 *id)
 443 {
 444         struct sil_sata *sata = sata_dev_desc[dev].priv;
 445
 446         if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
 447                 sata->wcache = 1;
 448         if (ata_id_has_flush(id))
 449                 sata->flush = 1;
 450         if (ata_id_has_flush_ext(id))
 451                 sata->flush_ext = 1;
 452 }
 453
 454 static int sil_sata_get_wcache(int dev)
 455 {
 456         struct sil_sata *sata = sata_dev_desc[dev].priv;
 457
 458         return sata->wcache;
 459 }
 460
 461 static int sil_sata_get_flush(int dev)
 462 {
 463         struct sil_sata *sata = sata_dev_desc[dev].priv;
 464
 465         return sata->flush;
 466 }
 467
 468 static int sil_sata_get_flush_ext(int dev)
 469 {
 470         struct sil_sata *sata = sata_dev_desc[dev].priv;
 471
 472         return sata->flush_ext;
 473 }
 474
 475 /*
 476  * SATA interface between low level driver and command layer
 477  */
 478 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
 479 {
 480         struct sil_sata *sata = sata_dev_desc[dev].priv;
 481         ulong rc;
 482
 483         if (sata->lba48)
 484                 rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
 485         else
 486                 rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
 487
 488         return rc;
 489 }
 490
 491 /*
 492  * SATA interface between low level driver and command layer
 493  */
 494 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
 495 {
 496         struct sil_sata *sata = sata_dev_desc[dev].priv;
 497         ulong rc;
 498
 499         if (sata->lba48) {
 500                 rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
 501                 if (sil_sata_get_wcache(dev) && sil_sata_get_flush_ext(dev))
 502                         sil_sata_cmd_flush_cache_ext(dev);
 503         } else {
 504                 rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
 505                 if (sil_sata_get_wcache(dev) && sil_sata_get_flush(dev))
 506                         sil_sata_cmd_flush_cache(dev);
 507         }
 508
 509         return rc;
 510 }
 511
 512 /*
 513  * SATA interface between low level driver and command layer
 514  */
 515 int init_sata(int dev)
 516 {
 517         static int init_done, idx;
 518         pci_dev_t devno;
 519         u16 word;
 520
 521         if (init_done == 1 && dev < sata_info.maxport)
 522                 return 1;
 523
 524         init_done = 1;
 525
 526         /* Find PCI device(s) */
 527         devno = pci_find_devices(supported, idx++);
 528         if (devno == -1)
 529                 return 1;
 530
 531         pci_read_config_word(devno, PCI_DEVICE_ID, &word);
 532
 533         /* get the port count */
 534         word &= 0xf;
 535
 536         sata_info.portbase = sata_info.maxport;
 537         sata_info.maxport = sata_info.portbase + word;
 538         sata_info.devno = devno;
 539
 540         /* Read out all BARs */
 541         sata_info.iobase[0] = (ulong)pci_map_bar(devno,
 542                         PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
 543         sata_info.iobase[1] = (ulong)pci_map_bar(devno,
 544                         PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
 545         sata_info.iobase[2] = (ulong)pci_map_bar(devno,
 546                         PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
 547
 548         /* mask out the unused bits */
 549         sata_info.iobase[0] &= 0xffffff80;
 550         sata_info.iobase[1] &= 0xfffffc00;
 551         sata_info.iobase[2] &= 0xffffff80;
 552
 553         /* Enable Bus Mastering and memory region */
 554         pci_write_config_word(devno, PCI_COMMAND,
 555                         PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 556
 557         /* Check if mem accesses and Bus Mastering are enabled. */
 558         pci_read_config_word(devno, PCI_COMMAND, &word);
 559         if (!(word & PCI_COMMAND_MEMORY) ||
 560                         (!(word & PCI_COMMAND_MASTER))) {
 561                 printf("Error: Can not enable MEM access or Bus Mastering.\n");
 562                 debug("PCI command: %04x\n", word);
 563                 return 1;
 564         }
 565
 566         /* GPIO off */
 567         writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
 568         /* clear global reset & mask interrupts during initialization */
 569         writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
 570
 571         return 0;
 572 }
 573
 574 /*
 575  * SATA interface between low level driver and command layer
 576  */
 577 int scan_sata(int dev)
 578 {
 579         unsigned char serial[ATA_ID_SERNO_LEN + 1];
 580         unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
 581         unsigned char product[ATA_ID_PROD_LEN + 1];
 582         struct sil_sata *sata;
 583         void *port;
 584         int cnt;
 585         u16 *id;
 586         u32 tmp;
 587
 588         if (dev >= sata_info.maxport) {
 589                 printf("SATA#%d is not present\n", dev);
 590                 return 1;
 591         }
 592
 593         printf("SATA#%d\n", dev);
 594         port = (void *)sata_info.iobase[1] +
 595                 PORT_REGS_SIZE * (dev - sata_info.portbase);
 596
 597         /* Initial PHY setting */
 598         writel(0x20c, port + PORT_PHY_CFG);
 599
 600         /* clear port RST */
 601         tmp = readl(port + PORT_CTRL_STAT);
 602         if (tmp & PORT_CS_PORT_RST) {
 603                 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
 604                 tmp = ata_wait_register(port + PORT_CTRL_STAT,
 605                                 PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
 606                 if (tmp & PORT_CS_PORT_RST)
 607                         printf("Err: Failed to clear port RST\n");
 608         }
 609
 610         /* Check if device is present */
 611         for (cnt = 0; cnt < 100; cnt++) {
 612                 tmp = readl(port + PORT_SSTATUS);
 613                 if ((tmp & 0xF) == 0x3)
 614                         break;
 615                 mdelay(1);
 616         }
 617
 618         tmp = readl(port + PORT_SSTATUS);
 619         if ((tmp & 0xf) != 0x3) {
 620                 printf("        (No RDY)\n");
 621                 return 1;
 622         }
 623
 624         /* Wait for port ready */
 625         tmp = ata_wait_register(port + PORT_CTRL_STAT,
 626                                 PORT_CS_RDY, PORT_CS_RDY, 100);
 627         if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
 628                 printf("%d port not ready.\n", dev);
 629                 return 1;
 630         }
 631
 632         /* configure port */
 633         sil_config_port(port);
 634
 635         /* Reset port */
 636         writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
 637         readl(port + PORT_CTRL_STAT);
 638         tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
 639                                 PORT_CS_DEV_RST, 100);
 640         if (tmp & PORT_CS_DEV_RST) {
 641                 printf("%d port reset failed.\n", dev);
 642                 return 1;
 643         }
 644
 645         sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
 646         if (!sata) {
 647                 printf("%d no memory.\n", dev);
 648                 return 1;
 649         }
 650         memset((void *)sata, 0, sizeof(struct sil_sata));
 651
 652         /* turn on port interrupt */
 653         tmp = readl((void *)(sata_info.iobase[0] + HOST_CTRL));
 654         tmp |= (1 << (dev - sata_info.portbase));
 655         writel(tmp, (void *)(sata_info.iobase[0] + HOST_CTRL));
 656
 657         /* Save the private struct to block device struct */
 658         sata_dev_desc[dev].priv = (void *)sata;
 659         sata->port = port;
 660         sata->devno = sata_info.devno;
 661         sprintf(sata->name, "SATA#%d", dev);
 662         sil_cmd_soft_reset(dev);
 663         tmp = readl(port + PORT_SSTATUS);
 664         tmp = (tmp >> 4) & 0xf;
 665         printf("        (%s)\n", sata_spd_string(tmp));
 666
 667         id = (u16 *)malloc(ATA_ID_WORDS * 2);
 668         if (!id) {
 669                 printf("Id malloc failed\n");
 670                 free((void *)sata);
 671                 return 1;
 672         }
 673         sil_cmd_identify_device(dev, id);
 674
 675 #ifdef CONFIG_LBA48
 676         /* Check if support LBA48 */
 677         if (ata_id_has_lba48(id)) {
 678                 sata_dev_desc[dev].lba48 = 1;
 679                 sata->lba48 = 1;
 680                 debug("Device supports LBA48\n");
 681         } else
 682                 debug("Device supports LBA28\n");
 683 #endif
 684
 685         /* Serial number */
 686         ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
 687         memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
 688
 689         /* Firmware version */
 690         ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
 691         memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
 692
 693         /* Product model */
 694         ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
 695         memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
 696
 697         /* Totoal sectors */
 698         sata_dev_desc[dev].lba = ata_id_n_sectors(id);
 699
 700         sil_sata_init_wcache(dev, id);
 701         sil_cmd_set_feature(dev);
 702
 703 #ifdef DEBUG
 704         sil_cmd_identify_device(dev, id);
 705         ata_dump_id(id);
 706 #endif
 707         free((void *)id);
 708
 709         return 0;
 710 }