]>
git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/clk/clk-uclass.c
2 * Copyright (C) 2015 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
4 * Copyright (c) 2016, NVIDIA CORPORATION.
5 * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <clk-uclass.h>
15 #include <dt-structs.h>
18 static inline const struct clk_ops
*clk_dev_ops(struct udevice
*dev
)
20 return (const struct clk_ops
*)dev
->driver
->ops
;
23 #if CONFIG_IS_ENABLED(OF_CONTROL)
24 # if CONFIG_IS_ENABLED(OF_PLATDATA)
25 int clk_get_by_index_platdata(struct udevice
*dev
, int index
,
26 struct phandle_1_arg
*cells
, struct clk
*clk
)
32 ret
= uclass_get_device(UCLASS_CLK
, 0, &clk
->dev
);
35 clk
->id
= cells
[0].arg
[0];
40 static int clk_of_xlate_default(struct clk
*clk
,
41 struct ofnode_phandle_args
*args
)
43 debug("%s(clk=%p)\n", __func__
, clk
);
45 if (args
->args_count
> 1) {
46 debug("Invaild args_count: %d\n", args
->args_count
);
51 clk
->id
= args
->args
[0];
58 static int clk_get_by_indexed_prop(struct udevice
*dev
, const char *prop_name
,
59 int index
, struct clk
*clk
)
62 struct ofnode_phandle_args args
;
63 struct udevice
*dev_clk
;
64 const struct clk_ops
*ops
;
66 debug("%s(dev=%p, index=%d, clk=%p)\n", __func__
, dev
, index
, clk
);
71 ret
= dev_read_phandle_with_args(dev
, prop_name
, "#clock-cells", 0,
74 debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
79 ret
= uclass_get_device_by_ofnode(UCLASS_CLK
, args
.node
, &dev_clk
);
81 debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
88 ops
= clk_dev_ops(dev_clk
);
91 ret
= ops
->of_xlate(clk
, &args
);
93 ret
= clk_of_xlate_default(clk
, &args
);
95 debug("of_xlate() failed: %d\n", ret
);
99 return clk_request(dev_clk
, clk
);
102 int clk_get_by_index(struct udevice
*dev
, int index
, struct clk
*clk
)
104 return clk_get_by_indexed_prop(dev
, "clocks", index
, clk
);
107 static int clk_set_default_parents(struct udevice
*dev
)
109 struct clk clk
, parent_clk
;
114 num_parents
= dev_count_phandle_with_args(dev
, "assigned-clock-parents",
116 if (num_parents
< 0) {
117 debug("%s: could not read assigned-clock-parents for %p\n",
122 for (index
= 0; index
< num_parents
; index
++) {
123 ret
= clk_get_by_indexed_prop(dev
, "assigned-clock-parents",
126 debug("%s: could not get parent clock %d for %s\n",
127 __func__
, index
, dev_read_name(dev
));
131 ret
= clk_get_by_indexed_prop(dev
, "assigned-clocks",
134 debug("%s: could not get assigned clock %d for %s\n",
135 __func__
, index
, dev_read_name(dev
));
139 ret
= clk_set_parent(&clk
, &parent_clk
);
142 * Not all drivers may support clock-reparenting (as of now).
143 * Ignore errors due to this.
149 debug("%s: failed to reparent clock %d for %s\n",
150 __func__
, index
, dev_read_name(dev
));
158 static int clk_set_default_rates(struct udevice
*dev
)
167 size
= dev_read_size(dev
, "assigned-clock-rates");
171 num_rates
= size
/ sizeof(u32
);
172 rates
= calloc(num_rates
, sizeof(u32
));
176 ret
= dev_read_u32_array(dev
, "assigned-clock-rates", rates
, num_rates
);
180 for (index
= 0; index
< num_rates
; index
++) {
181 ret
= clk_get_by_indexed_prop(dev
, "assigned-clocks",
184 debug("%s: could not get assigned clock %d for %s\n",
185 __func__
, index
, dev_read_name(dev
));
189 ret
= clk_set_rate(&clk
, rates
[index
]);
191 debug("%s: failed to set rate on clock %d for %s\n",
192 __func__
, index
, dev_read_name(dev
));
202 int clk_set_defaults(struct udevice
*dev
)
206 /* If this is running pre-reloc state, don't take any action. */
207 if (!(gd
->flags
& GD_FLG_RELOC
))
210 debug("%s(%s)\n", __func__
, dev_read_name(dev
));
212 ret
= clk_set_default_parents(dev
);
216 ret
= clk_set_default_rates(dev
);
222 # endif /* OF_PLATDATA */
224 int clk_get_by_name(struct udevice
*dev
, const char *name
, struct clk
*clk
)
228 debug("%s(dev=%p, name=%s, clk=%p)\n", __func__
, dev
, name
, clk
);
231 index
= dev_read_stringlist_search(dev
, "clock-names", name
);
233 debug("fdt_stringlist_search() failed: %d\n", index
);
237 return clk_get_by_index(dev
, index
, clk
);
240 int clk_release_all(struct clk
*clk
, int count
)
244 for (i
= 0; i
< count
; i
++) {
245 debug("%s(clk[%d]=%p)\n", __func__
, i
, &clk
[i
]);
247 /* check if clock has been previously requested */
251 ret
= clk_disable(&clk
[i
]);
252 if (ret
&& ret
!= -ENOSYS
)
255 ret
= clk_free(&clk
[i
]);
256 if (ret
&& ret
!= -ENOSYS
)
263 #endif /* OF_CONTROL */
265 int clk_request(struct udevice
*dev
, struct clk
*clk
)
267 const struct clk_ops
*ops
= clk_dev_ops(dev
);
269 debug("%s(dev=%p, clk=%p)\n", __func__
, dev
, clk
);
276 return ops
->request(clk
);
279 int clk_free(struct clk
*clk
)
281 const struct clk_ops
*ops
= clk_dev_ops(clk
->dev
);
283 debug("%s(clk=%p)\n", __func__
, clk
);
288 return ops
->free(clk
);
291 ulong
clk_get_rate(struct clk
*clk
)
293 const struct clk_ops
*ops
= clk_dev_ops(clk
->dev
);
295 debug("%s(clk=%p)\n", __func__
, clk
);
300 return ops
->get_rate(clk
);
303 ulong
clk_set_rate(struct clk
*clk
, ulong rate
)
305 const struct clk_ops
*ops
= clk_dev_ops(clk
->dev
);
307 debug("%s(clk=%p, rate=%lu)\n", __func__
, clk
, rate
);
312 return ops
->set_rate(clk
, rate
);
315 int clk_set_parent(struct clk
*clk
, struct clk
*parent
)
317 const struct clk_ops
*ops
= clk_dev_ops(clk
->dev
);
319 debug("%s(clk=%p, parent=%p)\n", __func__
, clk
, parent
);
321 if (!ops
->set_parent
)
324 return ops
->set_parent(clk
, parent
);
327 int clk_enable(struct clk
*clk
)
329 const struct clk_ops
*ops
= clk_dev_ops(clk
->dev
);
331 debug("%s(clk=%p)\n", __func__
, clk
);
336 return ops
->enable(clk
);
339 int clk_disable(struct clk
*clk
)
341 const struct clk_ops
*ops
= clk_dev_ops(clk
->dev
);
343 debug("%s(clk=%p)\n", __func__
, clk
);
348 return ops
->disable(clk
);
351 UCLASS_DRIVER(clk
) = {