drivers/clk/clk_fixed_rate.c

   1 /*
   2  * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10
  11 struct clk_fixed_rate {
  12         unsigned long fixed_rate;
  13 };
  14
  15 #define to_clk_fixed_rate(dev)  ((struct clk_fixed_rate *)dev_get_platdata(dev))
  16
  17 static ulong clk_fixed_rate_get_rate(struct clk *clk)
  18 {
  19         if (clk->id != 0)
  20                 return -EINVAL;
  21
  22         return to_clk_fixed_rate(clk->dev)->fixed_rate;
  23 }
  24
  25 const struct clk_ops clk_fixed_rate_ops = {
  26         .get_rate = clk_fixed_rate_get_rate,
  27 };
  28
  29 static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev)
  30 {
  31 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  32         to_clk_fixed_rate(dev)->fixed_rate =
  33                 dev_read_u32_default(dev, "clock-frequency", 0);
  34 #endif
  35
  36         return 0;
  37 }
  38
  39 static const struct udevice_id clk_fixed_rate_match[] = {
  40         {
  41                 .compatible = "fixed-clock",
  42         },
  43         { /* sentinel */ }
  44 };
  45
  46 U_BOOT_DRIVER(clk_fixed_rate) = {
  47         .name = "fixed_rate_clock",
  48         .id = UCLASS_CLK,
  49         .of_match = clk_fixed_rate_match,
  50         .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
  51         .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
  52         .ops = &clk_fixed_rate_ops,
  53 };