2 * (C) Copyright 2015 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/cru_rk3288.h>
15 #include <asm/arch/grf_rk3288.h>
16 #include <asm/arch/hardware.h>
17 #include <dt-bindings/clock/rk3288-cru.h>
18 #include <dm/device-internal.h>
20 #include <dm/uclass-internal.h>
22 DECLARE_GLOBAL_DATA_PTR
;
24 struct rk3288_clk_priv
{
25 struct rk3288_grf
*grf
;
26 struct rk3288_cru
*cru
;
37 VCO_MAX_HZ
= 2200U * 1000000,
38 VCO_MIN_HZ
= 440 * 1000000,
39 OUTPUT_MAX_HZ
= 2200U * 1000000,
40 OUTPUT_MIN_HZ
= 27500000,
41 FREF_MAX_HZ
= 2200U * 1000000,
42 FREF_MIN_HZ
= 269 * 1000000,
53 PLL_BWADJ_MASK
= 0x0fff,
59 CORE_SEL_PLL_MASK
= 1,
60 CORE_SEL_PLL_SHIFT
= 15,
68 /* CLKSEL1: pd bus clk pll sel: codec or general */
69 PD_BUS_SEL_PLL_MASK
= 15,
73 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
74 PD_BUS_PCLK_DIV_SHIFT
= 12,
75 PD_BUS_PCLK_DIV_MASK
= 7,
77 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
78 PD_BUS_HCLK_DIV_SHIFT
= 8,
79 PD_BUS_HCLK_DIV_MASK
= 3,
81 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
82 PD_BUS_ACLK_DIV0_SHIFT
= 3,
83 PD_BUS_ACLK_DIV0_MASK
= 0x1f,
84 PD_BUS_ACLK_DIV1_SHIFT
= 0,
85 PD_BUS_ACLK_DIV1_MASK
= 0x7,
89 * peripheral bus pclk div:
90 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
92 PERI_SEL_PLL_MASK
= 1,
93 PERI_SEL_PLL_SHIFT
= 15,
97 PERI_PCLK_DIV_SHIFT
= 12,
98 PERI_PCLK_DIV_MASK
= 3,
100 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
101 PERI_HCLK_DIV_SHIFT
= 8,
102 PERI_HCLK_DIV_MASK
= 3,
105 * peripheral bus aclk div:
106 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
108 PERI_ACLK_DIV_SHIFT
= 0,
109 PERI_ACLK_DIV_MASK
= 0x1f,
111 SOCSTS_DPLL_LOCK
= 1 << 5,
112 SOCSTS_APLL_LOCK
= 1 << 6,
113 SOCSTS_CPLL_LOCK
= 1 << 7,
114 SOCSTS_GPLL_LOCK
= 1 << 8,
115 SOCSTS_NPLL_LOCK
= 1 << 9,
118 #define RATE_TO_DIV(input_rate, output_rate) \
119 ((input_rate) / (output_rate) - 1);
121 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
123 #define PLL_DIVISORS(hz, _nr, _no) {\
124 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
125 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
126 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
127 "divisors on line " __stringify(__LINE__));
129 /* Keep divisors as low as possible to reduce jitter and power usage */
130 static const struct pll_div apll_init_cfg
= PLL_DIVISORS(APLL_HZ
, 1, 1);
131 static const struct pll_div gpll_init_cfg
= PLL_DIVISORS(GPLL_HZ
, 2, 2);
132 static const struct pll_div cpll_init_cfg
= PLL_DIVISORS(CPLL_HZ
, 1, 2);
134 void *rockchip_get_cru(void)
136 struct rk3288_clk_priv
*priv
;
140 ret
= uclass_get_device(UCLASS_CLK
, 0, &dev
);
144 priv
= dev_get_priv(dev
);
149 static int rkclk_set_pll(struct rk3288_cru
*cru
, enum rk_clk_id clk_id
,
150 const struct pll_div
*div
)
152 int pll_id
= rk_pll_id(clk_id
);
153 struct rk3288_pll
*pll
= &cru
->pll
[pll_id
];
154 /* All PLLs have same VCO and output frequency range restrictions. */
155 uint vco_hz
= OSC_HZ
/ 1000 * div
->nf
/ div
->nr
* 1000;
156 uint output_hz
= vco_hz
/ div
->no
;
158 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
159 (uint
)pll
, div
->nf
, div
->nr
, div
->no
, vco_hz
, output_hz
);
160 assert(vco_hz
>= VCO_MIN_HZ
&& vco_hz
<= VCO_MAX_HZ
&&
161 output_hz
>= OUTPUT_MIN_HZ
&& output_hz
<= OUTPUT_MAX_HZ
&&
162 (div
->no
== 1 || !(div
->no
% 2)));
165 rk_setreg(&pll
->con3
, 1 << PLL_RESET_SHIFT
);
167 rk_clrsetreg(&pll
->con0
,
168 CLKR_MASK
<< CLKR_SHIFT
| PLL_OD_MASK
,
169 ((div
->nr
- 1) << CLKR_SHIFT
) | (div
->no
- 1));
170 rk_clrsetreg(&pll
->con1
, CLKF_MASK
, div
->nf
- 1);
171 rk_clrsetreg(&pll
->con2
, PLL_BWADJ_MASK
, (div
->nf
>> 1) - 1);
175 /* return from reset */
176 rk_clrreg(&pll
->con3
, 1 << PLL_RESET_SHIFT
);
181 static inline unsigned int log2(unsigned int value
)
183 return fls(value
) - 1;
186 static int rkclk_configure_ddr(struct rk3288_cru
*cru
, struct rk3288_grf
*grf
,
189 static const struct pll_div dpll_cfg
[] = {
190 {.nf
= 25, .nr
= 2, .no
= 1},
191 {.nf
= 400, .nr
= 9, .no
= 2},
192 {.nf
= 500, .nr
= 9, .no
= 2},
193 {.nf
= 100, .nr
= 3, .no
= 1},
201 case 533000000: /* actually 533.3P MHz */
204 case 666000000: /* actually 666.6P MHz */
211 debug("Unsupported SDRAM frequency");
215 /* pll enter slow-mode */
216 rk_clrsetreg(&cru
->cru_mode_con
, DPLL_MODE_MASK
<< DPLL_MODE_SHIFT
,
217 DPLL_MODE_SLOW
<< DPLL_MODE_SHIFT
);
219 rkclk_set_pll(cru
, CLK_DDR
, &dpll_cfg
[cfg
]);
221 /* wait for pll lock */
222 while (!(readl(&grf
->soc_status
[1]) & SOCSTS_DPLL_LOCK
))
225 /* PLL enter normal-mode */
226 rk_clrsetreg(&cru
->cru_mode_con
, DPLL_MODE_MASK
<< DPLL_MODE_SHIFT
,
227 DPLL_MODE_NORMAL
<< DPLL_MODE_SHIFT
);
232 #ifndef CONFIG_SPL_BUILD
233 #define VCO_MAX_KHZ 2200000
234 #define VCO_MIN_KHZ 440000
235 #define FREF_MAX_KHZ 2200000
236 #define FREF_MIN_KHZ 269
238 static int pll_para_config(ulong freq_hz
, struct pll_div
*div
, uint
*ext_div
)
240 uint ref_khz
= OSC_HZ
/ 1000, nr
, nf
= 0;
242 uint diff_khz
, best_diff_khz
;
243 const uint max_nr
= 1 << 6, max_nf
= 1 << 12, max_no
= 1 << 4;
246 uint freq_khz
= freq_hz
/ 1000;
249 printf("%s: the frequency can not be 0 Hz\n", __func__
);
253 no
= DIV_ROUND_UP(VCO_MIN_KHZ
, freq_khz
);
255 *ext_div
= DIV_ROUND_UP(no
, max_no
);
256 no
= DIV_ROUND_UP(no
, *ext_div
);
259 /* only even divisors (and 1) are supported */
261 no
= DIV_ROUND_UP(no
, 2) * 2;
263 vco_khz
= freq_khz
* no
;
267 if (vco_khz
< VCO_MIN_KHZ
|| vco_khz
> VCO_MAX_KHZ
|| no
> max_no
) {
268 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
275 best_diff_khz
= vco_khz
;
276 for (nr
= 1; nr
< max_nr
&& best_diff_khz
; nr
++) {
277 fref_khz
= ref_khz
/ nr
;
278 if (fref_khz
< FREF_MIN_KHZ
)
280 if (fref_khz
> FREF_MAX_KHZ
)
283 nf
= vco_khz
/ fref_khz
;
286 diff_khz
= vco_khz
- nf
* fref_khz
;
287 if (nf
+ 1 < max_nf
&& diff_khz
> fref_khz
/ 2) {
289 diff_khz
= fref_khz
- diff_khz
;
292 if (diff_khz
>= best_diff_khz
)
295 best_diff_khz
= diff_khz
;
300 if (best_diff_khz
> 4 * 1000) {
301 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
302 __func__
, freq_hz
, best_diff_khz
* 1000);
309 static int rockchip_mac_set_clk(struct rk3288_cru
*cru
,
310 int periph
, uint freq
)
312 /* Assuming mac_clk is fed by an external clock */
313 rk_clrsetreg(&cru
->cru_clksel_con
[21],
314 RMII_EXTCLK_MASK
<< RMII_EXTCLK_SHIFT
,
315 RMII_EXTCLK_SELECT_EXT_CLK
<< RMII_EXTCLK_SHIFT
);
320 static int rockchip_vop_set_clk(struct rk3288_cru
*cru
, struct rk3288_grf
*grf
,
321 int periph
, unsigned int rate_hz
)
323 struct pll_div npll_config
= {0};
327 ret
= pll_para_config(rate_hz
, &npll_config
, &lcdc_div
);
331 rk_clrsetreg(&cru
->cru_mode_con
, NPLL_MODE_MASK
<< NPLL_MODE_SHIFT
,
332 NPLL_MODE_SLOW
<< NPLL_MODE_SHIFT
);
333 rkclk_set_pll(cru
, CLK_NEW
, &npll_config
);
335 /* waiting for pll lock */
337 if (readl(&grf
->soc_status
[1]) & SOCSTS_NPLL_LOCK
)
342 rk_clrsetreg(&cru
->cru_mode_con
, NPLL_MODE_MASK
<< NPLL_MODE_SHIFT
,
343 NPLL_MODE_NORMAL
<< NPLL_MODE_SHIFT
);
345 /* vop dclk source clk: npll,dclk_div: 1 */
348 rk_clrsetreg(&cru
->cru_clksel_con
[27], 0xff << 8 | 3 << 0,
349 (lcdc_div
- 1) << 8 | 2 << 0);
352 rk_clrsetreg(&cru
->cru_clksel_con
[29], 0xff << 8 | 3 << 6,
353 (lcdc_div
- 1) << 8 | 2 << 6);
361 #ifdef CONFIG_SPL_BUILD
362 static void rkclk_init(struct rk3288_cru
*cru
, struct rk3288_grf
*grf
)
368 /* pll enter slow-mode */
369 rk_clrsetreg(&cru
->cru_mode_con
,
370 GPLL_MODE_MASK
<< GPLL_MODE_SHIFT
|
371 CPLL_MODE_MASK
<< CPLL_MODE_SHIFT
,
372 GPLL_MODE_SLOW
<< GPLL_MODE_SHIFT
|
373 CPLL_MODE_SLOW
<< CPLL_MODE_SHIFT
);
376 rkclk_set_pll(cru
, CLK_GENERAL
, &gpll_init_cfg
);
377 rkclk_set_pll(cru
, CLK_CODEC
, &cpll_init_cfg
);
379 /* waiting for pll lock */
380 while ((readl(&grf
->soc_status
[1]) &
381 (SOCSTS_CPLL_LOCK
| SOCSTS_GPLL_LOCK
)) !=
382 (SOCSTS_CPLL_LOCK
| SOCSTS_GPLL_LOCK
))
386 * pd_bus clock pll source selection and
387 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
389 aclk_div
= GPLL_HZ
/ PD_BUS_ACLK_HZ
- 1;
390 assert((aclk_div
+ 1) * PD_BUS_ACLK_HZ
== GPLL_HZ
&& aclk_div
< 0x1f);
391 hclk_div
= PD_BUS_ACLK_HZ
/ PD_BUS_HCLK_HZ
- 1;
392 assert((hclk_div
+ 1) * PD_BUS_HCLK_HZ
==
393 PD_BUS_ACLK_HZ
&& (hclk_div
< 0x4) && (hclk_div
!= 0x2));
395 pclk_div
= PD_BUS_ACLK_HZ
/ PD_BUS_PCLK_HZ
- 1;
396 assert((pclk_div
+ 1) * PD_BUS_PCLK_HZ
==
397 PD_BUS_ACLK_HZ
&& pclk_div
< 0x7);
399 rk_clrsetreg(&cru
->cru_clksel_con
[1],
400 PD_BUS_PCLK_DIV_MASK
<< PD_BUS_PCLK_DIV_SHIFT
|
401 PD_BUS_HCLK_DIV_MASK
<< PD_BUS_HCLK_DIV_SHIFT
|
402 PD_BUS_ACLK_DIV0_MASK
<< PD_BUS_ACLK_DIV0_SHIFT
|
403 PD_BUS_ACLK_DIV1_MASK
<< PD_BUS_ACLK_DIV1_SHIFT
,
404 pclk_div
<< PD_BUS_PCLK_DIV_SHIFT
|
405 hclk_div
<< PD_BUS_HCLK_DIV_SHIFT
|
406 aclk_div
<< PD_BUS_ACLK_DIV0_SHIFT
|
410 * peri clock pll source selection and
411 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
413 aclk_div
= GPLL_HZ
/ PERI_ACLK_HZ
- 1;
414 assert((aclk_div
+ 1) * PERI_ACLK_HZ
== GPLL_HZ
&& aclk_div
< 0x1f);
416 hclk_div
= log2(PERI_ACLK_HZ
/ PERI_HCLK_HZ
);
417 assert((1 << hclk_div
) * PERI_HCLK_HZ
==
418 PERI_ACLK_HZ
&& (hclk_div
< 0x4));
420 pclk_div
= log2(PERI_ACLK_HZ
/ PERI_PCLK_HZ
);
421 assert((1 << pclk_div
) * PERI_PCLK_HZ
==
422 PERI_ACLK_HZ
&& (pclk_div
< 0x4));
424 rk_clrsetreg(&cru
->cru_clksel_con
[10],
425 PERI_PCLK_DIV_MASK
<< PERI_PCLK_DIV_SHIFT
|
426 PERI_HCLK_DIV_MASK
<< PERI_HCLK_DIV_SHIFT
|
427 PERI_ACLK_DIV_MASK
<< PERI_ACLK_DIV_SHIFT
,
428 PERI_SEL_GPLL
<< PERI_SEL_PLL_SHIFT
|
429 pclk_div
<< PERI_PCLK_DIV_SHIFT
|
430 hclk_div
<< PERI_HCLK_DIV_SHIFT
|
431 aclk_div
<< PERI_ACLK_DIV_SHIFT
);
433 /* PLL enter normal-mode */
434 rk_clrsetreg(&cru
->cru_mode_con
,
435 GPLL_MODE_MASK
<< GPLL_MODE_SHIFT
|
436 CPLL_MODE_MASK
<< CPLL_MODE_SHIFT
,
437 GPLL_MODE_NORMAL
<< GPLL_MODE_SHIFT
|
438 CPLL_MODE_NORMAL
<< CPLL_MODE_SHIFT
);
442 void rkclk_configure_cpu(struct rk3288_cru
*cru
, struct rk3288_grf
*grf
)
444 /* pll enter slow-mode */
445 rk_clrsetreg(&cru
->cru_mode_con
,
446 APLL_MODE_MASK
<< APLL_MODE_SHIFT
,
447 APLL_MODE_SLOW
<< APLL_MODE_SHIFT
);
449 rkclk_set_pll(cru
, CLK_ARM
, &apll_init_cfg
);
451 /* waiting for pll lock */
452 while (!(readl(&grf
->soc_status
[1]) & SOCSTS_APLL_LOCK
))
456 * core clock pll source selection and
457 * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
458 * core clock select apll, apll clk = 1800MHz
459 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
461 rk_clrsetreg(&cru
->cru_clksel_con
[0],
462 CORE_SEL_PLL_MASK
<< CORE_SEL_PLL_SHIFT
|
463 A17_DIV_MASK
<< A17_DIV_SHIFT
|
464 MP_DIV_MASK
<< MP_DIV_SHIFT
|
465 M0_DIV_MASK
<< M0_DIV_SHIFT
,
471 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
472 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
474 rk_clrsetreg(&cru
->cru_clksel_con
[37],
475 CLK_L2RAM_DIV_MASK
<< CLK_L2RAM_DIV_SHIFT
|
476 ATCLK_CORE_DIV_CON_MASK
<< ATCLK_CORE_DIV_CON_SHIFT
|
477 PCLK_CORE_DBG_DIV_MASK
>> PCLK_CORE_DBG_DIV_SHIFT
,
478 1 << CLK_L2RAM_DIV_SHIFT
|
479 3 << ATCLK_CORE_DIV_CON_SHIFT
|
480 3 << PCLK_CORE_DBG_DIV_SHIFT
);
482 /* PLL enter normal-mode */
483 rk_clrsetreg(&cru
->cru_mode_con
,
484 APLL_MODE_MASK
<< APLL_MODE_SHIFT
,
485 APLL_MODE_NORMAL
<< APLL_MODE_SHIFT
);
488 /* Get pll rate by id */
489 static uint32_t rkclk_pll_get_rate(struct rk3288_cru
*cru
,
490 enum rk_clk_id clk_id
)
494 int pll_id
= rk_pll_id(clk_id
);
495 struct rk3288_pll
*pll
= &cru
->pll
[pll_id
];
496 static u8 clk_shift
[CLK_COUNT
] = {
497 0xff, APLL_MODE_SHIFT
, DPLL_MODE_SHIFT
, CPLL_MODE_SHIFT
,
498 GPLL_MODE_SHIFT
, NPLL_MODE_SHIFT
502 con
= readl(&cru
->cru_mode_con
);
503 shift
= clk_shift
[clk_id
];
504 switch ((con
>> shift
) & APLL_MODE_MASK
) {
507 case APLL_MODE_NORMAL
:
509 con
= readl(&pll
->con0
);
510 no
= ((con
>> CLKOD_SHIFT
) & CLKOD_MASK
) + 1;
511 nr
= ((con
>> CLKR_SHIFT
) & CLKR_MASK
) + 1;
512 con
= readl(&pll
->con1
);
513 nf
= ((con
>> CLKF_SHIFT
) & CLKF_MASK
) + 1;
515 return (24 * nf
/ (nr
* no
)) * 1000000;
522 static ulong
rockchip_mmc_get_clk(struct rk3288_cru
*cru
, uint gclk_rate
,
531 con
= readl(&cru
->cru_clksel_con
[12]);
532 mux
= (con
>> EMMC_PLL_SHIFT
) & EMMC_PLL_MASK
;
533 div
= (con
>> EMMC_DIV_SHIFT
) & EMMC_DIV_MASK
;
536 con
= readl(&cru
->cru_clksel_con
[11]);
537 mux
= (con
>> MMC0_PLL_SHIFT
) & MMC0_PLL_MASK
;
538 div
= (con
>> MMC0_DIV_SHIFT
) & MMC0_DIV_MASK
;
541 con
= readl(&cru
->cru_clksel_con
[12]);
542 mux
= (con
>> SDIO0_PLL_SHIFT
) & SDIO0_PLL_MASK
;
543 div
= (con
>> SDIO0_DIV_SHIFT
) & SDIO0_DIV_MASK
;
549 src_rate
= mux
== EMMC_PLL_SELECT_24MHZ
? OSC_HZ
: gclk_rate
;
550 return DIV_TO_RATE(src_rate
, div
);
553 static ulong
rockchip_mmc_set_clk(struct rk3288_cru
*cru
, uint gclk_rate
,
554 int periph
, uint freq
)
559 debug("%s: gclk_rate=%u\n", __func__
, gclk_rate
);
560 src_clk_div
= RATE_TO_DIV(gclk_rate
, freq
);
562 if (src_clk_div
> 0x3f) {
563 src_clk_div
= RATE_TO_DIV(OSC_HZ
, freq
);
564 mux
= EMMC_PLL_SELECT_24MHZ
;
565 assert((int)EMMC_PLL_SELECT_24MHZ
==
566 (int)MMC0_PLL_SELECT_24MHZ
);
568 mux
= EMMC_PLL_SELECT_GENERAL
;
569 assert((int)EMMC_PLL_SELECT_GENERAL
==
570 (int)MMC0_PLL_SELECT_GENERAL
);
574 rk_clrsetreg(&cru
->cru_clksel_con
[12],
575 EMMC_PLL_MASK
<< EMMC_PLL_SHIFT
|
576 EMMC_DIV_MASK
<< EMMC_DIV_SHIFT
,
577 mux
<< EMMC_PLL_SHIFT
|
578 (src_clk_div
- 1) << EMMC_DIV_SHIFT
);
581 rk_clrsetreg(&cru
->cru_clksel_con
[11],
582 MMC0_PLL_MASK
<< MMC0_PLL_SHIFT
|
583 MMC0_DIV_MASK
<< MMC0_DIV_SHIFT
,
584 mux
<< MMC0_PLL_SHIFT
|
585 (src_clk_div
- 1) << MMC0_DIV_SHIFT
);
588 rk_clrsetreg(&cru
->cru_clksel_con
[12],
589 SDIO0_PLL_MASK
<< SDIO0_PLL_SHIFT
|
590 SDIO0_DIV_MASK
<< SDIO0_DIV_SHIFT
,
591 mux
<< SDIO0_PLL_SHIFT
|
592 (src_clk_div
- 1) << SDIO0_DIV_SHIFT
);
598 return rockchip_mmc_get_clk(cru
, gclk_rate
, periph
);
601 static ulong
rockchip_spi_get_clk(struct rk3288_cru
*cru
, uint gclk_rate
,
609 con
= readl(&cru
->cru_clksel_con
[25]);
610 mux
= (con
>> SPI0_PLL_SHIFT
) & SPI0_PLL_MASK
;
611 div
= (con
>> SPI0_DIV_SHIFT
) & SPI0_DIV_MASK
;
614 con
= readl(&cru
->cru_clksel_con
[25]);
615 mux
= (con
>> SPI1_PLL_SHIFT
) & SPI1_PLL_MASK
;
616 div
= (con
>> SPI1_DIV_SHIFT
) & SPI1_DIV_MASK
;
619 con
= readl(&cru
->cru_clksel_con
[39]);
620 mux
= (con
>> SPI2_PLL_SHIFT
) & SPI2_PLL_MASK
;
621 div
= (con
>> SPI2_DIV_SHIFT
) & SPI2_DIV_MASK
;
626 assert(mux
== SPI0_PLL_SELECT_GENERAL
);
628 return DIV_TO_RATE(gclk_rate
, div
);
631 static ulong
rockchip_spi_set_clk(struct rk3288_cru
*cru
, uint gclk_rate
,
632 int periph
, uint freq
)
636 debug("%s: clk_general_rate=%u\n", __func__
, gclk_rate
);
637 src_clk_div
= RATE_TO_DIV(gclk_rate
, freq
);
640 rk_clrsetreg(&cru
->cru_clksel_con
[25],
641 SPI0_PLL_MASK
<< SPI0_PLL_SHIFT
|
642 SPI0_DIV_MASK
<< SPI0_DIV_SHIFT
,
643 SPI0_PLL_SELECT_GENERAL
<< SPI0_PLL_SHIFT
|
644 src_clk_div
<< SPI0_DIV_SHIFT
);
647 rk_clrsetreg(&cru
->cru_clksel_con
[25],
648 SPI1_PLL_MASK
<< SPI1_PLL_SHIFT
|
649 SPI1_DIV_MASK
<< SPI1_DIV_SHIFT
,
650 SPI1_PLL_SELECT_GENERAL
<< SPI1_PLL_SHIFT
|
651 src_clk_div
<< SPI1_DIV_SHIFT
);
654 rk_clrsetreg(&cru
->cru_clksel_con
[39],
655 SPI2_PLL_MASK
<< SPI2_PLL_SHIFT
|
656 SPI2_DIV_MASK
<< SPI2_DIV_SHIFT
,
657 SPI2_PLL_SELECT_GENERAL
<< SPI2_PLL_SHIFT
|
658 src_clk_div
<< SPI2_DIV_SHIFT
);
664 return rockchip_spi_get_clk(cru
, gclk_rate
, periph
);
667 static ulong
rk3288_clk_get_rate(struct clk
*clk
)
669 struct rk3288_clk_priv
*priv
= dev_get_priv(clk
->dev
);
670 ulong new_rate
, gclk_rate
;
672 gclk_rate
= rkclk_pll_get_rate(priv
->cru
, CLK_GENERAL
);
675 new_rate
= rkclk_pll_get_rate(priv
->cru
, clk
->id
);
680 new_rate
= rockchip_mmc_get_clk(priv
->cru
, gclk_rate
, clk
->id
);
685 new_rate
= rockchip_spi_get_clk(priv
->cru
, gclk_rate
, clk
->id
);
701 static ulong
rk3288_clk_set_rate(struct clk
*clk
, ulong rate
)
703 struct rk3288_clk_priv
*priv
= dev_get_priv(clk
->dev
);
704 struct rk3288_cru
*cru
= priv
->cru
;
705 ulong new_rate
, gclk_rate
;
707 gclk_rate
= rkclk_pll_get_rate(priv
->cru
, CLK_GENERAL
);
710 new_rate
= rkclk_configure_ddr(priv
->cru
, priv
->grf
, rate
);
715 new_rate
= rockchip_mmc_set_clk(cru
, gclk_rate
, clk
->id
, rate
);
720 new_rate
= rockchip_spi_set_clk(cru
, gclk_rate
, clk
->id
, rate
);
722 #ifndef CONFIG_SPL_BUILD
724 new_rate
= rockchip_mac_set_clk(priv
->cru
, clk
->id
, rate
);
728 new_rate
= rockchip_vop_set_clk(cru
, priv
->grf
, clk
->id
, rate
);
731 /* clk_edp_24M source: 24M */
732 rk_setreg(&cru
->cru_clksel_con
[28], 1 << 15);
735 rk_setreg(&cru
->cru_clksel_con
[6], 1 << 15);
737 rk_clrreg(&cru
->cru_clksel_con
[6], 1 << 15);
744 /* vop aclk source clk: cpll */
745 div
= CPLL_HZ
/ rate
;
746 assert((div
- 1 < 64) && (div
* rate
== CPLL_HZ
));
750 rk_clrsetreg(&cru
->cru_clksel_con
[31],
752 0 << 6 | (div
- 1) << 0);
755 rk_clrsetreg(&cru
->cru_clksel_con
[31],
757 0 << 14 | (div
- 1) << 8);
764 /* enable pclk hdmi ctrl */
765 rk_clrreg(&cru
->cru_clkgate_con
[16], 1 << 9);
767 /* software reset hdmi */
768 rk_setreg(&cru
->cru_clkgate_con
[7], 1 << 9);
770 rk_clrreg(&cru
->cru_clkgate_con
[7], 1 << 9);
781 static struct clk_ops rk3288_clk_ops
= {
782 .get_rate
= rk3288_clk_get_rate
,
783 .set_rate
= rk3288_clk_set_rate
,
786 static int rk3288_clk_probe(struct udevice
*dev
)
788 struct rk3288_clk_priv
*priv
= dev_get_priv(dev
);
790 priv
->cru
= (struct rk3288_cru
*)dev_get_addr(dev
);
791 priv
->grf
= syscon_get_first_range(ROCKCHIP_SYSCON_GRF
);
792 #ifdef CONFIG_SPL_BUILD
793 rkclk_init(priv
->cru
, priv
->grf
);
799 static int rk3288_clk_bind(struct udevice
*dev
)
803 /* The reset driver does not have a device node, so bind it here */
804 ret
= device_bind_driver(gd
->dm_root
, "rk3288_sysreset", "reset", &dev
);
806 debug("Warning: No RK3288 reset driver: ret=%d\n", ret
);
811 static const struct udevice_id rk3288_clk_ids
[] = {
812 { .compatible
= "rockchip,rk3288-cru" },
816 U_BOOT_DRIVER(clk_rk3288
) = {
817 .name
= "clk_rk3288",
819 .of_match
= rk3288_clk_ids
,
820 .priv_auto_alloc_size
= sizeof(struct rk3288_clk_priv
),
821 .ops
= &rk3288_clk_ops
,
822 .bind
= rk3288_clk_bind
,
823 .probe
= rk3288_clk_probe
,