]> git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/clk/clk_rk3288.c
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
rk3399: add basic soc driver
[people/ms/u-boot.git] / drivers / clk / clk_rk3288.c
1 /*
2 * (C) Copyright 2015 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7 #include <common.h>
8 #include <clk-uclass.h>
9 #include <dm.h>
10 #include <dt-structs.h>
11 #include <errno.h>
12 #include <mapmem.h>
13 #include <syscon.h>
14 #include <asm/io.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/cru_rk3288.h>
17 #include <asm/arch/grf_rk3288.h>
18 #include <asm/arch/hardware.h>
19 #include <dt-bindings/clock/rk3288-cru.h>
20 #include <dm/device-internal.h>
21 #include <dm/lists.h>
22 #include <dm/uclass-internal.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 struct rk3288_clk_plat {
27 #if CONFIG_IS_ENABLED(OF_PLATDATA)
28 struct dtd_rockchip_rk3288_cru dtd;
29 #endif
30 };
31
32 struct rk3288_clk_priv {
33 struct rk3288_grf *grf;
34 struct rk3288_cru *cru;
35 ulong rate;
36 };
37
38 struct pll_div {
39 u32 nr;
40 u32 nf;
41 u32 no;
42 };
43
44 enum {
45 VCO_MAX_HZ = 2200U * 1000000,
46 VCO_MIN_HZ = 440 * 1000000,
47 OUTPUT_MAX_HZ = 2200U * 1000000,
48 OUTPUT_MIN_HZ = 27500000,
49 FREF_MAX_HZ = 2200U * 1000000,
50 FREF_MIN_HZ = 269 * 1000,
51 };
52
53 enum {
54 /* PLL CON0 */
55 PLL_OD_MASK = 0x0f,
56
57 /* PLL CON1 */
58 PLL_NF_MASK = 0x1fff,
59
60 /* PLL CON2 */
61 PLL_BWADJ_MASK = 0x0fff,
62
63 /* PLL CON3 */
64 PLL_RESET_SHIFT = 5,
65
66 /* CLKSEL0 */
67 CORE_SEL_PLL_MASK = 1,
68 CORE_SEL_PLL_SHIFT = 15,
69 A17_DIV_MASK = 0x1f,
70 A17_DIV_SHIFT = 8,
71 MP_DIV_MASK = 0xf,
72 MP_DIV_SHIFT = 4,
73 M0_DIV_MASK = 0xf,
74 M0_DIV_SHIFT = 0,
75
76 /* CLKSEL1: pd bus clk pll sel: codec or general */
77 PD_BUS_SEL_PLL_MASK = 15,
78 PD_BUS_SEL_CPLL = 0,
79 PD_BUS_SEL_GPLL,
80
81 /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
82 PD_BUS_PCLK_DIV_SHIFT = 12,
83 PD_BUS_PCLK_DIV_MASK = 7,
84
85 /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
86 PD_BUS_HCLK_DIV_SHIFT = 8,
87 PD_BUS_HCLK_DIV_MASK = 3,
88
89 /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
90 PD_BUS_ACLK_DIV0_SHIFT = 3,
91 PD_BUS_ACLK_DIV0_MASK = 0x1f,
92 PD_BUS_ACLK_DIV1_SHIFT = 0,
93 PD_BUS_ACLK_DIV1_MASK = 0x7,
94
95 /*
96 * CLKSEL10
97 * peripheral bus pclk div:
98 * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
99 */
100 PERI_SEL_PLL_MASK = 1,
101 PERI_SEL_PLL_SHIFT = 15,
102 PERI_SEL_CPLL = 0,
103 PERI_SEL_GPLL,
104
105 PERI_PCLK_DIV_SHIFT = 12,
106 PERI_PCLK_DIV_MASK = 3,
107
108 /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
109 PERI_HCLK_DIV_SHIFT = 8,
110 PERI_HCLK_DIV_MASK = 3,
111
112 /*
113 * peripheral bus aclk div:
114 * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
115 */
116 PERI_ACLK_DIV_SHIFT = 0,
117 PERI_ACLK_DIV_MASK = 0x1f,
118
119 SOCSTS_DPLL_LOCK = 1 << 5,
120 SOCSTS_APLL_LOCK = 1 << 6,
121 SOCSTS_CPLL_LOCK = 1 << 7,
122 SOCSTS_GPLL_LOCK = 1 << 8,
123 SOCSTS_NPLL_LOCK = 1 << 9,
124 };
125
126 #define RATE_TO_DIV(input_rate, output_rate) \
127 ((input_rate) / (output_rate) - 1);
128
129 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
130
131 #define PLL_DIVISORS(hz, _nr, _no) {\
132 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
133 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
134 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
135 "divisors on line " __stringify(__LINE__));
136
137 /* Keep divisors as low as possible to reduce jitter and power usage */
138 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
139 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
140 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
141
142 void *rockchip_get_cru(void)
143 {
144 struct rk3288_clk_priv *priv;
145 struct udevice *dev;
146 int ret;
147
148 ret = rockchip_get_clk(&dev);
149 if (ret)
150 return ERR_PTR(ret);
151
152 priv = dev_get_priv(dev);
153
154 return priv->cru;
155 }
156
157 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,
158 const struct pll_div *div)
159 {
160 int pll_id = rk_pll_id(clk_id);
161 struct rk3288_pll *pll = &cru->pll[pll_id];
162 /* All PLLs have same VCO and output frequency range restrictions. */
163 uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
164 uint output_hz = vco_hz / div->no;
165
166 debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
167 (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
168 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
169 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
170 (div->no == 1 || !(div->no % 2)));
171
172 /* enter reset */
173 rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
174
175 rk_clrsetreg(&pll->con0,
176 CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK,
177 ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
178 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
179 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
180
181 udelay(10);
182
183 /* return from reset */
184 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
185
186 return 0;
187 }
188
189 static inline unsigned int log2(unsigned int value)
190 {
191 return fls(value) - 1;
192 }
193
194 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,
195 unsigned int hz)
196 {
197 static const struct pll_div dpll_cfg[] = {
198 {.nf = 25, .nr = 2, .no = 1},
199 {.nf = 400, .nr = 9, .no = 2},
200 {.nf = 500, .nr = 9, .no = 2},
201 {.nf = 100, .nr = 3, .no = 1},
202 };
203 int cfg;
204
205 switch (hz) {
206 case 300000000:
207 cfg = 0;
208 break;
209 case 533000000: /* actually 533.3P MHz */
210 cfg = 1;
211 break;
212 case 666000000: /* actually 666.6P MHz */
213 cfg = 2;
214 break;
215 case 800000000:
216 cfg = 3;
217 break;
218 default:
219 debug("Unsupported SDRAM frequency");
220 return -EINVAL;
221 }
222
223 /* pll enter slow-mode */
224 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
225 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
226
227 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
228
229 /* wait for pll lock */
230 while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
231 udelay(1);
232
233 /* PLL enter normal-mode */
234 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
235 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
236
237 return 0;
238 }
239
240 #ifndef CONFIG_SPL_BUILD
241 #define VCO_MAX_KHZ 2200000
242 #define VCO_MIN_KHZ 440000
243 #define FREF_MAX_KHZ 2200000
244 #define FREF_MIN_KHZ 269
245
246 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
247 {
248 uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
249 uint fref_khz;
250 uint diff_khz, best_diff_khz;
251 const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
252 uint vco_khz;
253 uint no = 1;
254 uint freq_khz = freq_hz / 1000;
255
256 if (!freq_hz) {
257 printf("%s: the frequency can not be 0 Hz\n", __func__);
258 return -EINVAL;
259 }
260
261 no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
262 if (ext_div) {
263 *ext_div = DIV_ROUND_UP(no, max_no);
264 no = DIV_ROUND_UP(no, *ext_div);
265 }
266
267 /* only even divisors (and 1) are supported */
268 if (no > 1)
269 no = DIV_ROUND_UP(no, 2) * 2;
270
271 vco_khz = freq_khz * no;
272 if (ext_div)
273 vco_khz *= *ext_div;
274
275 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
276 printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
277 __func__, freq_hz);
278 return -1;
279 }
280
281 div->no = no;
282
283 best_diff_khz = vco_khz;
284 for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
285 fref_khz = ref_khz / nr;
286 if (fref_khz < FREF_MIN_KHZ)
287 break;
288 if (fref_khz > FREF_MAX_KHZ)
289 continue;
290
291 nf = vco_khz / fref_khz;
292 if (nf >= max_nf)
293 continue;
294 diff_khz = vco_khz - nf * fref_khz;
295 if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
296 nf++;
297 diff_khz = fref_khz - diff_khz;
298 }
299
300 if (diff_khz >= best_diff_khz)
301 continue;
302
303 best_diff_khz = diff_khz;
304 div->nr = nr;
305 div->nf = nf;
306 }
307
308 if (best_diff_khz > 4 * 1000) {
309 printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
310 __func__, freq_hz, best_diff_khz * 1000);
311 return -EINVAL;
312 }
313
314 return 0;
315 }
316
317 static int rockchip_mac_set_clk(struct rk3288_cru *cru,
318 int periph, uint freq)
319 {
320 /* Assuming mac_clk is fed by an external clock */
321 rk_clrsetreg(&cru->cru_clksel_con[21],
322 RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
323 RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
324
325 return 0;
326 }
327
328 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
329 int periph, unsigned int rate_hz)
330 {
331 struct pll_div npll_config = {0};
332 u32 lcdc_div;
333 int ret;
334
335 ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
336 if (ret)
337 return ret;
338
339 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
340 NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
341 rkclk_set_pll(cru, CLK_NEW, &npll_config);
342
343 /* waiting for pll lock */
344 while (1) {
345 if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
346 break;
347 udelay(1);
348 }
349
350 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK << NPLL_MODE_SHIFT,
351 NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
352
353 /* vop dclk source clk: npll,dclk_div: 1 */
354 switch (periph) {
355 case DCLK_VOP0:
356 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
357 (lcdc_div - 1) << 8 | 2 << 0);
358 break;
359 case DCLK_VOP1:
360 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
361 (lcdc_div - 1) << 8 | 2 << 6);
362 break;
363 }
364
365 return 0;
366 }
367 #endif
368
369 #ifdef CONFIG_SPL_BUILD
370 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)
371 {
372 u32 aclk_div;
373 u32 hclk_div;
374 u32 pclk_div;
375
376 /* pll enter slow-mode */
377 rk_clrsetreg(&cru->cru_mode_con,
378 GPLL_MODE_MASK << GPLL_MODE_SHIFT |
379 CPLL_MODE_MASK << CPLL_MODE_SHIFT,
380 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
381 CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
382
383 /* init pll */
384 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
385 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
386
387 /* waiting for pll lock */
388 while ((readl(&grf->soc_status[1]) &
389 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
390 (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
391 udelay(1);
392
393 /*
394 * pd_bus clock pll source selection and
395 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
396 */
397 aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
398 assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
399 hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
400 assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
401 PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
402
403 pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
404 assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
405 PD_BUS_ACLK_HZ && pclk_div < 0x7);
406
407 rk_clrsetreg(&cru->cru_clksel_con[1],
408 PD_BUS_PCLK_DIV_MASK << PD_BUS_PCLK_DIV_SHIFT |
409 PD_BUS_HCLK_DIV_MASK << PD_BUS_HCLK_DIV_SHIFT |
410 PD_BUS_ACLK_DIV0_MASK << PD_BUS_ACLK_DIV0_SHIFT |
411 PD_BUS_ACLK_DIV1_MASK << PD_BUS_ACLK_DIV1_SHIFT,
412 pclk_div << PD_BUS_PCLK_DIV_SHIFT |
413 hclk_div << PD_BUS_HCLK_DIV_SHIFT |
414 aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
415 0 << 0);
416
417 /*
418 * peri clock pll source selection and
419 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
420 */
421 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
422 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
423
424 hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ);
425 assert((1 << hclk_div) * PERI_HCLK_HZ ==
426 PERI_ACLK_HZ && (hclk_div < 0x4));
427
428 pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ);
429 assert((1 << pclk_div) * PERI_PCLK_HZ ==
430 PERI_ACLK_HZ && (pclk_div < 0x4));
431
432 rk_clrsetreg(&cru->cru_clksel_con[10],
433 PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT |
434 PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT |
435 PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT,
436 PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
437 pclk_div << PERI_PCLK_DIV_SHIFT |
438 hclk_div << PERI_HCLK_DIV_SHIFT |
439 aclk_div << PERI_ACLK_DIV_SHIFT);
440
441 /* PLL enter normal-mode */
442 rk_clrsetreg(&cru->cru_mode_con,
443 GPLL_MODE_MASK << GPLL_MODE_SHIFT |
444 CPLL_MODE_MASK << CPLL_MODE_SHIFT,
445 GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
446 CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
447 }
448 #endif
449
450 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)
451 {
452 /* pll enter slow-mode */
453 rk_clrsetreg(&cru->cru_mode_con,
454 APLL_MODE_MASK << APLL_MODE_SHIFT,
455 APLL_MODE_SLOW << APLL_MODE_SHIFT);
456
457 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
458
459 /* waiting for pll lock */
460 while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
461 udelay(1);
462
463 /*
464 * core clock pll source selection and
465 * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
466 * core clock select apll, apll clk = 1800MHz
467 * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
468 */
469 rk_clrsetreg(&cru->cru_clksel_con[0],
470 CORE_SEL_PLL_MASK << CORE_SEL_PLL_SHIFT |
471 A17_DIV_MASK << A17_DIV_SHIFT |
472 MP_DIV_MASK << MP_DIV_SHIFT |
473 M0_DIV_MASK << M0_DIV_SHIFT,
474 0 << A17_DIV_SHIFT |
475 3 << MP_DIV_SHIFT |
476 1 << M0_DIV_SHIFT);
477
478 /*
479 * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
480 * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
481 */
482 rk_clrsetreg(&cru->cru_clksel_con[37],
483 CLK_L2RAM_DIV_MASK << CLK_L2RAM_DIV_SHIFT |
484 ATCLK_CORE_DIV_CON_MASK << ATCLK_CORE_DIV_CON_SHIFT |
485 PCLK_CORE_DBG_DIV_MASK >> PCLK_CORE_DBG_DIV_SHIFT,
486 1 << CLK_L2RAM_DIV_SHIFT |
487 3 << ATCLK_CORE_DIV_CON_SHIFT |
488 3 << PCLK_CORE_DBG_DIV_SHIFT);
489
490 /* PLL enter normal-mode */
491 rk_clrsetreg(&cru->cru_mode_con,
492 APLL_MODE_MASK << APLL_MODE_SHIFT,
493 APLL_MODE_NORMAL << APLL_MODE_SHIFT);
494 }
495
496 /* Get pll rate by id */
497 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,
498 enum rk_clk_id clk_id)
499 {
500 uint32_t nr, no, nf;
501 uint32_t con;
502 int pll_id = rk_pll_id(clk_id);
503 struct rk3288_pll *pll = &cru->pll[pll_id];
504 static u8 clk_shift[CLK_COUNT] = {
505 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
506 GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
507 };
508 uint shift;
509
510 con = readl(&cru->cru_mode_con);
511 shift = clk_shift[clk_id];
512 switch ((con >> shift) & APLL_MODE_MASK) {
513 case APLL_MODE_SLOW:
514 return OSC_HZ;
515 case APLL_MODE_NORMAL:
516 /* normal mode */
517 con = readl(&pll->con0);
518 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1;
519 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1;
520 con = readl(&pll->con1);
521 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1;
522
523 return (24 * nf / (nr * no)) * 1000000;
524 case APLL_MODE_DEEP:
525 default:
526 return 32768;
527 }
528 }
529
530 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
531 int periph)
532 {
533 uint src_rate;
534 uint div, mux;
535 u32 con;
536
537 switch (periph) {
538 case HCLK_EMMC:
539 con = readl(&cru->cru_clksel_con[12]);
540 mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
541 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
542 break;
543 case HCLK_SDMMC:
544 con = readl(&cru->cru_clksel_con[11]);
545 mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
546 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
547 break;
548 case HCLK_SDIO0:
549 con = readl(&cru->cru_clksel_con[12]);
550 mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
551 div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
552 break;
553 default:
554 return -EINVAL;
555 }
556
557 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
558 return DIV_TO_RATE(src_rate, div);
559 }
560
561 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
562 int periph, uint freq)
563 {
564 int src_clk_div;
565 int mux;
566
567 debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
568 src_clk_div = RATE_TO_DIV(gclk_rate, freq);
569
570 if (src_clk_div > 0x3f) {
571 src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
572 mux = EMMC_PLL_SELECT_24MHZ;
573 assert((int)EMMC_PLL_SELECT_24MHZ ==
574 (int)MMC0_PLL_SELECT_24MHZ);
575 } else {
576 mux = EMMC_PLL_SELECT_GENERAL;
577 assert((int)EMMC_PLL_SELECT_GENERAL ==
578 (int)MMC0_PLL_SELECT_GENERAL);
579 }
580 switch (periph) {
581 case HCLK_EMMC:
582 rk_clrsetreg(&cru->cru_clksel_con[12],
583 EMMC_PLL_MASK << EMMC_PLL_SHIFT |
584 EMMC_DIV_MASK << EMMC_DIV_SHIFT,
585 mux << EMMC_PLL_SHIFT |
586 (src_clk_div - 1) << EMMC_DIV_SHIFT);
587 break;
588 case HCLK_SDMMC:
589 rk_clrsetreg(&cru->cru_clksel_con[11],
590 MMC0_PLL_MASK << MMC0_PLL_SHIFT |
591 MMC0_DIV_MASK << MMC0_DIV_SHIFT,
592 mux << MMC0_PLL_SHIFT |
593 (src_clk_div - 1) << MMC0_DIV_SHIFT);
594 break;
595 case HCLK_SDIO0:
596 rk_clrsetreg(&cru->cru_clksel_con[12],
597 SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
598 SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
599 mux << SDIO0_PLL_SHIFT |
600 (src_clk_div - 1) << SDIO0_DIV_SHIFT);
601 break;
602 default:
603 return -EINVAL;
604 }
605
606 return rockchip_mmc_get_clk(cru, gclk_rate, periph);
607 }
608
609 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,
610 int periph)
611 {
612 uint div, mux;
613 u32 con;
614
615 switch (periph) {
616 case SCLK_SPI0:
617 con = readl(&cru->cru_clksel_con[25]);
618 mux = (con >> SPI0_PLL_SHIFT) & SPI0_PLL_MASK;
619 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK;
620 break;
621 case SCLK_SPI1:
622 con = readl(&cru->cru_clksel_con[25]);
623 mux = (con >> SPI1_PLL_SHIFT) & SPI1_PLL_MASK;
624 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK;
625 break;
626 case SCLK_SPI2:
627 con = readl(&cru->cru_clksel_con[39]);
628 mux = (con >> SPI2_PLL_SHIFT) & SPI2_PLL_MASK;
629 div = (con >> SPI2_DIV_SHIFT) & SPI2_DIV_MASK;
630 break;
631 default:
632 return -EINVAL;
633 }
634 assert(mux == SPI0_PLL_SELECT_GENERAL);
635
636 return DIV_TO_RATE(gclk_rate, div);
637 }
638
639 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
640 int periph, uint freq)
641 {
642 int src_clk_div;
643
644 debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
645 src_clk_div = RATE_TO_DIV(gclk_rate, freq);
646 switch (periph) {
647 case SCLK_SPI0:
648 rk_clrsetreg(&cru->cru_clksel_con[25],
649 SPI0_PLL_MASK << SPI0_PLL_SHIFT |
650 SPI0_DIV_MASK << SPI0_DIV_SHIFT,
651 SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
652 src_clk_div << SPI0_DIV_SHIFT);
653 break;
654 case SCLK_SPI1:
655 rk_clrsetreg(&cru->cru_clksel_con[25],
656 SPI1_PLL_MASK << SPI1_PLL_SHIFT |
657 SPI1_DIV_MASK << SPI1_DIV_SHIFT,
658 SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
659 src_clk_div << SPI1_DIV_SHIFT);
660 break;
661 case SCLK_SPI2:
662 rk_clrsetreg(&cru->cru_clksel_con[39],
663 SPI2_PLL_MASK << SPI2_PLL_SHIFT |
664 SPI2_DIV_MASK << SPI2_DIV_SHIFT,
665 SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
666 src_clk_div << SPI2_DIV_SHIFT);
667 break;
668 default:
669 return -EINVAL;
670 }
671
672 return rockchip_spi_get_clk(cru, gclk_rate, periph);
673 }
674
675 static ulong rk3288_clk_get_rate(struct clk *clk)
676 {
677 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
678 ulong new_rate, gclk_rate;
679
680 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
681 switch (clk->id) {
682 case 0 ... 63:
683 new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
684 break;
685 case HCLK_EMMC:
686 case HCLK_SDMMC:
687 case HCLK_SDIO0:
688 new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
689 break;
690 case SCLK_SPI0:
691 case SCLK_SPI1:
692 case SCLK_SPI2:
693 new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
694 break;
695 case PCLK_I2C0:
696 case PCLK_I2C1:
697 case PCLK_I2C2:
698 case PCLK_I2C3:
699 case PCLK_I2C4:
700 case PCLK_I2C5:
701 return gclk_rate;
702 default:
703 return -ENOENT;
704 }
705
706 return new_rate;
707 }
708
709 static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
710 {
711 struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
712 struct rk3288_cru *cru = priv->cru;
713 ulong new_rate, gclk_rate;
714
715 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
716 switch (clk->id) {
717 case CLK_DDR:
718 new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
719 break;
720 case HCLK_EMMC:
721 case HCLK_SDMMC:
722 case HCLK_SDIO0:
723 new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
724 break;
725 case SCLK_SPI0:
726 case SCLK_SPI1:
727 case SCLK_SPI2:
728 new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
729 break;
730 #ifndef CONFIG_SPL_BUILD
731 case SCLK_MAC:
732 new_rate = rockchip_mac_set_clk(priv->cru, clk->id, rate);
733 break;
734 case DCLK_VOP0:
735 case DCLK_VOP1:
736 new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
737 break;
738 case SCLK_EDP_24M:
739 /* clk_edp_24M source: 24M */
740 rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
741
742 /* rst edp */
743 rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
744 udelay(1);
745 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
746 new_rate = rate;
747 break;
748 case ACLK_VOP0:
749 case ACLK_VOP1: {
750 u32 div;
751
752 /* vop aclk source clk: cpll */
753 div = CPLL_HZ / rate;
754 assert((div - 1 < 64) && (div * rate == CPLL_HZ));
755
756 switch (clk->id) {
757 case ACLK_VOP0:
758 rk_clrsetreg(&cru->cru_clksel_con[31],
759 3 << 6 | 0x1f << 0,
760 0 << 6 | (div - 1) << 0);
761 break;
762 case ACLK_VOP1:
763 rk_clrsetreg(&cru->cru_clksel_con[31],
764 3 << 14 | 0x1f << 8,
765 0 << 14 | (div - 1) << 8);
766 break;
767 }
768 new_rate = rate;
769 break;
770 }
771 case PCLK_HDMI_CTRL:
772 /* enable pclk hdmi ctrl */
773 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
774
775 /* software reset hdmi */
776 rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
777 udelay(1);
778 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
779 new_rate = rate;
780 break;
781 #endif
782 default:
783 return -ENOENT;
784 }
785
786 return new_rate;
787 }
788
789 static struct clk_ops rk3288_clk_ops = {
790 .get_rate = rk3288_clk_get_rate,
791 .set_rate = rk3288_clk_set_rate,
792 };
793
794 static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)
795 {
796 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
797 struct rk3288_clk_priv *priv = dev_get_priv(dev);
798
799 priv->cru = (struct rk3288_cru *)dev_get_addr(dev);
800 #endif
801
802 return 0;
803 }
804
805 static int rk3288_clk_probe(struct udevice *dev)
806 {
807 struct rk3288_clk_priv *priv = dev_get_priv(dev);
808
809 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
810 if (IS_ERR(priv->grf))
811 return PTR_ERR(priv->grf);
812 #ifdef CONFIG_SPL_BUILD
813 #if CONFIG_IS_ENABLED(OF_PLATDATA)
814 struct rk3288_clk_plat *plat = dev_get_platdata(dev);
815
816 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
817 #endif
818 rkclk_init(priv->cru, priv->grf);
819 #endif
820
821 return 0;
822 }
823
824 static int rk3288_clk_bind(struct udevice *dev)
825 {
826 int ret;
827
828 /* The reset driver does not have a device node, so bind it here */
829 ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
830 if (ret)
831 debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
832
833 return 0;
834 }
835
836 static const struct udevice_id rk3288_clk_ids[] = {
837 { .compatible = "rockchip,rk3288-cru" },
838 { }
839 };
840
841 U_BOOT_DRIVER(rockchip_rk3288_cru) = {
842 .name = "rockchip_rk3288_cru",
843 .id = UCLASS_CLK,
844 .of_match = rk3288_clk_ids,
845 .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv),
846 .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat),
847 .ops = &rk3288_clk_ops,
848 .bind = rk3288_clk_bind,
849 .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata,
850 .probe = rk3288_clk_probe,
851 };
"Das U-Boot" Source Tree